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1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2/*
3 * Wave5 series multi-standard codec IP - helper definitions
4 *
5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
6 */
7
8#ifndef VPUAPI_H_INCLUDED
9#define VPUAPI_H_INCLUDED
10
11#include <linux/idr.h>
12#include <linux/genalloc.h>
13#include <media/v4l2-device.h>
14#include <media/v4l2-mem2mem.h>
15#include <media/v4l2-ctrls.h>
16#include "wave5-vpuerror.h"
17#include "wave5-vpuconfig.h"
18#include "wave5-vdi.h"
19
20enum product_id {
21 PRODUCT_ID_521,
22 PRODUCT_ID_511,
23 PRODUCT_ID_517,
24 PRODUCT_ID_NONE,
25};
26
27struct vpu_attr;
28
29enum vpu_instance_type {
30 VPU_INST_TYPE_DEC = 0,
31 VPU_INST_TYPE_ENC = 1
32};
33
34enum vpu_instance_state {
35 VPU_INST_STATE_NONE = 0,
36 VPU_INST_STATE_OPEN = 1,
37 VPU_INST_STATE_INIT_SEQ = 2,
38 VPU_INST_STATE_PIC_RUN = 3,
39 VPU_INST_STATE_STOP = 4
40};
41
42/* Maximum available on hardware. */
43#define WAVE5_MAX_FBS 32
44
45#define MAX_REG_FRAME (WAVE5_MAX_FBS * 2)
46
47#define WAVE5_DEC_HEVC_BUF_SIZE(_w, _h) (DIV_ROUND_UP(_w, 64) * DIV_ROUND_UP(_h, 64) * 256 + 64)
48#define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80)
49
50#define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32)
51#define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32)
52#define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32)
53#define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128)
54
55/*
56 * common struct and definition
57 */
58enum cod_std {
59 STD_AVC = 0,
60 STD_HEVC = 12,
61 STD_MAX
62};
63
64enum wave_std {
65 W_HEVC_DEC = 0x00,
66 W_HEVC_ENC = 0x01,
67 W_AVC_DEC = 0x02,
68 W_AVC_ENC = 0x03,
69 STD_UNKNOWN = 0xFF
70};
71
72enum set_param_option {
73 OPT_COMMON = 0, /* SET_PARAM command option for encoding sequence */
74 OPT_CUSTOM_GOP = 1, /* SET_PARAM command option for setting custom GOP */
75 OPT_CUSTOM_HEADER = 2, /* SET_PARAM command option for setting custom VPS/SPS/PPS */
76 OPT_VUI = 3, /* SET_PARAM command option for encoding VUI */
77 OPT_CHANGE_PARAM = 0x10,
78};
79
80/************************************************************************/
81/* PROFILE & LEVEL */
82/************************************************************************/
83/* HEVC */
84#define HEVC_PROFILE_MAIN 1
85#define HEVC_PROFILE_MAIN10 2
86#define HEVC_PROFILE_STILLPICTURE 3
87#define HEVC_PROFILE_MAIN10_STILLPICTURE 2
88
89/* H.264 profile for encoder*/
90#define H264_PROFILE_BP 1
91#define H264_PROFILE_MP 2
92#define H264_PROFILE_EXTENDED 3
93#define H264_PROFILE_HP 4
94#define H264_PROFILE_HIGH10 5
95#define H264_PROFILE_HIGH422 6
96#define H264_PROFILE_HIGH444 7
97
98/************************************************************************/
99/* error codes */
100/************************************************************************/
101
102/************************************************************************/
103/* utility macros */
104/************************************************************************/
105
106/* Initialize sequence firmware command mode */
107#define INIT_SEQ_NORMAL 1
108
109/* Decode firmware command mode */
110#define DEC_PIC_NORMAL 0
111
112/* bit_alloc_mode */
113#define BIT_ALLOC_MODE_FIXED_RATIO 2
114
115/* bit_rate */
116#define MAX_BIT_RATE 700000000
117
118/* decoding_refresh_type */
119#define DEC_REFRESH_TYPE_NON_IRAP 0
120#define DEC_REFRESH_TYPE_CRA 1
121#define DEC_REFRESH_TYPE_IDR 2
122
123/* depend_slice_mode */
124#define DEPEND_SLICE_MODE_RECOMMENDED 1
125#define DEPEND_SLICE_MODE_BOOST 2
126#define DEPEND_SLICE_MODE_FAST 3
127
128/* hvs_max_delta_qp */
129#define MAX_HVS_MAX_DELTA_QP 51
130
131/* intra_refresh_mode */
132#define REFRESH_MODE_CTU_ROWS 1
133#define REFRESH_MODE_CTU_COLUMNS 2
134#define REFRESH_MODE_CTU_STEP_SIZE 3
135#define REFRESH_MODE_CTUS 4
136
137/* intra_mb_refresh_mode */
138#define REFRESH_MB_MODE_NONE 0
139#define REFRESH_MB_MODE_CTU_ROWS 1
140#define REFRESH_MB_MODE_CTU_COLUMNS 2
141#define REFRESH_MB_MODE_CTU_STEP_SIZE 3
142
143/* intra_qp */
144#define MAX_INTRA_QP 63
145
146/* nr_inter_weight_* */
147#define MAX_INTER_WEIGHT 31
148
149/* nr_intra_weight_* */
150#define MAX_INTRA_WEIGHT 31
151
152/* nr_noise_sigma_* */
153#define MAX_NOISE_SIGMA 255
154
155/* bitstream_buffer_size */
156#define MIN_BITSTREAM_BUFFER_SIZE 1024
157#define MIN_BITSTREAM_BUFFER_SIZE_WAVE521 (1024 * 64)
158
159/* vbv_buffer_size */
160#define MIN_VBV_BUFFER_SIZE 10
161#define MAX_VBV_BUFFER_SIZE 3000
162
163#define BUFFER_MARGIN 4096
164
165#define MAX_FIRMWARE_CALL_RETRY 10
166
167#define VDI_LITTLE_ENDIAN 0x0
168
169/*
170 * Parameters of DEC_SET_SEQ_CHANGE_MASK
171 */
172#define SEQ_CHANGE_ENABLE_PROFILE BIT(5)
173#define SEQ_CHANGE_ENABLE_SIZE BIT(16)
174#define SEQ_CHANGE_ENABLE_BITDEPTH BIT(18)
175#define SEQ_CHANGE_ENABLE_DPB_COUNT BIT(19)
176#define SEQ_CHANGE_ENABLE_ASPECT_RATIO BIT(21)
177#define SEQ_CHANGE_ENABLE_VIDEO_SIGNAL BIT(23)
178#define SEQ_CHANGE_ENABLE_VUI_TIMING_INFO BIT(29)
179
180#define SEQ_CHANGE_ENABLE_ALL_HEVC (SEQ_CHANGE_ENABLE_PROFILE | \
181 SEQ_CHANGE_ENABLE_SIZE | \
182 SEQ_CHANGE_ENABLE_BITDEPTH | \
183 SEQ_CHANGE_ENABLE_DPB_COUNT)
184
185#define SEQ_CHANGE_ENABLE_ALL_AVC (SEQ_CHANGE_ENABLE_SIZE | \
186 SEQ_CHANGE_ENABLE_BITDEPTH | \
187 SEQ_CHANGE_ENABLE_DPB_COUNT | \
188 SEQ_CHANGE_ENABLE_ASPECT_RATIO | \
189 SEQ_CHANGE_ENABLE_VIDEO_SIGNAL | \
190 SEQ_CHANGE_ENABLE_VUI_TIMING_INFO)
191
192#define DISPLAY_IDX_FLAG_SEQ_END -1
193#define DISPLAY_IDX_FLAG_NO_FB -3
194#define DECODED_IDX_FLAG_NO_FB -1
195#define DECODED_IDX_FLAG_SKIP -2
196
197#define RECON_IDX_FLAG_ENC_END -1
198#define RECON_IDX_FLAG_ENC_DELAY -2
199#define RECON_IDX_FLAG_HEADER_ONLY -3
200#define RECON_IDX_FLAG_CHANGE_PARAM -4
201
202enum codec_command {
203 ENABLE_ROTATION,
204 ENABLE_MIRRORING,
205 SET_MIRROR_DIRECTION,
206 SET_ROTATION_ANGLE,
207 DEC_GET_QUEUE_STATUS,
208 ENC_GET_QUEUE_STATUS,
209 DEC_RESET_FRAMEBUF_INFO,
210 DEC_GET_SEQ_INFO,
211};
212
213enum mirror_direction {
214 MIRDIR_NONE, /* no mirroring */
215 MIRDIR_VER, /* vertical mirroring */
216 MIRDIR_HOR, /* horizontal mirroring */
217 MIRDIR_HOR_VER /* horizontal and vertical mirroring */
218};
219
220enum frame_buffer_format {
221 FORMAT_ERR = -1,
222 FORMAT_420 = 0, /* 8bit */
223 FORMAT_422, /* 8bit */
224 FORMAT_224, /* 8bit */
225 FORMAT_444, /* 8bit */
226 FORMAT_400, /* 8bit */
227
228 /* little endian perspective */
229 /* | addr 0 | addr 1 | */
230 FORMAT_420_P10_16BIT_MSB = 5, /* lsb |000000xx|xxxxxxxx | msb */
231 FORMAT_420_P10_16BIT_LSB, /* lsb |xxxxxxx |xx000000 | msb */
232 FORMAT_420_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */
233 FORMAT_420_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */
234
235 /* 4:2:2 packed format */
236 /* little endian perspective */
237 /* | addr 0 | addr 1 | */
238 FORMAT_422_P10_16BIT_MSB, /* lsb |000000xx |xxxxxxxx | msb */
239 FORMAT_422_P10_16BIT_LSB, /* lsb |xxxxxxxx |xx000000 | msb */
240 FORMAT_422_P10_32BIT_MSB, /* lsb |00xxxxxxxxxxxxxxxxxxxxxxxxxxx| msb */
241 FORMAT_422_P10_32BIT_LSB, /* lsb |xxxxxxxxxxxxxxxxxxxxxxxxxxx00| msb */
242
243 FORMAT_YUYV, /* 8bit packed format : Y0U0Y1V0 Y2U1Y3V1 ... */
244 FORMAT_YUYV_P10_16BIT_MSB,
245 FORMAT_YUYV_P10_16BIT_LSB,
246 FORMAT_YUYV_P10_32BIT_MSB,
247 FORMAT_YUYV_P10_32BIT_LSB,
248
249 FORMAT_YVYU, /* 8bit packed format : Y0V0Y1U0 Y2V1Y3U1 ... */
250 FORMAT_YVYU_P10_16BIT_MSB,
251 FORMAT_YVYU_P10_16BIT_LSB,
252 FORMAT_YVYU_P10_32BIT_MSB,
253 FORMAT_YVYU_P10_32BIT_LSB,
254
255 FORMAT_UYVY, /* 8bit packed format : U0Y0V0Y1 U1Y2V1Y3 ... */
256 FORMAT_UYVY_P10_16BIT_MSB,
257 FORMAT_UYVY_P10_16BIT_LSB,
258 FORMAT_UYVY_P10_32BIT_MSB,
259 FORMAT_UYVY_P10_32BIT_LSB,
260
261 FORMAT_VYUY, /* 8bit packed format : V0Y0U0Y1 V1Y2U1Y3 ... */
262 FORMAT_VYUY_P10_16BIT_MSB,
263 FORMAT_VYUY_P10_16BIT_LSB,
264 FORMAT_VYUY_P10_32BIT_MSB,
265 FORMAT_VYUY_P10_32BIT_LSB,
266
267 FORMAT_MAX,
268};
269
270enum packed_format_num {
271 NOT_PACKED = 0,
272 PACKED_YUYV,
273 PACKED_YVYU,
274 PACKED_UYVY,
275 PACKED_VYUY,
276};
277
278enum wave5_interrupt_bit {
279 INT_WAVE5_INIT_VPU = 0,
280 INT_WAVE5_WAKEUP_VPU = 1,
281 INT_WAVE5_SLEEP_VPU = 2,
282 INT_WAVE5_CREATE_INSTANCE = 3,
283 INT_WAVE5_FLUSH_INSTANCE = 4,
284 INT_WAVE5_DESTROY_INSTANCE = 5,
285 INT_WAVE5_INIT_SEQ = 6,
286 INT_WAVE5_SET_FRAMEBUF = 7,
287 INT_WAVE5_DEC_PIC = 8,
288 INT_WAVE5_ENC_PIC = 8,
289 INT_WAVE5_ENC_SET_PARAM = 9,
290 INT_WAVE5_DEC_QUERY = 14,
291 INT_WAVE5_BSBUF_EMPTY = 15,
292 INT_WAVE5_BSBUF_FULL = 15,
293};
294
295enum pic_type {
296 PIC_TYPE_I = 0,
297 PIC_TYPE_P = 1,
298 PIC_TYPE_B = 2,
299 PIC_TYPE_IDR = 5, /* H.264/H.265 IDR (Instantaneous Decoder Refresh) picture */
300 PIC_TYPE_MAX /* no meaning */
301};
302
303enum sw_reset_mode {
304 SW_RESET_SAFETY,
305 SW_RESET_FORCE,
306 SW_RESET_ON_BOOT
307};
308
309enum tiled_map_type {
310 LINEAR_FRAME_MAP = 0, /* linear frame map type */
311 COMPRESSED_FRAME_MAP = 17, /* compressed frame map type*/
312};
313
314enum temporal_id_mode {
315 TEMPORAL_ID_MODE_ABSOLUTE,
316 TEMPORAL_ID_MODE_RELATIVE,
317};
318
319struct vpu_attr {
320 u32 product_id;
321 char product_name[8]; /* product name in ascii code */
322 u32 product_version;
323 u32 fw_version;
324 u32 customer_id;
325 u32 support_decoders; /* bitmask */
326 u32 support_encoders; /* bitmask */
327 u32 support_backbone: 1;
328 u32 support_avc10bit_enc: 1;
329 u32 support_hevc10bit_enc: 1;
330 u32 support_vcore_backbone: 1;
331 u32 support_vcpu_backbone: 1;
332};
333
334struct frame_buffer {
335 dma_addr_t buf_y;
336 dma_addr_t buf_cb;
337 dma_addr_t buf_cr;
338 unsigned int buf_y_size;
339 unsigned int buf_cb_size;
340 unsigned int buf_cr_size;
341 enum tiled_map_type map_type;
342 unsigned int stride; /* horizontal stride for the given frame buffer */
343 unsigned int width; /* width of the given frame buffer */
344 unsigned int height; /* height of the given frame buffer */
345 size_t size; /* size of the given frame buffer */
346 unsigned int sequence_no;
347 bool update_fb_info;
348};
349
350struct vpu_rect {
351 unsigned int left; /* horizontal pixel offset from left edge */
352 unsigned int top; /* vertical pixel offset from top edge */
353 unsigned int right; /* horizontal pixel offset from right edge */
354 unsigned int bottom; /* vertical pixel offset from bottom edge */
355};
356
357/*
358 * decode struct and definition
359 */
360
361struct dec_open_param {
362 dma_addr_t bitstream_buffer;
363 size_t bitstream_buffer_size;
364};
365
366struct dec_initial_info {
367 u32 pic_width;
368 u32 pic_height;
369 struct vpu_rect pic_crop_rect;
370 u32 min_frame_buffer_count; /* between 1 to 16 */
371
372 u32 profile;
373 u32 luma_bitdepth; /* bit-depth of the luma sample */
374 u32 chroma_bitdepth; /* bit-depth of the chroma sample */
375 u32 seq_init_err_reason;
376 dma_addr_t rd_ptr; /* read pointer of bitstream buffer */
377 dma_addr_t wr_ptr; /* write pointer of bitstream buffer */
378 u32 sequence_no;
379 u32 vlc_buf_size;
380 u32 param_buf_size;
381};
382
383struct dec_output_info {
384 /**
385 * This is a frame buffer index for the picture to be displayed at the moment
386 * among frame buffers which are registered using vpu_dec_register_frame_buffer().
387 * Frame data that will be displayed is stored in the frame buffer with this index
388 * When there is no display delay, this index is always the equal to
389 * index_frame_decoded, however, if displaying is delayed (for display
390 * reordering in AVC or B-frames in VC1), this index might be different to
391 * index_frame_decoded. By checking this index, HOST applications can easily figure
392 * out whether sequence decoding has been finished or not.
393 *
394 * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture
395 * reordering or skip option
396 * -1(0xFFFF) : when there is no more output for display at the end of sequence
397 * decoding
398 */
399 s32 index_frame_display;
400 /**
401 * This is the frame buffer index of the decoded picture among the frame buffers which were
402 * registered using vpu_dec_register_frame_buffer(). The currently decoded frame is stored
403 * into the frame buffer specified by this index.
404 *
405 * -2 : indicates that no decoded output is generated because decoder meets EOS
406 * (end of sequence) or skip
407 * -1 : indicates that the decoder fails to decode a picture because there is no available
408 * frame buffer
409 */
410 s32 index_frame_decoded;
411 s32 index_frame_decoded_for_tiled;
412 u32 nal_type;
413 unsigned int pic_type;
414 struct vpu_rect rc_display;
415 unsigned int disp_pic_width;
416 unsigned int disp_pic_height;
417 struct vpu_rect rc_decoded;
418 u32 dec_pic_width;
419 u32 dec_pic_height;
420 s32 decoded_poc;
421 int temporal_id; /* temporal ID of the picture */
422 dma_addr_t rd_ptr; /* stream buffer read pointer for the current decoder instance */
423 dma_addr_t wr_ptr; /* stream buffer write pointer for the current decoder instance */
424 struct frame_buffer disp_frame;
425 u32 frame_display_flag; /* it reports a frame buffer flag to be displayed */
426 /**
427 * this variable reports that sequence has been changed while H.264/AVC stream decoding.
428 * if it is 1, HOST application can get the new sequence information by calling
429 * vpu_dec_get_initial_info() or wave5_vpu_dec_issue_seq_init().
430 *
431 * for H.265/HEVC decoder, each bit has a different meaning as follows.
432 *
433 * sequence_changed[5] : it indicates that the profile_idc has been changed
434 * sequence_changed[16] : it indicates that the resolution has been changed
435 * sequence_changed[19] : it indicates that the required number of frame buffer has
436 * been changed.
437 */
438 unsigned int frame_cycle; /* reports the number of cycles for processing a frame */
439 u32 sequence_no;
440
441 u32 dec_host_cmd_tick; /* tick of DEC_PIC command for the picture */
442 u32 dec_decode_end_tick; /* end tick of decoding slices of the picture */
443
444 u32 sequence_changed;
445};
446
447struct queue_status_info {
448 u32 instance_queue_count;
449 u32 report_queue_count;
450};
451
452/*
453 * encode struct and definition
454 */
455
456#define MAX_NUM_TEMPORAL_LAYER 7
457#define MAX_NUM_SPATIAL_LAYER 3
458#define MAX_GOP_NUM 8
459
460struct custom_gop_pic_param {
461 u32 pic_type; /* picture type of nth picture in the custom GOP */
462 u32 poc_offset; /* POC of nth picture in the custom GOP */
463 u32 pic_qp; /* quantization parameter of nth picture in the custom GOP */
464 u32 use_multi_ref_p; /* use multiref pic for P picture. valid only if PIC_TYPE is P */
465 u32 ref_poc_l0; /* POC of reference L0 of nth picture in the custom GOP */
466 u32 ref_poc_l1; /* POC of reference L1 of nth picture in the custom GOP */
467 s32 temporal_id; /* temporal ID of nth picture in the custom GOP */
468};
469
470struct enc_wave_param {
471 /*
472 * profile indicator (HEVC only)
473 *
474 * 0 : the firmware determines a profile according to the internal_bit_depth
475 * 1 : main profile
476 * 2 : main10 profile
477 * 3 : main still picture profile
478 * In the AVC encoder, a profile cannot be set by the host application.
479 * The firmware decides it based on internal_bit_depth.
480 * profile = HIGH (bitdepth 8) profile = HIGH10 (bitdepth 10)
481 */
482 u32 profile;
483 u32 level; /* level indicator (level * 10) */
484 u32 internal_bit_depth: 4; /* 8/10 */
485 u32 gop_preset_idx: 4; /* 0 - 9 */
486 u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */
487 u32 intra_qp; /* quantization parameter of intra picture */
488 u32 intra_period; /* period of intra picture in GOP size */
489 u32 conf_win_top; /* top offset of conformance window */
490 u32 conf_win_bot; /* bottom offset of conformance window */
491 u32 conf_win_left; /* left offset of conformance window */
492 u32 conf_win_right; /* right offset of conformance window */
493 u32 intra_refresh_mode: 3;
494 /*
495 * Argument for intra_ctu_refresh_mode.
496 *
497 * Depending on intra_refresh_mode, it can mean one of the following:
498 * - intra_ctu_refresh_mode (1) -> number of consecutive CTU rows
499 * - intra_ctu_refresh_mode (2) -> the number of consecutive CTU columns
500 * - intra_ctu_refresh_mode (3) -> step size in CTU
501 * - intra_ctu_refresh_mode (4) -> number of intra ct_us to be encoded in a picture
502 */
503 u32 intra_refresh_arg;
504 /*
505 * 0 : custom setting
506 * 1 : recommended encoder parameters (slow encoding speed, highest picture quality)
507 * 2 : boost mode (normal encoding speed, moderate picture quality)
508 * 3 : fast mode (fast encoding speed, low picture quality)
509 */
510 u32 depend_slice_mode : 2;
511 u32 depend_slice_mode_arg;
512 u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/
513 u32 independ_slice_mode_arg;
514 u32 max_num_merge: 2;
515 s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */
516 s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */
517 u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */
518 u32 hvs_max_delta_qp; /* maximum delta QP for HVS */
519 s32 chroma_cb_qp_offset; /* the value of chroma(cb) QP offset */
520 s32 chroma_cr_qp_offset; /* the value of chroma(cr) QP offset */
521 s32 initial_rc_qp;
522 u32 nr_intra_weight_y;
523 u32 nr_intra_weight_cb; /* weight to cb noise level for intra picture (0 ~ 31) */
524 u32 nr_intra_weight_cr; /* weight to cr noise level for intra picture (0 ~ 31) */
525 u32 nr_inter_weight_y;
526 u32 nr_inter_weight_cb; /* weight to cb noise level for inter picture (0 ~ 31) */
527 u32 nr_inter_weight_cr; /* weight to cr noise level for inter picture (0 ~ 31) */
528 u32 min_qp_i; /* minimum QP of I picture for rate control */
529 u32 max_qp_i; /* maximum QP of I picture for rate control */
530 u32 min_qp_p; /* minimum QP of P picture for rate control */
531 u32 max_qp_p; /* maximum QP of P picture for rate control */
532 u32 min_qp_b; /* minimum QP of B picture for rate control */
533 u32 max_qp_b; /* maximum QP of B picture for rate control */
534 u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */
535 u32 avc_slice_arg; /* the number of MB for a slice when avc_slice_mode is set with 1 */
536 u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */
537 /**
538 * Argument for intra_mb_refresh_mode.
539 *
540 * intra_mb_refresh_mode (1) -> number of consecutive MB rows
541 * intra_mb_refresh_mode (2) ->the number of consecutive MB columns
542 * intra_mb_refresh_mode (3) -> step size in MB
543 */
544 u32 intra_mb_refresh_arg;
545 u32 rc_weight_param;
546 u32 rc_weight_buf;
547
548 /* flags */
549 u32 en_still_picture: 1; /* still picture profile */
550 u32 tier: 1; /* 0=main, 1=high */
551 u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */
552 u32 entropy_coding_mode: 1; /* 0=CAVLC, 1=CABAC */
553 u32 lossless_enable: 1; /* enable lossless encoding */
554 u32 const_intra_pred_flag: 1; /* enable constrained intra prediction */
555 u32 tmvp_enable: 1; /* enable temporal motion vector prediction */
556 u32 wpp_enable: 1;
557 u32 disable_deblk: 1; /* disable in-loop deblocking filtering */
558 u32 lf_cross_slice_boundary_enable: 1;
559 u32 skip_intra_trans: 1;
560 u32 sao_enable: 1; /* enable SAO (sample adaptive offset) */
561 u32 intra_nx_n_enable: 1; /* enables intra nx_n p_us */
562 u32 cu_level_rc_enable: 1; /* enable CU level rate control */
563 u32 hvs_qp_enable: 1; /* enable CU QP adjustment for subjective quality enhancement */
564 u32 strong_intra_smooth_enable: 1; /* enable strong intra smoothing */
565 u32 rdo_skip: 1; /* skip RDO (rate distortion optimization) */
566 u32 lambda_scaling_enable: 1; /* enable lambda scaling using custom GOP */
567 u32 transform8x8_enable: 1; /* enable 8x8 intra prediction and 8x8 transform */
568 u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
569};
570
571struct enc_open_param {
572 dma_addr_t bitstream_buffer;
573 unsigned int bitstream_buffer_size;
574 u32 pic_width; /* width of a picture to be encoded in unit of sample */
575 u32 pic_height; /* height of a picture to be encoded in unit of sample */
576 u32 frame_rate_info;/* desired fps */
577 u32 vbv_buffer_size;
578 u32 bit_rate; /* target bitrate in bps */
579 struct enc_wave_param wave_param;
580 enum packed_format_num packed_format; /* <<vpuapi_h_packed_format_num>> */
581 enum frame_buffer_format src_format;
582 bool line_buf_int_en;
583 u32 rc_enable : 1; /* rate control */
584};
585
586struct enc_initial_info {
587 u32 min_frame_buffer_count; /* minimum number of frame buffers */
588 u32 min_src_frame_count; /* minimum number of source buffers */
589 u32 seq_init_err_reason;
590 u32 warn_info;
591 u32 vlc_buf_size; /* size of task buffer */
592 u32 param_buf_size; /* size of task buffer */
593};
594
595/*
596 * Flags to encode NAL units explicitly
597 */
598struct enc_code_opt {
599 u32 implicit_header_encode: 1;
600 u32 encode_vcl: 1;
601 u32 encode_vps: 1;
602 u32 encode_sps: 1;
603 u32 encode_pps: 1;
604 u32 encode_aud: 1;
605 u32 encode_eos: 1;
606 u32 encode_eob: 1;
607 u32 encode_vui: 1;
608};
609
610struct enc_param {
611 struct frame_buffer *source_frame;
612 u32 pic_stream_buffer_addr;
613 u64 pic_stream_buffer_size;
614 u32 src_idx; /* source frame buffer index */
615 struct enc_code_opt code_option;
616 u64 pts; /* presentation timestamp (PTS) of the input source */
617 bool src_end_flag;
618};
619
620struct enc_output_info {
621 u32 bitstream_buffer;
622 u32 bitstream_size; /* byte size of encoded bitstream */
623 u32 pic_type: 2; /* <<vpuapi_h_pic_type>> */
624 s32 recon_frame_index;
625 dma_addr_t rd_ptr;
626 dma_addr_t wr_ptr;
627 u32 enc_pic_byte; /* number of encoded picture bytes */
628 s32 enc_src_idx; /* source buffer index of the currently encoded picture */
629 u32 enc_vcl_nut;
630 u32 error_reason; /* error reason of the currently encoded picture */
631 u32 warn_info; /* warning information on the currently encoded picture */
632 unsigned int frame_cycle; /* param for reporting the cycle number of encoding one frame*/
633 u64 pts;
634 u32 enc_host_cmd_tick; /* tick of ENC_PIC command for the picture */
635 u32 enc_encode_end_tick; /* end tick of encoding slices of the picture */
636};
637
638enum enc_pic_code_option {
639 CODEOPT_ENC_HEADER_IMPLICIT = BIT(0),
640 CODEOPT_ENC_VCL = BIT(1), /* flag to encode VCL nal unit explicitly */
641};
642
643enum gop_preset_idx {
644 PRESET_IDX_CUSTOM_GOP = 0, /* user defined GOP structure */
645 PRESET_IDX_ALL_I = 1, /* all intra, gopsize = 1 */
646 PRESET_IDX_IPP = 2, /* consecutive P, cyclic gopsize = 1 */
647 PRESET_IDX_IBBB = 3, /* consecutive B, cyclic gopsize = 1 */
648 PRESET_IDX_IBPBP = 4, /* gopsize = 2 */
649 PRESET_IDX_IBBBP = 5, /* gopsize = 4 */
650 PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */
651 PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */
652 PRESET_IDX_RA_IB = 8, /* random access, cyclic gopsize = 8 */
653 PRESET_IDX_IPP_SINGLE = 9, /* consecutive P, cyclic gopsize = 1, with single ref */
654};
655
656struct sec_axi_info {
657 u32 use_ip_enable;
658 u32 use_bit_enable;
659 u32 use_lf_row_enable: 1;
660 u32 use_enc_rdo_enable: 1;
661 u32 use_enc_lf_enable: 1;
662};
663
664struct dec_info {
665 struct dec_open_param open_param;
666 struct dec_initial_info initial_info;
667 struct dec_initial_info new_seq_info; /* temporal new sequence information */
668 u32 stream_wr_ptr;
669 u32 stream_rd_ptr;
670 u32 frame_display_flag;
671 dma_addr_t stream_buf_start_addr;
672 dma_addr_t stream_buf_end_addr;
673 u32 stream_buf_size;
674 struct vpu_buf vb_mv[MAX_REG_FRAME];
675 struct vpu_buf vb_fbc_y_tbl[MAX_REG_FRAME];
676 struct vpu_buf vb_fbc_c_tbl[MAX_REG_FRAME];
677 unsigned int num_of_decoding_fbs: 7;
678 unsigned int num_of_display_fbs: 7;
679 unsigned int stride;
680 struct sec_axi_info sec_axi_info;
681 dma_addr_t user_data_buf_addr;
682 u32 user_data_enable;
683 u32 user_data_buf_size;
684 struct vpu_buf vb_work;
685 struct vpu_buf vb_task;
686 struct dec_output_info dec_out_info[WAVE5_MAX_FBS];
687 u32 seq_change_mask;
688 enum temporal_id_mode temp_id_select_mode;
689 u32 target_temp_id;
690 u32 target_spatial_id;
691 u32 instance_queue_count;
692 u32 report_queue_count;
693 u32 cycle_per_tick;
694 u32 product_code;
695 u32 vlc_buf_size;
696 u32 param_buf_size;
697 bool initial_info_obtained;
698 bool reorder_enable;
699 bool first_cycle_check;
700 u32 stream_endflag: 1;
701};
702
703struct enc_info {
704 struct enc_open_param open_param;
705 struct enc_initial_info initial_info;
706 u32 stream_rd_ptr;
707 u32 stream_wr_ptr;
708 dma_addr_t stream_buf_start_addr;
709 dma_addr_t stream_buf_end_addr;
710 u32 stream_buf_size;
711 unsigned int num_frame_buffers;
712 unsigned int stride;
713 bool rotation_enable;
714 bool mirror_enable;
715 enum mirror_direction mirror_direction;
716 unsigned int rotation_angle;
717 bool initial_info_obtained;
718 struct sec_axi_info sec_axi_info;
719 bool line_buf_int_en;
720 struct vpu_buf vb_work;
721 struct vpu_buf vb_mv; /* col_mv buffer */
722 struct vpu_buf vb_fbc_y_tbl; /* FBC luma table buffer */
723 struct vpu_buf vb_fbc_c_tbl; /* FBC chroma table buffer */
724 struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */
725 struct vpu_buf vb_task;
726 u64 cur_pts; /* current timestamp in 90_k_hz */
727 u64 pts_map[32]; /* PTS mapped with source frame index */
728 u32 instance_queue_count;
729 u32 report_queue_count;
730 bool first_cycle_check;
731 u32 cycle_per_tick;
732 u32 product_code;
733 u32 vlc_buf_size;
734 u32 param_buf_size;
735};
736
737struct vpu_device {
738 struct device *dev;
739 struct v4l2_device v4l2_dev;
740 struct v4l2_m2m_dev *v4l2_m2m_dec_dev;
741 struct v4l2_m2m_dev *v4l2_m2m_enc_dev;
742 struct list_head instances;
743 struct video_device *video_dev_dec;
744 struct video_device *video_dev_enc;
745 struct mutex dev_lock; /* lock for the src, dst v4l2 queues */
746 struct mutex hw_lock; /* lock hw configurations */
747 int irq;
748 enum product_id product;
749 struct vpu_attr attr;
750 struct vpu_buf common_mem;
751 u32 last_performance_cycles;
752 u32 sram_size;
753 struct gen_pool *sram_pool;
754 struct vpu_buf sram_buf;
755 void __iomem *vdb_register;
756 u32 product_code;
757 struct ida inst_ida;
758 struct clk_bulk_data *clks;
759 int num_clks;
760};
761
762struct vpu_instance;
763
764struct vpu_instance_ops {
765 void (*finish_process)(struct vpu_instance *inst);
766};
767
768struct vpu_instance {
769 struct list_head list;
770 struct v4l2_fh v4l2_fh;
771 struct v4l2_m2m_dev *v4l2_m2m_dev;
772 struct v4l2_ctrl_handler v4l2_ctrl_hdl;
773 struct vpu_device *dev;
774 struct completion irq_done;
775
776 struct v4l2_pix_format_mplane src_fmt;
777 struct v4l2_pix_format_mplane dst_fmt;
778 enum v4l2_colorspace colorspace;
779 enum v4l2_xfer_func xfer_func;
780 enum v4l2_ycbcr_encoding ycbcr_enc;
781 enum v4l2_quantization quantization;
782
783 enum vpu_instance_state state;
784 enum vpu_instance_type type;
785 const struct vpu_instance_ops *ops;
786 spinlock_t state_spinlock; /* This protects the instance state */
787
788 enum wave_std std;
789 s32 id;
790 union {
791 struct enc_info enc_info;
792 struct dec_info dec_info;
793 } *codec_info;
794 struct frame_buffer frame_buf[MAX_REG_FRAME];
795 struct vpu_buf frame_vbuf[MAX_REG_FRAME];
796 u32 fbc_buf_count;
797 u32 queued_src_buf_num;
798 u32 queued_dst_buf_num;
799 struct list_head avail_src_bufs;
800 struct list_head avail_dst_bufs;
801 struct v4l2_rect conf_win;
802 u64 timestamp;
803 enum frame_buffer_format output_format;
804 bool cbcr_interleave;
805 bool nv21;
806 bool eos;
807 struct vpu_buf bitstream_vbuf;
808 dma_addr_t last_rd_ptr;
809 size_t remaining_consumed_bytes;
810 bool needs_reallocation;
811
812 unsigned int min_src_buf_count;
813 unsigned int rot_angle;
814 unsigned int mirror_direction;
815 unsigned int bit_depth;
816 unsigned int frame_rate;
817 unsigned int vbv_buf_size;
818 unsigned int rc_mode;
819 unsigned int rc_enable;
820 unsigned int bit_rate;
821 unsigned int encode_aud;
822 struct enc_wave_param enc_param;
823};
824
825void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data);
826u32 wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr);
827int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
828int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
829int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,
830 size_t size);
831int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,
832 u8 *data, size_t len);
833int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb);
834void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev);
835void wave5_vdi_free_sram(struct vpu_device *vpu_dev);
836
837int wave5_vpu_init_with_bitcode(struct device *dev, u8 *bitcode, size_t size);
838int wave5_vpu_flush_instance(struct vpu_instance *inst);
839int wave5_vpu_get_version_info(struct device *dev, u32 *revision, unsigned int *product_id);
840int wave5_vpu_dec_open(struct vpu_instance *inst, struct dec_open_param *open_param);
841int wave5_vpu_dec_close(struct vpu_instance *inst, u32 *fail_res);
842int wave5_vpu_dec_issue_seq_init(struct vpu_instance *inst);
843int wave5_vpu_dec_complete_seq_init(struct vpu_instance *inst, struct dec_initial_info *info);
844int wave5_vpu_dec_register_frame_buffer_ex(struct vpu_instance *inst, int num_of_decoding_fbs,
845 int num_of_display_fbs, int stride, int height);
846int wave5_vpu_dec_start_one_frame(struct vpu_instance *inst, u32 *res_fail);
847int wave5_vpu_dec_get_output_info(struct vpu_instance *inst, struct dec_output_info *info);
848int wave5_vpu_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr, int update_wr_ptr);
849dma_addr_t wave5_vpu_dec_get_rd_ptr(struct vpu_instance *inst);
850int wave5_vpu_dec_reset_framebuffer(struct vpu_instance *inst, unsigned int index);
851int wave5_vpu_dec_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
852int wave5_vpu_dec_get_bitstream_buffer(struct vpu_instance *inst, dma_addr_t *prd_ptr,
853 dma_addr_t *pwr_ptr, size_t *size);
854int wave5_vpu_dec_update_bitstream_buffer(struct vpu_instance *inst, size_t size);
855int wave5_vpu_dec_clr_disp_flag(struct vpu_instance *inst, int index);
856int wave5_vpu_dec_set_disp_flag(struct vpu_instance *inst, int index);
857
858int wave5_vpu_enc_open(struct vpu_instance *inst, struct enc_open_param *open_param);
859int wave5_vpu_enc_close(struct vpu_instance *inst, u32 *fail_res);
860int wave5_vpu_enc_issue_seq_init(struct vpu_instance *inst);
861int wave5_vpu_enc_complete_seq_init(struct vpu_instance *inst, struct enc_initial_info *info);
862int wave5_vpu_enc_register_frame_buffer(struct vpu_instance *inst, unsigned int num,
863 unsigned int stride, int height,
864 enum tiled_map_type map_type);
865int wave5_vpu_enc_start_one_frame(struct vpu_instance *inst, struct enc_param *param,
866 u32 *fail_res);
867int wave5_vpu_enc_get_output_info(struct vpu_instance *inst, struct enc_output_info *info);
868int wave5_vpu_enc_give_command(struct vpu_instance *inst, enum codec_command cmd, void *parameter);
869
870#endif