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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 | // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) /* * Wave5 series multi-standard codec IP - low level access functions * * Copyright (C) 2021-2023 CHIPS&MEDIA INC */ #include <linux/bug.h> #include "wave5-vdi.h" #include "wave5-vpu.h" #include "wave5-regdefine.h" #include <linux/delay.h> static int wave5_vdi_allocate_common_memory(struct device *dev) { struct vpu_device *vpu_dev = dev_get_drvdata(dev); if (!vpu_dev->common_mem.vaddr) { int ret; vpu_dev->common_mem.size = SIZE_COMMON; ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem); if (ret) { dev_err(dev, "unable to allocate common buffer\n"); return ret; } } dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n", &vpu_dev->common_mem.daddr, vpu_dev->common_mem.size, vpu_dev->common_mem.vaddr); return 0; } int wave5_vdi_init(struct device *dev) { struct vpu_device *vpu_dev = dev_get_drvdata(dev); int ret; ret = wave5_vdi_allocate_common_memory(dev); if (ret < 0) { dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n"); return ret; } if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) { WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code); return -EOPNOTSUPP; } /* if BIT processor is not running. */ if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) { int i; for (i = 0; i < 64; i++) wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0); } dev_dbg(dev, "[VDI] driver initialized successfully\n"); return 0; } int wave5_vdi_release(struct device *dev) { struct vpu_device *vpu_dev = dev_get_drvdata(dev); vpu_dev->vdb_register = NULL; wave5_vdi_free_dma_memory(vpu_dev, &vpu_dev->common_mem); return 0; } void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data) { writel(data, vpu_dev->vdb_register + addr); } unsigned int wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr) { return readl(vpu_dev->vdb_register + addr); } int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) { if (!vb || !vb->vaddr) { dev_err(vpu_dev->dev, "%s: unable to clear unmapped buffer\n", __func__); return -EINVAL; } memset(vb->vaddr, 0, vb->size); return vb->size; } int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset, u8 *data, size_t len) { if (!vb || !vb->vaddr) { dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__); return -EINVAL; } if (offset > vb->size || len > vb->size || offset + len > vb->size) { dev_err(vpu_dev->dev, "%s: buffer too small\n", __func__); return -ENOSPC; } memcpy(vb->vaddr + offset, data, len); return len; } int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) { void *vaddr; dma_addr_t daddr; if (!vb->size) { dev_err(vpu_dev->dev, "%s: requested size==0\n", __func__); return -EINVAL; } vaddr = dma_alloc_coherent(vpu_dev->dev, vb->size, &daddr, GFP_KERNEL); if (!vaddr) return -ENOMEM; vb->vaddr = vaddr; vb->daddr = daddr; return 0; } int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb) { if (vb->size == 0) return -EINVAL; if (!vb->vaddr) dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__); else dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr); memset(vb, 0, sizeof(*vb)); return 0; } int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count, size_t size) { struct vpu_buf vb_buf; int i, ret = 0; vb_buf.size = size; for (i = 0; i < count; i++) { if (array[i].size == size) continue; if (array[i].size != 0) wave5_vdi_free_dma_memory(vpu_dev, &array[i]); ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_buf); if (ret) return -ENOMEM; array[i] = vb_buf; } for (i = count; i < MAX_REG_FRAME; i++) wave5_vdi_free_dma_memory(vpu_dev, &array[i]); return 0; } void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev) { struct vpu_buf *vb = &vpu_dev->sram_buf; if (!vpu_dev->sram_pool || !vpu_dev->sram_size) return; if (!vb->vaddr) { vb->size = vpu_dev->sram_size; vb->vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, vb->size, &vb->daddr); if (!vb->vaddr) vb->size = 0; } dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n", __func__, &vb->daddr, vb->size, vb->vaddr); } void wave5_vdi_free_sram(struct vpu_device *vpu_dev) { struct vpu_buf *vb = &vpu_dev->sram_buf; if (!vb->size || !vb->vaddr) return; if (vb->vaddr) gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr, vb->size); memset(vb, 0, sizeof(*vb)); } |