Loading...
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Realtek RTL2832 DVB-T demodulator driver
4 *
5 * Copyright (C) 2012 Thomas Mair <thomas.mair86@gmail.com>
6 * Copyright (C) 2012-2014 Antti Palosaari <crope@iki.fi>
7 */
8
9#ifndef RTL2832_PRIV_H
10#define RTL2832_PRIV_H
11
12#include <linux/regmap.h>
13#include <linux/math64.h>
14#include <linux/bitops.h>
15
16#include <media/dvb_frontend.h>
17#include <linux/int_log.h>
18#include "rtl2832.h"
19
20struct rtl2832_dev {
21 struct rtl2832_platform_data *pdata;
22 struct i2c_client *client;
23 struct regmap_config regmap_config;
24 struct regmap *regmap;
25 struct i2c_mux_core *muxc;
26 struct dvb_frontend fe;
27 enum fe_status fe_status;
28 u64 post_bit_error_prev; /* for old DVBv3 read_ber() calculation */
29 u64 post_bit_error;
30 u64 post_bit_count;
31 bool sleeping;
32 struct delayed_work i2c_gate_work;
33 unsigned long filters; /* PID filter */
34 bool slave_ts;
35};
36
37struct rtl2832_reg_entry {
38 u16 start_address;
39 u8 msb;
40 u8 lsb;
41};
42
43struct rtl2832_reg_value {
44 int reg;
45 u32 value;
46};
47
48/* Demod register bit names */
49enum DVBT_REG_BIT_NAME {
50 DVBT_SOFT_RST,
51 DVBT_IIC_REPEAT,
52 DVBT_TR_WAIT_MIN_8K,
53 DVBT_RSD_BER_FAIL_VAL,
54 DVBT_EN_BK_TRK,
55 DVBT_REG_PI,
56 DVBT_REG_PFREQ_1_0,
57 DVBT_PD_DA8,
58 DVBT_LOCK_TH,
59 DVBT_BER_PASS_SCAL,
60 DVBT_CE_FFSM_BYPASS,
61 DVBT_ALPHAIIR_N,
62 DVBT_ALPHAIIR_DIF,
63 DVBT_EN_TRK_SPAN,
64 DVBT_LOCK_TH_LEN,
65 DVBT_CCI_THRE,
66 DVBT_CCI_MON_SCAL,
67 DVBT_CCI_M0,
68 DVBT_CCI_M1,
69 DVBT_CCI_M2,
70 DVBT_CCI_M3,
71 DVBT_SPEC_INIT_0,
72 DVBT_SPEC_INIT_1,
73 DVBT_SPEC_INIT_2,
74 DVBT_AD_EN_REG,
75 DVBT_AD_EN_REG1,
76 DVBT_EN_BBIN,
77 DVBT_MGD_THD0,
78 DVBT_MGD_THD1,
79 DVBT_MGD_THD2,
80 DVBT_MGD_THD3,
81 DVBT_MGD_THD4,
82 DVBT_MGD_THD5,
83 DVBT_MGD_THD6,
84 DVBT_MGD_THD7,
85 DVBT_EN_CACQ_NOTCH,
86 DVBT_AD_AV_REF,
87 DVBT_PIP_ON,
88 DVBT_SCALE1_B92,
89 DVBT_SCALE1_B93,
90 DVBT_SCALE1_BA7,
91 DVBT_SCALE1_BA9,
92 DVBT_SCALE1_BAA,
93 DVBT_SCALE1_BAB,
94 DVBT_SCALE1_BAC,
95 DVBT_SCALE1_BB0,
96 DVBT_SCALE1_BB1,
97 DVBT_KB_P1,
98 DVBT_KB_P2,
99 DVBT_KB_P3,
100 DVBT_OPT_ADC_IQ,
101 DVBT_AD_AVI,
102 DVBT_AD_AVQ,
103 DVBT_K1_CR_STEP12,
104 DVBT_TRK_KS_P2,
105 DVBT_TRK_KS_I2,
106 DVBT_TR_THD_SET2,
107 DVBT_TRK_KC_P2,
108 DVBT_TRK_KC_I2,
109 DVBT_CR_THD_SET2,
110 DVBT_PSET_IFFREQ,
111 DVBT_SPEC_INV,
112 DVBT_BW_INDEX,
113 DVBT_RSAMP_RATIO,
114 DVBT_CFREQ_OFF_RATIO,
115 DVBT_FSM_STAGE,
116 DVBT_RX_CONSTEL,
117 DVBT_RX_HIER,
118 DVBT_RX_C_RATE_LP,
119 DVBT_RX_C_RATE_HP,
120 DVBT_GI_IDX,
121 DVBT_FFT_MODE_IDX,
122 DVBT_RSD_BER_EST,
123 DVBT_CE_EST_EVM,
124 DVBT_RF_AGC_VAL,
125 DVBT_IF_AGC_VAL,
126 DVBT_DAGC_VAL,
127 DVBT_SFREQ_OFF,
128 DVBT_CFREQ_OFF,
129 DVBT_POLAR_RF_AGC,
130 DVBT_POLAR_IF_AGC,
131 DVBT_AAGC_HOLD,
132 DVBT_EN_RF_AGC,
133 DVBT_EN_IF_AGC,
134 DVBT_IF_AGC_MIN,
135 DVBT_IF_AGC_MAX,
136 DVBT_RF_AGC_MIN,
137 DVBT_RF_AGC_MAX,
138 DVBT_IF_AGC_MAN,
139 DVBT_IF_AGC_MAN_VAL,
140 DVBT_RF_AGC_MAN,
141 DVBT_RF_AGC_MAN_VAL,
142 DVBT_DAGC_TRG_VAL,
143 DVBT_AGC_TARG_VAL,
144 DVBT_LOOP_GAIN_3_0,
145 DVBT_LOOP_GAIN_4,
146 DVBT_VTOP,
147 DVBT_KRF,
148 DVBT_AGC_TARG_VAL_0,
149 DVBT_AGC_TARG_VAL_8_1,
150 DVBT_AAGC_LOOP_GAIN,
151 DVBT_LOOP_GAIN2_3_0,
152 DVBT_LOOP_GAIN2_4,
153 DVBT_LOOP_GAIN3,
154 DVBT_VTOP1,
155 DVBT_VTOP2,
156 DVBT_VTOP3,
157 DVBT_KRF1,
158 DVBT_KRF2,
159 DVBT_KRF3,
160 DVBT_KRF4,
161 DVBT_EN_GI_PGA,
162 DVBT_THD_LOCK_UP,
163 DVBT_THD_LOCK_DW,
164 DVBT_THD_UP1,
165 DVBT_THD_DW1,
166 DVBT_INTER_CNT_LEN,
167 DVBT_GI_PGA_STATE,
168 DVBT_EN_AGC_PGA,
169 DVBT_CKOUTPAR,
170 DVBT_CKOUT_PWR,
171 DVBT_SYNC_DUR,
172 DVBT_ERR_DUR,
173 DVBT_SYNC_LVL,
174 DVBT_ERR_LVL,
175 DVBT_VAL_LVL,
176 DVBT_SERIAL,
177 DVBT_SER_LSB,
178 DVBT_CDIV_PH0,
179 DVBT_CDIV_PH1,
180 DVBT_MPEG_IO_OPT_2_2,
181 DVBT_MPEG_IO_OPT_1_0,
182 DVBT_CKOUTPAR_PIP,
183 DVBT_CKOUT_PWR_PIP,
184 DVBT_SYNC_LVL_PIP,
185 DVBT_ERR_LVL_PIP,
186 DVBT_VAL_LVL_PIP,
187 DVBT_CKOUTPAR_PID,
188 DVBT_CKOUT_PWR_PID,
189 DVBT_SYNC_LVL_PID,
190 DVBT_ERR_LVL_PID,
191 DVBT_VAL_LVL_PID,
192 DVBT_SM_PASS,
193 DVBT_UPDATE_REG_2,
194 DVBT_BTHD_P3,
195 DVBT_BTHD_D3,
196 DVBT_FUNC4_REG0,
197 DVBT_FUNC4_REG1,
198 DVBT_FUNC4_REG2,
199 DVBT_FUNC4_REG3,
200 DVBT_FUNC4_REG4,
201 DVBT_FUNC4_REG5,
202 DVBT_FUNC4_REG6,
203 DVBT_FUNC4_REG7,
204 DVBT_FUNC4_REG8,
205 DVBT_FUNC4_REG9,
206 DVBT_FUNC4_REG10,
207 DVBT_FUNC5_REG0,
208 DVBT_FUNC5_REG1,
209 DVBT_FUNC5_REG2,
210 DVBT_FUNC5_REG3,
211 DVBT_FUNC5_REG4,
212 DVBT_FUNC5_REG5,
213 DVBT_FUNC5_REG6,
214 DVBT_FUNC5_REG7,
215 DVBT_FUNC5_REG8,
216 DVBT_FUNC5_REG9,
217 DVBT_FUNC5_REG10,
218 DVBT_FUNC5_REG11,
219 DVBT_FUNC5_REG12,
220 DVBT_FUNC5_REG13,
221 DVBT_FUNC5_REG14,
222 DVBT_FUNC5_REG15,
223 DVBT_FUNC5_REG16,
224 DVBT_FUNC5_REG17,
225 DVBT_FUNC5_REG18,
226 DVBT_AD7_SETTING,
227 DVBT_RSSI_R,
228 DVBT_ACI_DET_IND,
229 DVBT_REG_MON,
230 DVBT_REG_MONSEL,
231 DVBT_REG_GPE,
232 DVBT_REG_GPO,
233 DVBT_REG_4MSEL,
234 DVBT_TEST_REG_1,
235 DVBT_TEST_REG_2,
236 DVBT_TEST_REG_3,
237 DVBT_TEST_REG_4,
238 DVBT_REG_BIT_NAME_ITEM_TERMINATOR,
239};
240
241static const struct rtl2832_reg_value rtl2832_tuner_init_fc2580[] = {
242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
252 {DVBT_KRF1, 0x0},
253 {DVBT_KRF2, 0x40},
254 {DVBT_KRF3, 0x10},
255 {DVBT_KRF4, 0x10},
256 {DVBT_IF_AGC_MIN, 0x80},
257 {DVBT_IF_AGC_MAX, 0x7f},
258 {DVBT_RF_AGC_MIN, 0x9c},
259 {DVBT_RF_AGC_MAX, 0x7f},
260 {DVBT_POLAR_RF_AGC, 0x0},
261 {DVBT_POLAR_IF_AGC, 0x0},
262 {DVBT_AD7_SETTING, 0xe9f4},
263};
264
265static const struct rtl2832_reg_value rtl2832_tuner_init_tua9001[] = {
266 {DVBT_DAGC_TRG_VAL, 0x39},
267 {DVBT_AGC_TARG_VAL_0, 0x0},
268 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
269 {DVBT_AAGC_LOOP_GAIN, 0x16},
270 {DVBT_LOOP_GAIN2_3_0, 0x6},
271 {DVBT_LOOP_GAIN2_4, 0x1},
272 {DVBT_LOOP_GAIN3, 0x16},
273 {DVBT_VTOP1, 0x35},
274 {DVBT_VTOP2, 0x21},
275 {DVBT_VTOP3, 0x21},
276 {DVBT_KRF1, 0x0},
277 {DVBT_KRF2, 0x40},
278 {DVBT_KRF3, 0x10},
279 {DVBT_KRF4, 0x10},
280 {DVBT_IF_AGC_MIN, 0x80},
281 {DVBT_IF_AGC_MAX, 0x7f},
282 {DVBT_RF_AGC_MIN, 0x9c},
283 {DVBT_RF_AGC_MAX, 0x7f},
284 {DVBT_POLAR_RF_AGC, 0x0},
285 {DVBT_POLAR_IF_AGC, 0x0},
286 {DVBT_AD7_SETTING, 0xe9f4},
287 {DVBT_OPT_ADC_IQ, 0x1},
288 {DVBT_AD_AVI, 0x0},
289 {DVBT_AD_AVQ, 0x0},
290 {DVBT_SPEC_INV, 0x0},
291};
292
293static const struct rtl2832_reg_value rtl2832_tuner_init_fc0012[] = {
294 {DVBT_DAGC_TRG_VAL, 0x5a},
295 {DVBT_AGC_TARG_VAL_0, 0x0},
296 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
297 {DVBT_AAGC_LOOP_GAIN, 0x16},
298 {DVBT_LOOP_GAIN2_3_0, 0x6},
299 {DVBT_LOOP_GAIN2_4, 0x1},
300 {DVBT_LOOP_GAIN3, 0x16},
301 {DVBT_VTOP1, 0x35},
302 {DVBT_VTOP2, 0x21},
303 {DVBT_VTOP3, 0x21},
304 {DVBT_KRF1, 0x0},
305 {DVBT_KRF2, 0x40},
306 {DVBT_KRF3, 0x10},
307 {DVBT_KRF4, 0x10},
308 {DVBT_IF_AGC_MIN, 0x80},
309 {DVBT_IF_AGC_MAX, 0x7f},
310 {DVBT_RF_AGC_MIN, 0x80},
311 {DVBT_RF_AGC_MAX, 0x7f},
312 {DVBT_POLAR_RF_AGC, 0x0},
313 {DVBT_POLAR_IF_AGC, 0x0},
314 {DVBT_AD7_SETTING, 0xe9bf},
315 {DVBT_EN_GI_PGA, 0x0},
316 {DVBT_THD_LOCK_UP, 0x0},
317 {DVBT_THD_LOCK_DW, 0x0},
318 {DVBT_THD_UP1, 0x11},
319 {DVBT_THD_DW1, 0xef},
320 {DVBT_INTER_CNT_LEN, 0xc},
321 {DVBT_GI_PGA_STATE, 0x0},
322 {DVBT_EN_AGC_PGA, 0x1},
323 {DVBT_IF_AGC_MAN, 0x0},
324 {DVBT_SPEC_INV, 0x0},
325};
326
327static const struct rtl2832_reg_value rtl2832_tuner_init_e4000[] = {
328 {DVBT_DAGC_TRG_VAL, 0x5a},
329 {DVBT_AGC_TARG_VAL_0, 0x0},
330 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
331 {DVBT_AAGC_LOOP_GAIN, 0x18},
332 {DVBT_LOOP_GAIN2_3_0, 0x8},
333 {DVBT_LOOP_GAIN2_4, 0x1},
334 {DVBT_LOOP_GAIN3, 0x18},
335 {DVBT_VTOP1, 0x35},
336 {DVBT_VTOP2, 0x21},
337 {DVBT_VTOP3, 0x21},
338 {DVBT_KRF1, 0x0},
339 {DVBT_KRF2, 0x40},
340 {DVBT_KRF3, 0x10},
341 {DVBT_KRF4, 0x10},
342 {DVBT_IF_AGC_MIN, 0x80},
343 {DVBT_IF_AGC_MAX, 0x7f},
344 {DVBT_RF_AGC_MIN, 0x80},
345 {DVBT_RF_AGC_MAX, 0x7f},
346 {DVBT_POLAR_RF_AGC, 0x0},
347 {DVBT_POLAR_IF_AGC, 0x0},
348 {DVBT_AD7_SETTING, 0xe9d4},
349 {DVBT_EN_GI_PGA, 0x0},
350 {DVBT_THD_LOCK_UP, 0x0},
351 {DVBT_THD_LOCK_DW, 0x0},
352 {DVBT_THD_UP1, 0x14},
353 {DVBT_THD_DW1, 0xec},
354 {DVBT_INTER_CNT_LEN, 0xc},
355 {DVBT_GI_PGA_STATE, 0x0},
356 {DVBT_EN_AGC_PGA, 0x1},
357 {DVBT_REG_GPE, 0x1},
358 {DVBT_REG_GPO, 0x1},
359 {DVBT_REG_MONSEL, 0x1},
360 {DVBT_REG_MON, 0x1},
361 {DVBT_REG_4MSEL, 0x0},
362 {DVBT_SPEC_INV, 0x0},
363};
364
365static const struct rtl2832_reg_value rtl2832_tuner_init_r820t[] = {
366 {DVBT_DAGC_TRG_VAL, 0x39},
367 {DVBT_AGC_TARG_VAL_0, 0x0},
368 {DVBT_AGC_TARG_VAL_8_1, 0x40},
369 {DVBT_AAGC_LOOP_GAIN, 0x16},
370 {DVBT_LOOP_GAIN2_3_0, 0x8},
371 {DVBT_LOOP_GAIN2_4, 0x1},
372 {DVBT_LOOP_GAIN3, 0x18},
373 {DVBT_VTOP1, 0x35},
374 {DVBT_VTOP2, 0x21},
375 {DVBT_VTOP3, 0x21},
376 {DVBT_KRF1, 0x0},
377 {DVBT_KRF2, 0x40},
378 {DVBT_KRF3, 0x10},
379 {DVBT_KRF4, 0x10},
380 {DVBT_IF_AGC_MIN, 0x80},
381 {DVBT_IF_AGC_MAX, 0x7f},
382 {DVBT_RF_AGC_MIN, 0x80},
383 {DVBT_RF_AGC_MAX, 0x7f},
384 {DVBT_POLAR_RF_AGC, 0x0},
385 {DVBT_POLAR_IF_AGC, 0x0},
386 {DVBT_AD7_SETTING, 0xe9f4},
387 {DVBT_SPEC_INV, 0x1},
388};
389
390static const struct rtl2832_reg_value rtl2832_tuner_init_si2157[] = {
391 {DVBT_DAGC_TRG_VAL, 0x39},
392 {DVBT_AGC_TARG_VAL_0, 0x0},
393 {DVBT_AGC_TARG_VAL_8_1, 0x40},
394 {DVBT_AAGC_LOOP_GAIN, 0x16},
395 {DVBT_LOOP_GAIN2_3_0, 0x8},
396 {DVBT_LOOP_GAIN2_4, 0x1},
397 {DVBT_LOOP_GAIN3, 0x18},
398 {DVBT_VTOP1, 0x35},
399 {DVBT_VTOP2, 0x21},
400 {DVBT_VTOP3, 0x21},
401 {DVBT_KRF1, 0x0},
402 {DVBT_KRF2, 0x40},
403 {DVBT_KRF3, 0x10},
404 {DVBT_KRF4, 0x10},
405 {DVBT_IF_AGC_MIN, 0x80},
406 {DVBT_IF_AGC_MAX, 0x7f},
407 {DVBT_RF_AGC_MIN, 0x80},
408 {DVBT_RF_AGC_MAX, 0x7f},
409 {DVBT_POLAR_RF_AGC, 0x0},
410 {DVBT_POLAR_IF_AGC, 0x0},
411 {DVBT_AD7_SETTING, 0xe9f4},
412 {DVBT_SPEC_INV, 0x0},
413};
414
415#endif /* RTL2832_PRIV_H */