1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
 4 */
 5
 6#ifndef _ARM_SMMU_QCOM_H
 7#define _ARM_SMMU_QCOM_H
 8
 9struct qcom_smmu {
10	struct arm_smmu_device smmu;
11	const struct qcom_smmu_config *cfg;
12	bool bypass_quirk;
13	u8 bypass_cbndx;
14	u32 stall_enabled;
15};
16
17enum qcom_smmu_impl_reg_offset {
18	QCOM_SMMU_TBU_PWR_STATUS,
19	QCOM_SMMU_STATS_SYNC_INV_TBU_ACK,
20	QCOM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR,
21};
22
23struct qcom_smmu_config {
24	const u32 *reg_offset;
25};
26
27struct qcom_smmu_match_data {
28	const struct qcom_smmu_config *cfg;
29	const struct arm_smmu_impl *impl;
30	const struct arm_smmu_impl *adreno_impl;
31};
32
33#ifdef CONFIG_ARM_SMMU_QCOM_DEBUG
34void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu);
35#else
36static inline void qcom_smmu_tlb_sync_debug(struct arm_smmu_device *smmu) { }
37#endif
38
39#endif /* _ARM_SMMU_QCOM_H */