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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 TDK-InvenSense, Inc. */ #include <linux/kernel.h> #include <linux/device.h> #include <linux/regmap.h> #include <linux/delay.h> #include "inv_mpu_aux.h" #include "inv_mpu_iio.h" /* * i2c master auxiliary bus transfer function. * Requires the i2c operations to be correctly setup before. */ static int inv_mpu_i2c_master_xfer(const struct inv_mpu6050_state *st) { /* use 50hz frequency for xfer */ const unsigned int freq = 50; const unsigned int period_ms = 1000 / freq; uint8_t d; unsigned int user_ctrl; int ret; /* set sample rate */ d = INV_MPU6050_FIFO_RATE_TO_DIVIDER(freq); ret = regmap_write(st->map, st->reg->sample_rate_div, d); if (ret) return ret; /* start i2c master */ user_ctrl = st->chip_config.user_ctrl | INV_MPU6050_BIT_I2C_MST_EN; ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); if (ret) goto error_restore_rate; /* wait for xfer: 1 period + half-period margin */ msleep(period_ms + period_ms / 2); /* stop i2c master */ user_ctrl = st->chip_config.user_ctrl; ret = regmap_write(st->map, st->reg->user_ctrl, user_ctrl); if (ret) goto error_stop_i2c; /* restore sample rate */ d = st->chip_config.divider; ret = regmap_write(st->map, st->reg->sample_rate_div, d); if (ret) goto error_restore_rate; return 0; error_stop_i2c: regmap_write(st->map, st->reg->user_ctrl, st->chip_config.user_ctrl); error_restore_rate: regmap_write(st->map, st->reg->sample_rate_div, st->chip_config.divider); return ret; } /** * inv_mpu_aux_init() - init i2c auxiliary bus * @st: driver internal state * * Returns 0 on success, a negative error code otherwise. */ int inv_mpu_aux_init(const struct inv_mpu6050_state *st) { unsigned int val; int ret; /* * Code based on the vendor Linux kernel v3.0, * the exact meaning is unknown. */ if (st->chip_type == INV_MPU9150) { unsigned int mask = BIT(7); val = st->level_shifter ? mask : 0; ret = regmap_update_bits(st->map, 0x1, mask, val); if (ret) return ret; } /* configure i2c master */ val = INV_MPU6050_BITS_I2C_MST_CLK_400KHZ | INV_MPU6050_BIT_WAIT_FOR_ES; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_MST_CTRL, val); if (ret) return ret; /* configure i2c master delay */ ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV4_CTRL, 0); if (ret) return ret; val = INV_MPU6050_BIT_I2C_SLV0_DLY_EN | INV_MPU6050_BIT_I2C_SLV1_DLY_EN | INV_MPU6050_BIT_I2C_SLV2_DLY_EN | INV_MPU6050_BIT_I2C_SLV3_DLY_EN | INV_MPU6050_BIT_DELAY_ES_SHADOW; return regmap_write(st->map, INV_MPU6050_REG_I2C_MST_DELAY_CTRL, val); } /** * inv_mpu_aux_read() - read register function for i2c auxiliary bus * @st: driver internal state. * @addr: chip i2c Address * @reg: chip register address * @val: buffer for storing read bytes * @size: number of bytes to read * * Returns 0 on success, a negative error code otherwise. */ int inv_mpu_aux_read(const struct inv_mpu6050_state *st, uint8_t addr, uint8_t reg, uint8_t *val, size_t size) { unsigned int status; int ret; if (size > 0x0F) return -EINVAL; /* setup i2c SLV0 control: i2c addr, register, enable + size */ ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_ADDR(0), INV_MPU6050_BIT_I2C_SLV_RNW | addr); if (ret) return ret; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_REG(0), reg); if (ret) return ret; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), INV_MPU6050_BIT_SLV_EN | size); if (ret) return ret; /* do i2c xfer */ ret = inv_mpu_i2c_master_xfer(st); if (ret) goto error_disable_i2c; /* disable i2c slave */ ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); if (ret) goto error_disable_i2c; /* check i2c status */ ret = regmap_read(st->map, INV_MPU6050_REG_I2C_MST_STATUS, &status); if (ret) return ret; if (status & INV_MPU6050_BIT_I2C_SLV0_NACK) return -EIO; /* read data in registers */ return regmap_bulk_read(st->map, INV_MPU6050_REG_EXT_SENS_DATA, val, size); error_disable_i2c: regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); return ret; } /** * inv_mpu_aux_write() - write register function for i2c auxiliary bus * @st: driver internal state. * @addr: chip i2c Address * @reg: chip register address * @val: 1 byte value to write * * Returns 0 on success, a negative error code otherwise. */ int inv_mpu_aux_write(const struct inv_mpu6050_state *st, uint8_t addr, uint8_t reg, uint8_t val) { unsigned int status; int ret; /* setup i2c SLV0 control: i2c addr, register, value, enable + size */ ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_ADDR(0), addr); if (ret) return ret; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_REG(0), reg); if (ret) return ret; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_DO(0), val); if (ret) return ret; ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), INV_MPU6050_BIT_SLV_EN | 1); if (ret) return ret; /* do i2c xfer */ ret = inv_mpu_i2c_master_xfer(st); if (ret) goto error_disable_i2c; /* disable i2c slave */ ret = regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); if (ret) goto error_disable_i2c; /* check i2c status */ ret = regmap_read(st->map, INV_MPU6050_REG_I2C_MST_STATUS, &status); if (ret) return ret; if (status & INV_MPU6050_BIT_I2C_SLV0_NACK) return -EIO; return 0; error_disable_i2c: regmap_write(st->map, INV_MPU6050_REG_I2C_SLV_CTRL(0), 0); return ret; } |