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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2020 Invensense, Inc.
4 */
5
6#ifndef INV_ICM42600_H_
7#define INV_ICM42600_H_
8
9#include <linux/bits.h>
10#include <linux/bitfield.h>
11#include <linux/regmap.h>
12#include <linux/mutex.h>
13#include <linux/regulator/consumer.h>
14#include <linux/pm.h>
15#include <linux/iio/iio.h>
16
17#include "inv_icm42600_buffer.h"
18
19enum inv_icm42600_chip {
20 INV_CHIP_INVALID,
21 INV_CHIP_ICM42600,
22 INV_CHIP_ICM42602,
23 INV_CHIP_ICM42605,
24 INV_CHIP_ICM42622,
25 INV_CHIP_ICM42631,
26 INV_CHIP_NB,
27};
28
29/* serial bus slew rates */
30enum inv_icm42600_slew_rate {
31 INV_ICM42600_SLEW_RATE_20_60NS,
32 INV_ICM42600_SLEW_RATE_12_36NS,
33 INV_ICM42600_SLEW_RATE_6_18NS,
34 INV_ICM42600_SLEW_RATE_4_12NS,
35 INV_ICM42600_SLEW_RATE_2_6NS,
36 INV_ICM42600_SLEW_RATE_INF_2NS,
37};
38
39enum inv_icm42600_sensor_mode {
40 INV_ICM42600_SENSOR_MODE_OFF,
41 INV_ICM42600_SENSOR_MODE_STANDBY,
42 INV_ICM42600_SENSOR_MODE_LOW_POWER,
43 INV_ICM42600_SENSOR_MODE_LOW_NOISE,
44 INV_ICM42600_SENSOR_MODE_NB,
45};
46
47/* gyroscope fullscale values */
48enum inv_icm42600_gyro_fs {
49 INV_ICM42600_GYRO_FS_2000DPS,
50 INV_ICM42600_GYRO_FS_1000DPS,
51 INV_ICM42600_GYRO_FS_500DPS,
52 INV_ICM42600_GYRO_FS_250DPS,
53 INV_ICM42600_GYRO_FS_125DPS,
54 INV_ICM42600_GYRO_FS_62_5DPS,
55 INV_ICM42600_GYRO_FS_31_25DPS,
56 INV_ICM42600_GYRO_FS_15_625DPS,
57 INV_ICM42600_GYRO_FS_NB,
58};
59
60/* accelerometer fullscale values */
61enum inv_icm42600_accel_fs {
62 INV_ICM42600_ACCEL_FS_16G,
63 INV_ICM42600_ACCEL_FS_8G,
64 INV_ICM42600_ACCEL_FS_4G,
65 INV_ICM42600_ACCEL_FS_2G,
66 INV_ICM42600_ACCEL_FS_NB,
67};
68
69/* ODR suffixed by LN or LP are Low-Noise or Low-Power mode only */
70enum inv_icm42600_odr {
71 INV_ICM42600_ODR_8KHZ_LN = 3,
72 INV_ICM42600_ODR_4KHZ_LN,
73 INV_ICM42600_ODR_2KHZ_LN,
74 INV_ICM42600_ODR_1KHZ_LN,
75 INV_ICM42600_ODR_200HZ,
76 INV_ICM42600_ODR_100HZ,
77 INV_ICM42600_ODR_50HZ,
78 INV_ICM42600_ODR_25HZ,
79 INV_ICM42600_ODR_12_5HZ,
80 INV_ICM42600_ODR_6_25HZ_LP,
81 INV_ICM42600_ODR_3_125HZ_LP,
82 INV_ICM42600_ODR_1_5625HZ_LP,
83 INV_ICM42600_ODR_500HZ,
84 INV_ICM42600_ODR_NB,
85};
86
87enum inv_icm42600_filter {
88 /* Low-Noise mode sensor data filter (3rd order filter by default) */
89 INV_ICM42600_FILTER_BW_ODR_DIV_2,
90
91 /* Low-Power mode sensor data filter (averaging) */
92 INV_ICM42600_FILTER_AVG_1X = 1,
93 INV_ICM42600_FILTER_AVG_16X = 6,
94};
95
96struct inv_icm42600_sensor_conf {
97 int mode;
98 int fs;
99 int odr;
100 int filter;
101};
102#define INV_ICM42600_SENSOR_CONF_INIT {-1, -1, -1, -1}
103
104struct inv_icm42600_conf {
105 struct inv_icm42600_sensor_conf gyro;
106 struct inv_icm42600_sensor_conf accel;
107 bool temp_en;
108};
109
110struct inv_icm42600_suspended {
111 enum inv_icm42600_sensor_mode gyro;
112 enum inv_icm42600_sensor_mode accel;
113 bool temp;
114};
115
116/**
117 * struct inv_icm42600_state - driver state variables
118 * @lock: lock for serializing multiple registers access.
119 * @chip: chip identifier.
120 * @name: chip name.
121 * @map: regmap pointer.
122 * @vdd_supply: VDD voltage regulator for the chip.
123 * @vddio_supply: I/O voltage regulator for the chip.
124 * @orientation: sensor chip orientation relative to main hardware.
125 * @conf: chip sensors configurations.
126 * @suspended: suspended sensors configuration.
127 * @indio_gyro: gyroscope IIO device.
128 * @indio_accel: accelerometer IIO device.
129 * @buffer: data transfer buffer aligned for DMA.
130 * @fifo: FIFO management structure.
131 * @timestamp: interrupt timestamps.
132 */
133struct inv_icm42600_state {
134 struct mutex lock;
135 enum inv_icm42600_chip chip;
136 const char *name;
137 struct regmap *map;
138 struct regulator *vdd_supply;
139 struct regulator *vddio_supply;
140 struct iio_mount_matrix orientation;
141 struct inv_icm42600_conf conf;
142 struct inv_icm42600_suspended suspended;
143 struct iio_dev *indio_gyro;
144 struct iio_dev *indio_accel;
145 uint8_t buffer[2] __aligned(IIO_DMA_MINALIGN);
146 struct inv_icm42600_fifo fifo;
147 struct {
148 int64_t gyro;
149 int64_t accel;
150 } timestamp;
151};
152
153/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */
154
155/* Bank selection register, available in all banks */
156#define INV_ICM42600_REG_BANK_SEL 0x76
157#define INV_ICM42600_BANK_SEL_MASK GENMASK(2, 0)
158
159/* User bank 0 (MSB 0x00) */
160#define INV_ICM42600_REG_DEVICE_CONFIG 0x0011
161#define INV_ICM42600_DEVICE_CONFIG_SOFT_RESET BIT(0)
162
163#define INV_ICM42600_REG_DRIVE_CONFIG 0x0013
164#define INV_ICM42600_DRIVE_CONFIG_I2C_MASK GENMASK(5, 3)
165#define INV_ICM42600_DRIVE_CONFIG_I2C(_rate) \
166 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_I2C_MASK, (_rate))
167#define INV_ICM42600_DRIVE_CONFIG_SPI_MASK GENMASK(2, 0)
168#define INV_ICM42600_DRIVE_CONFIG_SPI(_rate) \
169 FIELD_PREP(INV_ICM42600_DRIVE_CONFIG_SPI_MASK, (_rate))
170
171#define INV_ICM42600_REG_INT_CONFIG 0x0014
172#define INV_ICM42600_INT_CONFIG_INT2_LATCHED BIT(5)
173#define INV_ICM42600_INT_CONFIG_INT2_PUSH_PULL BIT(4)
174#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)
175#define INV_ICM42600_INT_CONFIG_INT2_ACTIVE_LOW 0x00
176#define INV_ICM42600_INT_CONFIG_INT1_LATCHED BIT(2)
177#define INV_ICM42600_INT_CONFIG_INT1_PUSH_PULL BIT(1)
178#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_HIGH BIT(0)
179#define INV_ICM42600_INT_CONFIG_INT1_ACTIVE_LOW 0x00
180
181#define INV_ICM42600_REG_FIFO_CONFIG 0x0016
182#define INV_ICM42600_FIFO_CONFIG_MASK GENMASK(7, 6)
183#define INV_ICM42600_FIFO_CONFIG_BYPASS \
184 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 0)
185#define INV_ICM42600_FIFO_CONFIG_STREAM \
186 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 1)
187#define INV_ICM42600_FIFO_CONFIG_STOP_ON_FULL \
188 FIELD_PREP(INV_ICM42600_FIFO_CONFIG_MASK, 2)
189
190/* all sensor data are 16 bits (2 registers wide) in big-endian */
191#define INV_ICM42600_REG_TEMP_DATA 0x001D
192#define INV_ICM42600_REG_ACCEL_DATA_X 0x001F
193#define INV_ICM42600_REG_ACCEL_DATA_Y 0x0021
194#define INV_ICM42600_REG_ACCEL_DATA_Z 0x0023
195#define INV_ICM42600_REG_GYRO_DATA_X 0x0025
196#define INV_ICM42600_REG_GYRO_DATA_Y 0x0027
197#define INV_ICM42600_REG_GYRO_DATA_Z 0x0029
198#define INV_ICM42600_DATA_INVALID -32768
199
200#define INV_ICM42600_REG_INT_STATUS 0x002D
201#define INV_ICM42600_INT_STATUS_UI_FSYNC BIT(6)
202#define INV_ICM42600_INT_STATUS_PLL_RDY BIT(5)
203#define INV_ICM42600_INT_STATUS_RESET_DONE BIT(4)
204#define INV_ICM42600_INT_STATUS_DATA_RDY BIT(3)
205#define INV_ICM42600_INT_STATUS_FIFO_THS BIT(2)
206#define INV_ICM42600_INT_STATUS_FIFO_FULL BIT(1)
207#define INV_ICM42600_INT_STATUS_AGC_RDY BIT(0)
208
209/*
210 * FIFO access registers
211 * FIFO count is 16 bits (2 registers) big-endian
212 * FIFO data is a continuous read register to read FIFO content
213 */
214#define INV_ICM42600_REG_FIFO_COUNT 0x002E
215#define INV_ICM42600_REG_FIFO_DATA 0x0030
216
217#define INV_ICM42600_REG_SIGNAL_PATH_RESET 0x004B
218#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_INIT_EN BIT(6)
219#define INV_ICM42600_SIGNAL_PATH_RESET_DMP_MEM_RESET BIT(5)
220#define INV_ICM42600_SIGNAL_PATH_RESET_RESET BIT(3)
221#define INV_ICM42600_SIGNAL_PATH_RESET_TMST_STROBE BIT(2)
222#define INV_ICM42600_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(1)
223
224/* default configuration: all data big-endian and fifo count in bytes */
225#define INV_ICM42600_REG_INTF_CONFIG0 0x004C
226#define INV_ICM42600_INTF_CONFIG0_FIFO_HOLD_LAST_DATA BIT(7)
227#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_REC BIT(6)
228#define INV_ICM42600_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)
229#define INV_ICM42600_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)
230#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK GENMASK(1, 0)
231#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS \
232 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 2)
233#define INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS \
234 FIELD_PREP(INV_ICM42600_INTF_CONFIG0_UI_SIFS_CFG_MASK, 3)
235
236#define INV_ICM42600_REG_INTF_CONFIG1 0x004D
237#define INV_ICM42600_INTF_CONFIG1_ACCEL_LP_CLK_RC BIT(3)
238
239#define INV_ICM42600_REG_PWR_MGMT0 0x004E
240#define INV_ICM42600_PWR_MGMT0_TEMP_DIS BIT(5)
241#define INV_ICM42600_PWR_MGMT0_IDLE BIT(4)
242#define INV_ICM42600_PWR_MGMT0_GYRO(_mode) \
243 FIELD_PREP(GENMASK(3, 2), (_mode))
244#define INV_ICM42600_PWR_MGMT0_ACCEL(_mode) \
245 FIELD_PREP(GENMASK(1, 0), (_mode))
246
247#define INV_ICM42600_REG_GYRO_CONFIG0 0x004F
248#define INV_ICM42600_GYRO_CONFIG0_FS(_fs) \
249 FIELD_PREP(GENMASK(7, 5), (_fs))
250#define INV_ICM42600_GYRO_CONFIG0_ODR(_odr) \
251 FIELD_PREP(GENMASK(3, 0), (_odr))
252
253#define INV_ICM42600_REG_ACCEL_CONFIG0 0x0050
254#define INV_ICM42600_ACCEL_CONFIG0_FS(_fs) \
255 FIELD_PREP(GENMASK(7, 5), (_fs))
256#define INV_ICM42600_ACCEL_CONFIG0_ODR(_odr) \
257 FIELD_PREP(GENMASK(3, 0), (_odr))
258
259#define INV_ICM42600_REG_GYRO_ACCEL_CONFIG0 0x0052
260#define INV_ICM42600_GYRO_ACCEL_CONFIG0_ACCEL_FILT(_f) \
261 FIELD_PREP(GENMASK(7, 4), (_f))
262#define INV_ICM42600_GYRO_ACCEL_CONFIG0_GYRO_FILT(_f) \
263 FIELD_PREP(GENMASK(3, 0), (_f))
264
265#define INV_ICM42600_REG_TMST_CONFIG 0x0054
266#define INV_ICM42600_TMST_CONFIG_MASK GENMASK(4, 0)
267#define INV_ICM42600_TMST_CONFIG_TMST_TO_REGS_EN BIT(4)
268#define INV_ICM42600_TMST_CONFIG_TMST_RES_16US BIT(3)
269#define INV_ICM42600_TMST_CONFIG_TMST_DELTA_EN BIT(2)
270#define INV_ICM42600_TMST_CONFIG_TMST_FSYNC_EN BIT(1)
271#define INV_ICM42600_TMST_CONFIG_TMST_EN BIT(0)
272
273#define INV_ICM42600_REG_FIFO_CONFIG1 0x005F
274#define INV_ICM42600_FIFO_CONFIG1_RESUME_PARTIAL_RD BIT(6)
275#define INV_ICM42600_FIFO_CONFIG1_WM_GT_TH BIT(5)
276#define INV_ICM42600_FIFO_CONFIG1_TMST_FSYNC_EN BIT(3)
277#define INV_ICM42600_FIFO_CONFIG1_TEMP_EN BIT(2)
278#define INV_ICM42600_FIFO_CONFIG1_GYRO_EN BIT(1)
279#define INV_ICM42600_FIFO_CONFIG1_ACCEL_EN BIT(0)
280
281/* FIFO watermark is 16 bits (2 registers wide) in little-endian */
282#define INV_ICM42600_REG_FIFO_WATERMARK 0x0060
283#define INV_ICM42600_FIFO_WATERMARK_VAL(_wm) \
284 cpu_to_le16((_wm) & GENMASK(11, 0))
285/* FIFO is 2048 bytes, let 12 samples for reading latency */
286#define INV_ICM42600_FIFO_WATERMARK_MAX (2048 - 12 * 16)
287
288#define INV_ICM42600_REG_INT_CONFIG1 0x0064
289#define INV_ICM42600_INT_CONFIG1_TPULSE_DURATION BIT(6)
290#define INV_ICM42600_INT_CONFIG1_TDEASSERT_DISABLE BIT(5)
291#define INV_ICM42600_INT_CONFIG1_ASYNC_RESET BIT(4)
292
293#define INV_ICM42600_REG_INT_SOURCE0 0x0065
294#define INV_ICM42600_INT_SOURCE0_UI_FSYNC_INT1_EN BIT(6)
295#define INV_ICM42600_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)
296#define INV_ICM42600_INT_SOURCE0_RESET_DONE_INT1_EN BIT(4)
297#define INV_ICM42600_INT_SOURCE0_UI_DRDY_INT1_EN BIT(3)
298#define INV_ICM42600_INT_SOURCE0_FIFO_THS_INT1_EN BIT(2)
299#define INV_ICM42600_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)
300#define INV_ICM42600_INT_SOURCE0_UI_AGC_RDY_INT1_EN BIT(0)
301
302#define INV_ICM42600_REG_WHOAMI 0x0075
303#define INV_ICM42600_WHOAMI_ICM42600 0x40
304#define INV_ICM42600_WHOAMI_ICM42602 0x41
305#define INV_ICM42600_WHOAMI_ICM42605 0x42
306#define INV_ICM42600_WHOAMI_ICM42622 0x46
307#define INV_ICM42600_WHOAMI_ICM42631 0x5C
308
309/* User bank 1 (MSB 0x10) */
310#define INV_ICM42600_REG_SENSOR_CONFIG0 0x1003
311#define INV_ICM42600_SENSOR_CONFIG0_ZG_DISABLE BIT(5)
312#define INV_ICM42600_SENSOR_CONFIG0_YG_DISABLE BIT(4)
313#define INV_ICM42600_SENSOR_CONFIG0_XG_DISABLE BIT(3)
314#define INV_ICM42600_SENSOR_CONFIG0_ZA_DISABLE BIT(2)
315#define INV_ICM42600_SENSOR_CONFIG0_YA_DISABLE BIT(1)
316#define INV_ICM42600_SENSOR_CONFIG0_XA_DISABLE BIT(0)
317
318/* Timestamp value is 20 bits (3 registers) in little-endian */
319#define INV_ICM42600_REG_TMSTVAL 0x1062
320#define INV_ICM42600_TMSTVAL_MASK GENMASK(19, 0)
321
322#define INV_ICM42600_REG_INTF_CONFIG4 0x107A
323#define INV_ICM42600_INTF_CONFIG4_I3C_BUS_ONLY BIT(6)
324#define INV_ICM42600_INTF_CONFIG4_SPI_AP_4WIRE BIT(1)
325
326#define INV_ICM42600_REG_INTF_CONFIG6 0x107C
327#define INV_ICM42600_INTF_CONFIG6_MASK GENMASK(4, 0)
328#define INV_ICM42600_INTF_CONFIG6_I3C_EN BIT(4)
329#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_BYTE_EN BIT(3)
330#define INV_ICM42600_INTF_CONFIG6_I3C_IBI_EN BIT(2)
331#define INV_ICM42600_INTF_CONFIG6_I3C_DDR_EN BIT(1)
332#define INV_ICM42600_INTF_CONFIG6_I3C_SDR_EN BIT(0)
333
334/* User bank 4 (MSB 0x40) */
335#define INV_ICM42600_REG_INT_SOURCE8 0x404F
336#define INV_ICM42600_INT_SOURCE8_FSYNC_IBI_EN BIT(5)
337#define INV_ICM42600_INT_SOURCE8_PLL_RDY_IBI_EN BIT(4)
338#define INV_ICM42600_INT_SOURCE8_UI_DRDY_IBI_EN BIT(3)
339#define INV_ICM42600_INT_SOURCE8_FIFO_THS_IBI_EN BIT(2)
340#define INV_ICM42600_INT_SOURCE8_FIFO_FULL_IBI_EN BIT(1)
341#define INV_ICM42600_INT_SOURCE8_AGC_RDY_IBI_EN BIT(0)
342
343#define INV_ICM42600_REG_OFFSET_USER0 0x4077
344#define INV_ICM42600_REG_OFFSET_USER1 0x4078
345#define INV_ICM42600_REG_OFFSET_USER2 0x4079
346#define INV_ICM42600_REG_OFFSET_USER3 0x407A
347#define INV_ICM42600_REG_OFFSET_USER4 0x407B
348#define INV_ICM42600_REG_OFFSET_USER5 0x407C
349#define INV_ICM42600_REG_OFFSET_USER6 0x407D
350#define INV_ICM42600_REG_OFFSET_USER7 0x407E
351#define INV_ICM42600_REG_OFFSET_USER8 0x407F
352
353/* Sleep times required by the driver */
354#define INV_ICM42600_POWER_UP_TIME_MS 100
355#define INV_ICM42600_RESET_TIME_MS 1
356#define INV_ICM42600_ACCEL_STARTUP_TIME_MS 20
357#define INV_ICM42600_GYRO_STARTUP_TIME_MS 60
358#define INV_ICM42600_GYRO_STOP_TIME_MS 150
359#define INV_ICM42600_TEMP_STARTUP_TIME_MS 14
360#define INV_ICM42600_SUSPEND_DELAY_MS 2000
361
362typedef int (*inv_icm42600_bus_setup)(struct inv_icm42600_state *);
363
364extern const struct regmap_config inv_icm42600_regmap_config;
365extern const struct dev_pm_ops inv_icm42600_pm_ops;
366
367const struct iio_mount_matrix *
368inv_icm42600_get_mount_matrix(const struct iio_dev *indio_dev,
369 const struct iio_chan_spec *chan);
370
371uint32_t inv_icm42600_odr_to_period(enum inv_icm42600_odr odr);
372
373int inv_icm42600_set_accel_conf(struct inv_icm42600_state *st,
374 struct inv_icm42600_sensor_conf *conf,
375 unsigned int *sleep_ms);
376
377int inv_icm42600_set_gyro_conf(struct inv_icm42600_state *st,
378 struct inv_icm42600_sensor_conf *conf,
379 unsigned int *sleep_ms);
380
381int inv_icm42600_set_temp_conf(struct inv_icm42600_state *st, bool enable,
382 unsigned int *sleep_ms);
383
384int inv_icm42600_debugfs_reg(struct iio_dev *indio_dev, unsigned int reg,
385 unsigned int writeval, unsigned int *readval);
386
387int inv_icm42600_core_probe(struct regmap *regmap, int chip, int irq,
388 inv_icm42600_bus_setup bus_setup);
389
390struct iio_dev *inv_icm42600_gyro_init(struct inv_icm42600_state *st);
391
392int inv_icm42600_gyro_parse_fifo(struct iio_dev *indio_dev);
393
394struct iio_dev *inv_icm42600_accel_init(struct inv_icm42600_state *st);
395
396int inv_icm42600_accel_parse_fifo(struct iio_dev *indio_dev);
397
398#endif