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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 | // SPDX-License-Identifier: GPL-2.0 /* * IIO driver for Texas Instruments ADS7924 ADC, 12-bit, 4-Channels, I2C * * Author: Hugo Villeneuve <hvilleneuve@dimonoff.com> * Copyright 2022 DimOnOff * * based on iio/adc/ti-ads1015.c * Copyright (c) 2016, Intel Corporation. * * Datasheet: https://www.ti.com/lit/gpn/ads7924 */ #include <linux/bitfield.h> #include <linux/delay.h> #include <linux/gpio/consumer.h> #include <linux/init.h> #include <linux/irq.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/mutex.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/iio/iio.h> #include <linux/iio/types.h> #define ADS7924_CHANNELS 4 #define ADS7924_BITS 12 #define ADS7924_DATA_SHIFT 4 /* Registers. */ #define ADS7924_MODECNTRL_REG 0x00 #define ADS7924_INTCNTRL_REG 0x01 #define ADS7924_DATA0_U_REG 0x02 #define ADS7924_DATA0_L_REG 0x03 #define ADS7924_DATA1_U_REG 0x04 #define ADS7924_DATA1_L_REG 0x05 #define ADS7924_DATA2_U_REG 0x06 #define ADS7924_DATA2_L_REG 0x07 #define ADS7924_DATA3_U_REG 0x08 #define ADS7924_DATA3_L_REG 0x09 #define ADS7924_ULR0_REG 0x0A #define ADS7924_LLR0_REG 0x0B #define ADS7924_ULR1_REG 0x0C #define ADS7924_LLR1_REG 0x0D #define ADS7924_ULR2_REG 0x0E #define ADS7924_LLR2_REG 0x0F #define ADS7924_ULR3_REG 0x10 #define ADS7924_LLR3_REG 0x11 #define ADS7924_INTCONFIG_REG 0x12 #define ADS7924_SLPCONFIG_REG 0x13 #define ADS7924_ACQCONFIG_REG 0x14 #define ADS7924_PWRCONFIG_REG 0x15 #define ADS7924_RESET_REG 0x16 /* * Register address INC bit: when set to '1', the register address is * automatically incremented after every register read which allows convenient * reading of multiple registers. Set INC to '0' when reading a single register. */ #define ADS7924_AUTO_INCREMENT_BIT BIT(7) #define ADS7924_MODECNTRL_MODE_MASK GENMASK(7, 2) #define ADS7924_MODECNTRL_SEL_MASK GENMASK(1, 0) #define ADS7924_CFG_INTPOL_BIT 1 #define ADS7924_CFG_INTTRIG_BIT 0 #define ADS7924_CFG_INTPOL_MASK BIT(ADS7924_CFG_INTPOL_BIT) #define ADS7924_CFG_INTTRIG_MASK BIT(ADS7924_CFG_INTTRIG_BIT) /* Interrupt pin polarity */ #define ADS7924_CFG_INTPOL_LOW 0 #define ADS7924_CFG_INTPOL_HIGH 1 /* Interrupt pin signaling */ #define ADS7924_CFG_INTTRIG_LEVEL 0 #define ADS7924_CFG_INTTRIG_EDGE 1 /* Mode control values */ #define ADS7924_MODECNTRL_IDLE 0x00 #define ADS7924_MODECNTRL_AWAKE 0x20 #define ADS7924_MODECNTRL_MANUAL_SINGLE 0x30 #define ADS7924_MODECNTRL_MANUAL_SCAN 0x32 #define ADS7924_MODECNTRL_AUTO_SINGLE 0x31 #define ADS7924_MODECNTRL_AUTO_SCAN 0x33 #define ADS7924_MODECNTRL_AUTO_SINGLE_SLEEP 0x39 #define ADS7924_MODECNTRL_AUTO_SCAN_SLEEP 0x3B #define ADS7924_MODECNTRL_AUTO_BURST_SLEEP 0x3F #define ADS7924_ACQTIME_MASK GENMASK(4, 0) #define ADS7924_PWRUPTIME_MASK GENMASK(4, 0) /* * The power-up time is allowed to elapse whenever the device has been shutdown * in idle mode. Power-up time can allow external circuits, such as an * operational amplifier, between the MUXOUT and ADCIN pins to turn on. * The nominal time programmed by the PUTIME[4:0] register bits is given by: * t PU = PWRUPTIME[4:0] × 2 μs * If a power-up time is not required, set the bits to '0' to effectively bypass. */ #define ADS7924_PWRUPTIME_US 0 /* Bypass (0us). */ /* * Acquisition Time according to ACQTIME[4:0] register bits. * The Acquisition Time is given by: * t ACQ = (ACQTIME[4:0] × 2 μs) + 6 μs * Using default value of 0 for ACQTIME[4:0] results in a minimum acquisition * time of 6us. */ #define ADS7924_ACQTIME_US 6 /* The conversion time is always 4μs and cannot be programmed by the user. */ #define ADS7924_CONVTIME_US 4 #define ADS7924_TOTAL_CONVTIME_US (ADS7924_PWRUPTIME_US + ADS7924_ACQTIME_US + \ ADS7924_CONVTIME_US) #define ADS7924_V_CHAN(_chan, _addr) { \ .type = IIO_VOLTAGE, \ .indexed = 1, \ .channel = _chan, \ .address = _addr, \ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ .datasheet_name = "AIN"#_chan, \ } struct ads7924_data { struct device *dev; struct regmap *regmap; struct regulator *vref_reg; /* GPIO descriptor for device hard-reset pin. */ struct gpio_desc *reset_gpio; /* * Protects ADC ops, e.g: concurrent sysfs/buffered * data reads, configuration updates */ struct mutex lock; /* * Set to true when the ADC is switched to the continuous-conversion * mode and exits from a power-down state. This flag is used to avoid * getting the stale result from the conversion register. */ bool conv_invalid; }; static bool ads7924_is_writeable_reg(struct device *dev, unsigned int reg) { switch (reg) { case ADS7924_MODECNTRL_REG: case ADS7924_INTCNTRL_REG: case ADS7924_ULR0_REG: case ADS7924_LLR0_REG: case ADS7924_ULR1_REG: case ADS7924_LLR1_REG: case ADS7924_ULR2_REG: case ADS7924_LLR2_REG: case ADS7924_ULR3_REG: case ADS7924_LLR3_REG: case ADS7924_INTCONFIG_REG: case ADS7924_SLPCONFIG_REG: case ADS7924_ACQCONFIG_REG: case ADS7924_PWRCONFIG_REG: case ADS7924_RESET_REG: return true; default: return false; } } static const struct regmap_config ads7924_regmap_config = { .reg_bits = 8, .val_bits = 8, .max_register = ADS7924_RESET_REG, .writeable_reg = ads7924_is_writeable_reg, }; static const struct iio_chan_spec ads7924_channels[] = { ADS7924_V_CHAN(0, ADS7924_DATA0_U_REG), ADS7924_V_CHAN(1, ADS7924_DATA1_U_REG), ADS7924_V_CHAN(2, ADS7924_DATA2_U_REG), ADS7924_V_CHAN(3, ADS7924_DATA3_U_REG), }; static int ads7924_get_adc_result(struct ads7924_data *data, struct iio_chan_spec const *chan, int *val) { int ret; __be16 be_val; if (chan->channel < 0 || chan->channel >= ADS7924_CHANNELS) return -EINVAL; if (data->conv_invalid) { int conv_time; conv_time = ADS7924_TOTAL_CONVTIME_US; /* Allow 10% for internal clock inaccuracy. */ conv_time += conv_time / 10; usleep_range(conv_time, conv_time + 1); data->conv_invalid = false; } ret = regmap_raw_read(data->regmap, ADS7924_AUTO_INCREMENT_BIT | chan->address, &be_val, sizeof(be_val)); if (ret) return ret; *val = be16_to_cpu(be_val) >> ADS7924_DATA_SHIFT; return 0; } static int ads7924_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, int *val2, long mask) { int ret, vref_uv; struct ads7924_data *data = iio_priv(indio_dev); switch (mask) { case IIO_CHAN_INFO_RAW: mutex_lock(&data->lock); ret = ads7924_get_adc_result(data, chan, val); mutex_unlock(&data->lock); if (ret < 0) return ret; return IIO_VAL_INT; case IIO_CHAN_INFO_SCALE: vref_uv = regulator_get_voltage(data->vref_reg); if (vref_uv < 0) return vref_uv; *val = vref_uv / 1000; /* Convert reg voltage to mV */ *val2 = ADS7924_BITS; return IIO_VAL_FRACTIONAL_LOG2; default: return -EINVAL; } } static const struct iio_info ads7924_info = { .read_raw = ads7924_read_raw, }; static int ads7924_get_channels_config(struct i2c_client *client, struct iio_dev *indio_dev) { struct ads7924_data *priv = iio_priv(indio_dev); struct device *dev = priv->dev; struct fwnode_handle *node; int num_channels = 0; device_for_each_child_node(dev, node) { u32 pval; unsigned int channel; if (fwnode_property_read_u32(node, "reg", &pval)) { dev_err(dev, "invalid reg on %pfw\n", node); continue; } channel = pval; if (channel >= ADS7924_CHANNELS) { dev_err(dev, "invalid channel index %d on %pfw\n", channel, node); continue; } num_channels++; } if (!num_channels) return -EINVAL; return 0; } static int ads7924_set_conv_mode(struct ads7924_data *data, int mode) { int ret; unsigned int mode_field; struct device *dev = data->dev; /* * When switching between modes, be sure to first select the Awake mode * and then switch to the desired mode. This procedure ensures the * internal control logic is properly synchronized. */ if (mode != ADS7924_MODECNTRL_IDLE) { mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, ADS7924_MODECNTRL_AWAKE); ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG, ADS7924_MODECNTRL_MODE_MASK, mode_field); if (ret) { dev_err(dev, "failed to set awake mode (%pe)\n", ERR_PTR(ret)); return ret; } } mode_field = FIELD_PREP(ADS7924_MODECNTRL_MODE_MASK, mode); ret = regmap_update_bits(data->regmap, ADS7924_MODECNTRL_REG, ADS7924_MODECNTRL_MODE_MASK, mode_field); if (ret) dev_err(dev, "failed to set mode %d (%pe)\n", mode, ERR_PTR(ret)); return ret; } static int ads7924_reset(struct iio_dev *indio_dev) { struct ads7924_data *data = iio_priv(indio_dev); if (data->reset_gpio) { gpiod_set_value(data->reset_gpio, 1); /* Assert. */ /* Educated guess: assert time not specified in datasheet... */ mdelay(100); gpiod_set_value(data->reset_gpio, 0); /* Deassert. */ return 0; } /* * A write of 10101010 to this register will generate a * software reset of the ADS7924. */ return regmap_write(data->regmap, ADS7924_RESET_REG, 0b10101010); }; static void ads7924_reg_disable(void *data) { regulator_disable(data); } static void ads7924_set_idle_mode(void *data) { ads7924_set_conv_mode(data, ADS7924_MODECNTRL_IDLE); } static int ads7924_probe(struct i2c_client *client) { struct iio_dev *indio_dev; struct ads7924_data *data; struct device *dev = &client->dev; int ret; indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); if (!indio_dev) return dev_err_probe(dev, -ENOMEM, "failed to allocate iio device\n"); data = iio_priv(indio_dev); data->dev = dev; /* Initialize the reset GPIO as output with an initial value of 0. */ data->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(data->reset_gpio)) return dev_err_probe(dev, PTR_ERR(data->reset_gpio), "failed to get request reset GPIO\n"); mutex_init(&data->lock); indio_dev->name = "ads7924"; indio_dev->modes = INDIO_DIRECT_MODE; indio_dev->channels = ads7924_channels; indio_dev->num_channels = ARRAY_SIZE(ads7924_channels); indio_dev->info = &ads7924_info; ret = ads7924_get_channels_config(client, indio_dev); if (ret < 0) return dev_err_probe(dev, ret, "failed to get channels configuration\n"); data->regmap = devm_regmap_init_i2c(client, &ads7924_regmap_config); if (IS_ERR(data->regmap)) return dev_err_probe(dev, PTR_ERR(data->regmap), "failed to init regmap\n"); data->vref_reg = devm_regulator_get(dev, "vref"); if (IS_ERR(data->vref_reg)) return dev_err_probe(dev, PTR_ERR(data->vref_reg), "failed to get vref regulator\n"); ret = regulator_enable(data->vref_reg); if (ret) return dev_err_probe(dev, ret, "failed to enable regulator\n"); ret = devm_add_action_or_reset(dev, ads7924_reg_disable, data->vref_reg); if (ret) return dev_err_probe(dev, ret, "failed to add regulator disable action\n"); ret = ads7924_reset(indio_dev); if (ret < 0) return dev_err_probe(dev, ret, "failed to reset device\n"); ret = ads7924_set_conv_mode(data, ADS7924_MODECNTRL_AUTO_SCAN); if (ret) return dev_err_probe(dev, ret, "failed to set conversion mode\n"); ret = devm_add_action_or_reset(dev, ads7924_set_idle_mode, data); if (ret) return dev_err_probe(dev, ret, "failed to add idle mode action\n"); /* Use minimum signal acquire time. */ ret = regmap_update_bits(data->regmap, ADS7924_ACQCONFIG_REG, ADS7924_ACQTIME_MASK, FIELD_PREP(ADS7924_ACQTIME_MASK, 0)); if (ret < 0) return dev_err_probe(dev, ret, "failed to configure signal acquire time\n"); /* Disable power-up time. */ ret = regmap_update_bits(data->regmap, ADS7924_PWRCONFIG_REG, ADS7924_PWRUPTIME_MASK, FIELD_PREP(ADS7924_PWRUPTIME_MASK, 0)); if (ret < 0) return dev_err_probe(dev, ret, "failed to configure power-up time\n"); data->conv_invalid = true; ret = devm_iio_device_register(dev, indio_dev); if (ret < 0) return dev_err_probe(dev, ret, "failed to register IIO device\n"); return 0; } static const struct i2c_device_id ads7924_id[] = { { "ads7924", 0 }, {} }; MODULE_DEVICE_TABLE(i2c, ads7924_id); static const struct of_device_id ads7924_of_match[] = { { .compatible = "ti,ads7924", }, {} }; MODULE_DEVICE_TABLE(of, ads7924_of_match); static struct i2c_driver ads7924_driver = { .driver = { .name = "ads7924", .of_match_table = ads7924_of_match, }, .probe = ads7924_probe, .id_table = ads7924_id, }; module_i2c_driver(ads7924_driver); MODULE_AUTHOR("Hugo Villeneuve <hvilleneuve@dimonoff.com>"); MODULE_DESCRIPTION("Texas Instruments ADS7924 ADC I2C driver"); MODULE_LICENSE("GPL"); |