1/* SPDX-License-Identifier: GPL-2.0-only */
  2/*
  3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  4 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
  5 */
  6
  7#ifndef _DPU_HW_INTF_H
  8#define _DPU_HW_INTF_H
  9
 10#include "dpu_hw_catalog.h"
 11#include "dpu_hw_mdss.h"
 12#include "dpu_hw_util.h"
 13
 14struct dpu_hw_intf;
 15
 16/* intf timing settings */
 17struct dpu_hw_intf_timing_params {
 18	u32 width;		/* active width */
 19	u32 height;		/* active height */
 20	u32 xres;		/* Display panel width */
 21	u32 yres;		/* Display panel height */
 22
 23	u32 h_back_porch;
 24	u32 h_front_porch;
 25	u32 v_back_porch;
 26	u32 v_front_porch;
 27	u32 hsync_pulse_width;
 28	u32 vsync_pulse_width;
 29	u32 hsync_polarity;
 30	u32 vsync_polarity;
 31	u32 border_clr;
 32	u32 underflow_clr;
 33	u32 hsync_skew;
 34
 35	bool wide_bus_en;
 36	bool compression_en;
 37};
 38
 39struct dpu_hw_intf_prog_fetch {
 40	u8 enable;
 41	/* vsync counter for the front porch pixel line */
 42	u32 fetch_start;
 43};
 44
 45struct dpu_hw_intf_status {
 46	u8 is_en;		/* interface timing engine is enabled or not */
 47	u8 is_prog_fetch_en;	/* interface prog fetch counter is enabled or not */
 48	u32 frame_count;	/* frame count since timing engine enabled */
 49	u32 line_count;		/* current line count including blanking */
 50};
 51
 52struct dpu_hw_intf_cmd_mode_cfg {
 53	u8 data_compress;	/* enable data compress between dpu and dsi */
 54	u8 wide_bus_en;		/* enable databus widen mode */
 55};
 56
 57/**
 58 * struct dpu_hw_intf_ops : Interface to the interface Hw driver functions
 59 *  Assumption is these functions will be called after clocks are enabled
 60 * @ setup_timing_gen : programs the timing engine
 61 * @ setup_prog_fetch : enables/disables the programmable fetch logic
 62 * @ enable_timing: enable/disable timing engine
 63 * @ get_status: returns if timing engine is enabled or not
 64 * @ get_line_count: reads current vertical line counter
 65 * @bind_pingpong_blk: enable/disable the connection with pingpong which will
 66 *                     feed pixels to this interface
 67 * @setup_misr: enable/disable MISR
 68 * @collect_misr: read MISR signature
 69 * @enable_tearcheck:           Enables vsync generation and sets up init value of read
 70 *                              pointer and programs the tear check configuration
 71 * @disable_tearcheck:          Disables tearcheck block
 72 * @connect_external_te:        Read, modify, write to either set or clear listening to external TE
 73 *                              Return: 1 if TE was originally connected, 0 if not, or -ERROR
 74 * @get_vsync_info:             Provides the programmed and current line_count
 75 * @setup_autorefresh:          Configure and enable the autorefresh config
 76 * @get_autorefresh:            Retrieve autorefresh config from hardware
 77 *                              Return: 0 on success, -ETIMEDOUT on timeout
 78 * @vsync_sel:                  Select vsync signal for tear-effect configuration
 79 * @program_intf_cmd_cfg:       Program the DPU to interface datapath for command mode
 80 */
 81struct dpu_hw_intf_ops {
 82	void (*setup_timing_gen)(struct dpu_hw_intf *intf,
 83			const struct dpu_hw_intf_timing_params *p,
 84			const struct dpu_format *fmt);
 85
 86	void (*setup_prg_fetch)(struct dpu_hw_intf *intf,
 87			const struct dpu_hw_intf_prog_fetch *fetch);
 88
 89	void (*enable_timing)(struct dpu_hw_intf *intf,
 90			u8 enable);
 91
 92	void (*get_status)(struct dpu_hw_intf *intf,
 93			struct dpu_hw_intf_status *status);
 94
 95	u32 (*get_line_count)(struct dpu_hw_intf *intf);
 96
 97	void (*bind_pingpong_blk)(struct dpu_hw_intf *intf,
 98			const enum dpu_pingpong pp);
 99	void (*setup_misr)(struct dpu_hw_intf *intf);
100	int (*collect_misr)(struct dpu_hw_intf *intf, u32 *misr_value);
101
102	// Tearcheck on INTF since DPU 5.0.0
103
104	int (*enable_tearcheck)(struct dpu_hw_intf *intf, struct dpu_hw_tear_check *cfg);
105
106	int (*disable_tearcheck)(struct dpu_hw_intf *intf);
107
108	int (*connect_external_te)(struct dpu_hw_intf *intf, bool enable_external_te);
109
110	void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
111
112	/**
113	 * Disable autorefresh if enabled
114	 */
115	void (*disable_autorefresh)(struct dpu_hw_intf *intf, uint32_t encoder_id, u16 vdisplay);
116
117	void (*program_intf_cmd_cfg)(struct dpu_hw_intf *intf,
118				     struct dpu_hw_intf_cmd_mode_cfg *cmd_mode_cfg);
119};
120
121struct dpu_hw_intf {
122	struct dpu_hw_blk_reg_map hw;
123
124	/* intf */
125	enum dpu_intf idx;
126	const struct dpu_intf_cfg *cap;
127
128	/* ops */
129	struct dpu_hw_intf_ops ops;
130};
131
132/**
133 * dpu_hw_intf_init() - Initializes the INTF driver for the passed
134 * interface catalog entry.
135 * @dev:  Corresponding device for devres management
136 * @cfg:  interface catalog entry for which driver object is required
137 * @addr: mapped register io address of MDP
138 * @mdss_rev: dpu core's major and minor versions
139 */
140struct dpu_hw_intf *dpu_hw_intf_init(struct drm_device *dev,
141				     const struct dpu_intf_cfg *cfg,
142				     void __iomem *addr,
143				     const struct dpu_mdss_version *mdss_rev);
144
145#endif /*_DPU_HW_INTF_H */