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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 | /* * Copyright(c) 2011-2016 Intel Corporation. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice (including the next * paragraph) shall be included in all copies or substantial portions of the * Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #include <linux/acpi.h> #include "i915_drv.h" #include "gvt.h" /* * Note: Only for GVT-g virtual VBT generation, other usage must * not do like this. */ #define _INTEL_BIOS_PRIVATE #include "display/intel_vbt_defs.h" #define OPREGION_SIGNATURE "IntelGraphicsMem" #define MBOX_VBT (1<<3) /* device handle */ #define DEVICE_TYPE_CRT 0x01 #define DEVICE_TYPE_EFP1 0x04 #define DEVICE_TYPE_EFP2 0x40 #define DEVICE_TYPE_EFP3 0x20 #define DEVICE_TYPE_EFP4 0x10 struct opregion_header { u8 signature[16]; u32 size; u32 opregion_ver; u8 bios_ver[32]; u8 vbios_ver[16]; u8 driver_ver[16]; u32 mboxes; u32 driver_model; u32 pcon; u8 dver[32]; u8 rsvd[124]; } __packed; struct bdb_data_header { u8 id; u16 size; /* data size */ } __packed; /* For supporting windows guest with opregion, here hardcode the emulated * bdb header version as '186', and the corresponding child_device_config * length should be '33' but not '38'. */ struct efp_child_device_config { u16 handle; u16 device_type; u16 device_class; u8 i2c_speed; u8 dp_onboard_redriver; /* 158 */ u8 dp_ondock_redriver; /* 158 */ u8 hdmi_level_shifter_value:4; /* 169 */ u8 hdmi_max_data_rate:4; /* 204 */ u16 dtd_buf_ptr; /* 161 */ u8 edidless_efp:1; /* 161 */ u8 compression_enable:1; /* 198 */ u8 compression_method:1; /* 198 */ u8 ganged_edp:1; /* 202 */ u8 skip0:4; u8 compression_structure_index:4; /* 198 */ u8 skip1:4; u8 slave_port; /* 202 */ u8 skip2; u8 dvo_port; u8 i2c_pin; /* for add-in card */ u8 slave_addr; /* for add-in card */ u8 ddc_pin; u16 edid_ptr; u8 dvo_config; u8 efp_docked_port:1; /* 158 */ u8 lane_reversal:1; /* 184 */ u8 onboard_lspcon:1; /* 192 */ u8 iboost_enable:1; /* 196 */ u8 hpd_invert:1; /* BXT 196 */ u8 slip3:3; u8 hdmi_compat:1; u8 dp_compat:1; u8 tmds_compat:1; u8 skip4:5; u8 aux_channel; u8 dongle_detect; u8 pipe_cap:2; u8 sdvo_stall:1; /* 158 */ u8 hpd_status:2; u8 integrated_encoder:1; u8 skip5:2; u8 dvo_wiring; u8 mipi_bridge_type; /* 171 */ u16 device_class_ext; u8 dvo_function; } __packed; struct vbt { /* header->bdb_offset point to bdb_header offset */ struct vbt_header header; struct bdb_header bdb_header; struct bdb_data_header general_features_header; struct bdb_general_features general_features; struct bdb_data_header general_definitions_header; struct bdb_general_definitions general_definitions; struct efp_child_device_config child0; struct efp_child_device_config child1; struct efp_child_device_config child2; struct efp_child_device_config child3; struct bdb_data_header driver_features_header; struct bdb_driver_features driver_features; }; static void virt_vbt_generation(struct vbt *v) { int num_child; memset(v, 0, sizeof(struct vbt)); v->header.signature[0] = '$'; v->header.signature[1] = 'V'; v->header.signature[2] = 'B'; v->header.signature[3] = 'T'; /* there's features depending on version! */ v->header.version = 155; v->header.header_size = sizeof(v->header); v->header.vbt_size = sizeof(struct vbt); v->header.bdb_offset = offsetof(struct vbt, bdb_header); strcpy(&v->bdb_header.signature[0], "BIOS_DATA_BLOCK"); v->bdb_header.version = 186; /* child_dev_size = 33 */ v->bdb_header.header_size = sizeof(v->bdb_header); v->bdb_header.bdb_size = sizeof(struct vbt) - sizeof(struct vbt_header); /* general features */ v->general_features_header.id = BDB_GENERAL_FEATURES; v->general_features_header.size = sizeof(struct bdb_general_features); v->general_features.int_crt_support = 0; v->general_features.int_tv_support = 0; /* child device */ num_child = 4; /* each port has one child */ v->general_definitions.child_dev_size = sizeof(struct efp_child_device_config); v->general_definitions_header.id = BDB_GENERAL_DEFINITIONS; /* size will include child devices */ v->general_definitions_header.size = sizeof(struct bdb_general_definitions) + num_child * v->general_definitions.child_dev_size; /* portA */ v->child0.handle = DEVICE_TYPE_EFP1; v->child0.device_type = DEVICE_TYPE_DP; v->child0.dvo_port = DVO_PORT_DPA; v->child0.aux_channel = DP_AUX_A; v->child0.dp_compat = true; v->child0.integrated_encoder = true; /* portB */ v->child1.handle = DEVICE_TYPE_EFP2; v->child1.device_type = DEVICE_TYPE_DP; v->child1.dvo_port = DVO_PORT_DPB; v->child1.aux_channel = DP_AUX_B; v->child1.dp_compat = true; v->child1.integrated_encoder = true; /* portC */ v->child2.handle = DEVICE_TYPE_EFP3; v->child2.device_type = DEVICE_TYPE_DP; v->child2.dvo_port = DVO_PORT_DPC; v->child2.aux_channel = DP_AUX_C; v->child2.dp_compat = true; v->child2.integrated_encoder = true; /* portD */ v->child3.handle = DEVICE_TYPE_EFP4; v->child3.device_type = DEVICE_TYPE_DP; v->child3.dvo_port = DVO_PORT_DPD; v->child3.aux_channel = DP_AUX_D; v->child3.dp_compat = true; v->child3.integrated_encoder = true; /* driver features */ v->driver_features_header.id = BDB_DRIVER_FEATURES; v->driver_features_header.size = sizeof(struct bdb_driver_features); v->driver_features.lvds_config = BDB_DRIVER_FEATURE_NO_LVDS; } /** * intel_vgpu_init_opregion - initialize the stuff used to emulate opregion * @vgpu: a vGPU * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu) { u8 *buf; struct opregion_header *header; struct vbt v; const char opregion_signature[16] = OPREGION_SIGNATURE; gvt_dbg_core("init vgpu%d opregion\n", vgpu->id); vgpu_opregion(vgpu)->va = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, get_order(INTEL_GVT_OPREGION_SIZE)); if (!vgpu_opregion(vgpu)->va) { gvt_err("fail to get memory for vgpu virt opregion\n"); return -ENOMEM; } /* emulated opregion with VBT mailbox only */ buf = (u8 *)vgpu_opregion(vgpu)->va; header = (struct opregion_header *)buf; memcpy(header->signature, opregion_signature, sizeof(opregion_signature)); header->size = 0x8; header->opregion_ver = 0x02000000; header->mboxes = MBOX_VBT; /* for unknown reason, the value in LID field is incorrect * which block the windows guest, so workaround it by force * setting it to "OPEN" */ buf[INTEL_GVT_OPREGION_CLID] = 0x3; /* emulated vbt from virt vbt generation */ virt_vbt_generation(&v); memcpy(buf + INTEL_GVT_OPREGION_VBT_OFFSET, &v, sizeof(struct vbt)); return 0; } /** * intel_vgpu_opregion_base_write_handler - Opregion base register write handler * * @vgpu: a vGPU * @gpa: guest physical address of opregion * * Returns: * Zero on success, negative error code if failed. */ int intel_vgpu_opregion_base_write_handler(struct intel_vgpu *vgpu, u32 gpa) { int i; gvt_dbg_core("emulate opregion from kernel\n"); for (i = 0; i < INTEL_GVT_OPREGION_PAGES; i++) vgpu_opregion(vgpu)->gfn[i] = (gpa >> PAGE_SHIFT) + i; return 0; } /** * intel_vgpu_clean_opregion - clean the stuff used to emulate opregion * @vgpu: a vGPU * */ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu) { gvt_dbg_core("vgpu%d: clean vgpu opregion\n", vgpu->id); if (!vgpu_opregion(vgpu)->va) return; /* Guest opregion is released by VFIO */ free_pages((unsigned long)vgpu_opregion(vgpu)->va, get_order(INTEL_GVT_OPREGION_SIZE)); vgpu_opregion(vgpu)->va = NULL; } #define GVT_OPREGION_FUNC(scic) \ ({ \ u32 __ret; \ __ret = (scic & OPREGION_SCIC_FUNC_MASK) >> \ OPREGION_SCIC_FUNC_SHIFT; \ __ret; \ }) #define GVT_OPREGION_SUBFUNC(scic) \ ({ \ u32 __ret; \ __ret = (scic & OPREGION_SCIC_SUBFUNC_MASK) >> \ OPREGION_SCIC_SUBFUNC_SHIFT; \ __ret; \ }) static const char *opregion_func_name(u32 func) { const char *name = NULL; switch (func) { case 0 ... 3: case 5: case 7 ... 15: name = "Reserved"; break; case 4: name = "Get BIOS Data"; break; case 6: name = "System BIOS Callbacks"; break; default: name = "Unknown"; break; } return name; } static const char *opregion_subfunc_name(u32 subfunc) { const char *name = NULL; switch (subfunc) { case 0: name = "Supported Calls"; break; case 1: name = "Requested Callbacks"; break; case 2 ... 3: case 8 ... 9: name = "Reserved"; break; case 5: name = "Boot Display"; break; case 6: name = "TV-Standard/Video-Connector"; break; case 7: name = "Internal Graphics"; break; case 10: name = "Spread Spectrum Clocks"; break; case 11: name = "Get AKSV"; break; default: name = "Unknown"; break; } return name; }; static bool querying_capabilities(u32 scic) { u32 func, subfunc; func = GVT_OPREGION_FUNC(scic); subfunc = GVT_OPREGION_SUBFUNC(scic); if ((func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA && subfunc == INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS) || (func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSDATA && subfunc == INTEL_GVT_OPREGION_SCIC_SF_REQEUSTEDCALLBACKS) || (func == INTEL_GVT_OPREGION_SCIC_F_GETBIOSCALLBACKS && subfunc == INTEL_GVT_OPREGION_SCIC_SF_SUPPRTEDCALLS)) { return true; } return false; } /** * intel_vgpu_emulate_opregion_request - emulating OpRegion request * @vgpu: a vGPU * @swsci: SWSCI request * * Returns: * Zero on success, negative error code if failed */ int intel_vgpu_emulate_opregion_request(struct intel_vgpu *vgpu, u32 swsci) { u32 scic, parm; u32 func, subfunc; u64 scic_pa = 0, parm_pa = 0; int ret; scic_pa = (vgpu_opregion(vgpu)->gfn[0] << PAGE_SHIFT) + INTEL_GVT_OPREGION_SCIC; parm_pa = (vgpu_opregion(vgpu)->gfn[0] << PAGE_SHIFT) + INTEL_GVT_OPREGION_PARM; ret = intel_gvt_read_gpa(vgpu, scic_pa, &scic, sizeof(scic)); if (ret) { gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", ret, scic_pa, sizeof(scic)); return ret; } ret = intel_gvt_read_gpa(vgpu, parm_pa, &parm, sizeof(parm)); if (ret) { gvt_vgpu_err("guest opregion read error %d, gpa 0x%llx, len %lu\n", ret, scic_pa, sizeof(scic)); return ret; } if (!(swsci & SWSCI_SCI_SELECT)) { gvt_vgpu_err("requesting SMI service\n"); return 0; } /* ignore non 0->1 trasitions */ if ((vgpu_cfg_space(vgpu)[INTEL_GVT_PCI_SWSCI] & SWSCI_SCI_TRIGGER) || !(swsci & SWSCI_SCI_TRIGGER)) { return 0; } func = GVT_OPREGION_FUNC(scic); subfunc = GVT_OPREGION_SUBFUNC(scic); if (!querying_capabilities(scic)) { gvt_vgpu_err("requesting runtime service: func \"%s\"," " subfunc \"%s\"\n", opregion_func_name(func), opregion_subfunc_name(subfunc)); /* * emulate exit status of function call, '0' means * "failure, generic, unsupported or unknown cause" */ scic &= ~OPREGION_SCIC_EXIT_MASK; goto out; } scic = 0; parm = 0; out: ret = intel_gvt_write_gpa(vgpu, scic_pa, &scic, sizeof(scic)); if (ret) { gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", ret, scic_pa, sizeof(scic)); return ret; } ret = intel_gvt_write_gpa(vgpu, parm_pa, &parm, sizeof(parm)); if (ret) { gvt_vgpu_err("guest opregion write error %d, gpa 0x%llx, len %lu\n", ret, scic_pa, sizeof(scic)); return ret; } return 0; } |