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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright © 2023 Intel Corporation
4 */
5
6#include <drm/i915_pciids.h>
7#include <drm/drm_color_mgmt.h>
8#include <linux/pci.h>
9
10#include "i915_drv.h"
11#include "i915_reg.h"
12#include "intel_de.h"
13#include "intel_display.h"
14#include "intel_display_device.h"
15#include "intel_display_params.h"
16#include "intel_display_power.h"
17#include "intel_display_reg_defs.h"
18#include "intel_fbc.h"
19
20static const struct intel_display_device_info no_display = {};
21
22#define PIPE_A_OFFSET 0x70000
23#define PIPE_B_OFFSET 0x71000
24#define PIPE_C_OFFSET 0x72000
25#define PIPE_D_OFFSET 0x73000
26#define CHV_PIPE_C_OFFSET 0x74000
27/*
28 * There's actually no pipe EDP. Some pipe registers have
29 * simply shifted from the pipe to the transcoder, while
30 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
31 * to access such registers in transcoder EDP.
32 */
33#define PIPE_EDP_OFFSET 0x7f000
34
35/* ICL DSI 0 and 1 */
36#define PIPE_DSI0_OFFSET 0x7b000
37#define PIPE_DSI1_OFFSET 0x7b800
38
39#define TRANSCODER_A_OFFSET 0x60000
40#define TRANSCODER_B_OFFSET 0x61000
41#define TRANSCODER_C_OFFSET 0x62000
42#define CHV_TRANSCODER_C_OFFSET 0x63000
43#define TRANSCODER_D_OFFSET 0x63000
44#define TRANSCODER_EDP_OFFSET 0x6f000
45#define TRANSCODER_DSI0_OFFSET 0x6b000
46#define TRANSCODER_DSI1_OFFSET 0x6b800
47
48#define CURSOR_A_OFFSET 0x70080
49#define CURSOR_B_OFFSET 0x700c0
50#define CHV_CURSOR_C_OFFSET 0x700e0
51#define IVB_CURSOR_B_OFFSET 0x71080
52#define IVB_CURSOR_C_OFFSET 0x72080
53#define TGL_CURSOR_D_OFFSET 0x73080
54
55#define I845_PIPE_OFFSETS \
56 .pipe_offsets = { \
57 [TRANSCODER_A] = PIPE_A_OFFSET, \
58 }, \
59 .trans_offsets = { \
60 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
61 }
62
63#define I9XX_PIPE_OFFSETS \
64 .pipe_offsets = { \
65 [TRANSCODER_A] = PIPE_A_OFFSET, \
66 [TRANSCODER_B] = PIPE_B_OFFSET, \
67 }, \
68 .trans_offsets = { \
69 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
70 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
71 }
72
73#define IVB_PIPE_OFFSETS \
74 .pipe_offsets = { \
75 [TRANSCODER_A] = PIPE_A_OFFSET, \
76 [TRANSCODER_B] = PIPE_B_OFFSET, \
77 [TRANSCODER_C] = PIPE_C_OFFSET, \
78 }, \
79 .trans_offsets = { \
80 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
81 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
82 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
83 }
84
85#define HSW_PIPE_OFFSETS \
86 .pipe_offsets = { \
87 [TRANSCODER_A] = PIPE_A_OFFSET, \
88 [TRANSCODER_B] = PIPE_B_OFFSET, \
89 [TRANSCODER_C] = PIPE_C_OFFSET, \
90 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
91 }, \
92 .trans_offsets = { \
93 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
94 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
95 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
96 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
97 }
98
99#define CHV_PIPE_OFFSETS \
100 .pipe_offsets = { \
101 [TRANSCODER_A] = PIPE_A_OFFSET, \
102 [TRANSCODER_B] = PIPE_B_OFFSET, \
103 [TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
104 }, \
105 .trans_offsets = { \
106 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
107 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
108 [TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
109 }
110
111#define I845_CURSOR_OFFSETS \
112 .cursor_offsets = { \
113 [PIPE_A] = CURSOR_A_OFFSET, \
114 }
115
116#define I9XX_CURSOR_OFFSETS \
117 .cursor_offsets = { \
118 [PIPE_A] = CURSOR_A_OFFSET, \
119 [PIPE_B] = CURSOR_B_OFFSET, \
120 }
121
122#define CHV_CURSOR_OFFSETS \
123 .cursor_offsets = { \
124 [PIPE_A] = CURSOR_A_OFFSET, \
125 [PIPE_B] = CURSOR_B_OFFSET, \
126 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
127 }
128
129#define IVB_CURSOR_OFFSETS \
130 .cursor_offsets = { \
131 [PIPE_A] = CURSOR_A_OFFSET, \
132 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
133 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
134 }
135
136#define TGL_CURSOR_OFFSETS \
137 .cursor_offsets = { \
138 [PIPE_A] = CURSOR_A_OFFSET, \
139 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
140 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
141 [PIPE_D] = TGL_CURSOR_D_OFFSET, \
142 }
143
144#define I845_COLORS \
145 .color = { .gamma_lut_size = 256 }
146#define I9XX_COLORS \
147 .color = { .gamma_lut_size = 129, \
148 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
149 }
150#define ILK_COLORS \
151 .color = { .gamma_lut_size = 1024 }
152#define IVB_COLORS \
153 .color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
154#define CHV_COLORS \
155 .color = { \
156 .degamma_lut_size = 65, .gamma_lut_size = 257, \
157 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
158 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
159 }
160#define GLK_COLORS \
161 .color = { \
162 .degamma_lut_size = 33, .gamma_lut_size = 1024, \
163 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
164 DRM_COLOR_LUT_EQUAL_CHANNELS, \
165 }
166#define ICL_COLORS \
167 .color = { \
168 .degamma_lut_size = 33, .gamma_lut_size = 262145, \
169 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
170 DRM_COLOR_LUT_EQUAL_CHANNELS, \
171 .gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
172 }
173
174#define I830_DISPLAY \
175 .has_overlay = 1, \
176 .cursor_needs_physical = 1, \
177 .overlay_needs_physical = 1, \
178 .has_gmch = 1, \
179 I9XX_PIPE_OFFSETS, \
180 I9XX_CURSOR_OFFSETS, \
181 I9XX_COLORS, \
182 \
183 .__runtime_defaults.ip.ver = 2, \
184 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
185 .__runtime_defaults.cpu_transcoder_mask = \
186 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
187
188#define I845_DISPLAY \
189 .has_overlay = 1, \
190 .overlay_needs_physical = 1, \
191 .has_gmch = 1, \
192 I845_PIPE_OFFSETS, \
193 I845_CURSOR_OFFSETS, \
194 I845_COLORS, \
195 \
196 .__runtime_defaults.ip.ver = 2, \
197 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
198 .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A)
199
200static const struct intel_display_device_info i830_display = {
201 I830_DISPLAY,
202
203 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
204};
205
206static const struct intel_display_device_info i845_display = {
207 I845_DISPLAY,
208
209 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
210};
211
212static const struct intel_display_device_info i85x_display = {
213 I830_DISPLAY,
214
215 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
216 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
217};
218
219static const struct intel_display_device_info i865g_display = {
220 I845_DISPLAY,
221
222 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
223 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
224};
225
226#define GEN3_DISPLAY \
227 .has_gmch = 1, \
228 .has_overlay = 1, \
229 I9XX_PIPE_OFFSETS, \
230 I9XX_CURSOR_OFFSETS, \
231 \
232 .__runtime_defaults.ip.ver = 3, \
233 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
234 .__runtime_defaults.cpu_transcoder_mask = \
235 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
236 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
237
238static const struct intel_display_device_info i915g_display = {
239 GEN3_DISPLAY,
240 I845_COLORS,
241 .cursor_needs_physical = 1,
242 .overlay_needs_physical = 1,
243};
244
245static const struct intel_display_device_info i915gm_display = {
246 GEN3_DISPLAY,
247 I9XX_COLORS,
248 .cursor_needs_physical = 1,
249 .overlay_needs_physical = 1,
250 .supports_tv = 1,
251
252 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
253};
254
255static const struct intel_display_device_info i945g_display = {
256 GEN3_DISPLAY,
257 I845_COLORS,
258 .has_hotplug = 1,
259 .cursor_needs_physical = 1,
260 .overlay_needs_physical = 1,
261};
262
263static const struct intel_display_device_info i945gm_display = {
264 GEN3_DISPLAY,
265 I9XX_COLORS,
266 .has_hotplug = 1,
267 .cursor_needs_physical = 1,
268 .overlay_needs_physical = 1,
269 .supports_tv = 1,
270
271 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
272};
273
274static const struct intel_display_device_info g33_display = {
275 GEN3_DISPLAY,
276 I845_COLORS,
277 .has_hotplug = 1,
278};
279
280static const struct intel_display_device_info pnv_display = {
281 GEN3_DISPLAY,
282 I9XX_COLORS,
283 .has_hotplug = 1,
284};
285
286#define GEN4_DISPLAY \
287 .has_hotplug = 1, \
288 .has_gmch = 1, \
289 I9XX_PIPE_OFFSETS, \
290 I9XX_CURSOR_OFFSETS, \
291 I9XX_COLORS, \
292 \
293 .__runtime_defaults.ip.ver = 4, \
294 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
295 .__runtime_defaults.cpu_transcoder_mask = \
296 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
297
298static const struct intel_display_device_info i965g_display = {
299 GEN4_DISPLAY,
300 .has_overlay = 1,
301
302 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
303};
304
305static const struct intel_display_device_info i965gm_display = {
306 GEN4_DISPLAY,
307 .has_overlay = 1,
308 .supports_tv = 1,
309
310 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
311 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
312};
313
314static const struct intel_display_device_info g45_display = {
315 GEN4_DISPLAY,
316
317 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
318};
319
320static const struct intel_display_device_info gm45_display = {
321 GEN4_DISPLAY,
322 .supports_tv = 1,
323
324 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */
325 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
326};
327
328#define ILK_DISPLAY \
329 .has_hotplug = 1, \
330 I9XX_PIPE_OFFSETS, \
331 I9XX_CURSOR_OFFSETS, \
332 ILK_COLORS, \
333 \
334 .__runtime_defaults.ip.ver = 5, \
335 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
336 .__runtime_defaults.cpu_transcoder_mask = \
337 BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
338 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
339
340static const struct intel_display_device_info ilk_d_display = {
341 ILK_DISPLAY,
342};
343
344static const struct intel_display_device_info ilk_m_display = {
345 ILK_DISPLAY,
346
347 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
348};
349
350static const struct intel_display_device_info snb_display = {
351 .has_hotplug = 1,
352 I9XX_PIPE_OFFSETS,
353 I9XX_CURSOR_OFFSETS,
354 ILK_COLORS,
355
356 .__runtime_defaults.ip.ver = 6,
357 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
358 .__runtime_defaults.cpu_transcoder_mask =
359 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
360 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
361 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
362};
363
364static const struct intel_display_device_info ivb_display = {
365 .has_hotplug = 1,
366 IVB_PIPE_OFFSETS,
367 IVB_CURSOR_OFFSETS,
368 IVB_COLORS,
369
370 .__runtime_defaults.ip.ver = 7,
371 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
372 .__runtime_defaults.cpu_transcoder_mask =
373 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
374 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */
375 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
376};
377
378static const struct intel_display_device_info vlv_display = {
379 .has_gmch = 1,
380 .has_hotplug = 1,
381 .mmio_offset = VLV_DISPLAY_BASE,
382 I9XX_PIPE_OFFSETS,
383 I9XX_CURSOR_OFFSETS,
384 I9XX_COLORS,
385
386 .__runtime_defaults.ip.ver = 7,
387 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
388 .__runtime_defaults.cpu_transcoder_mask =
389 BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
390 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */
391};
392
393static const struct intel_display_device_info hsw_display = {
394 .has_ddi = 1,
395 .has_dp_mst = 1,
396 .has_fpga_dbg = 1,
397 .has_hotplug = 1,
398 .has_psr = 1,
399 .has_psr_hw_tracking = 1,
400 HSW_PIPE_OFFSETS,
401 IVB_CURSOR_OFFSETS,
402 IVB_COLORS,
403
404 .__runtime_defaults.ip.ver = 7,
405 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
406 .__runtime_defaults.cpu_transcoder_mask =
407 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
408 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
409 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
410 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
411};
412
413static const struct intel_display_device_info bdw_display = {
414 .has_ddi = 1,
415 .has_dp_mst = 1,
416 .has_fpga_dbg = 1,
417 .has_hotplug = 1,
418 .has_psr = 1,
419 .has_psr_hw_tracking = 1,
420 HSW_PIPE_OFFSETS,
421 IVB_CURSOR_OFFSETS,
422 IVB_COLORS,
423
424 .__runtime_defaults.ip.ver = 8,
425 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
426 .__runtime_defaults.cpu_transcoder_mask =
427 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
428 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
429 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
430 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
431};
432
433static const struct intel_display_device_info chv_display = {
434 .has_hotplug = 1,
435 .has_gmch = 1,
436 .mmio_offset = VLV_DISPLAY_BASE,
437 CHV_PIPE_OFFSETS,
438 CHV_CURSOR_OFFSETS,
439 CHV_COLORS,
440
441 .__runtime_defaults.ip.ver = 8,
442 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
443 .__runtime_defaults.cpu_transcoder_mask =
444 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
445 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */
446};
447
448static const struct intel_display_device_info skl_display = {
449 .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */
450 .dbuf.slice_mask = BIT(DBUF_S1),
451 .has_ddi = 1,
452 .has_dp_mst = 1,
453 .has_fpga_dbg = 1,
454 .has_hotplug = 1,
455 .has_ipc = 1,
456 .has_psr = 1,
457 .has_psr_hw_tracking = 1,
458 HSW_PIPE_OFFSETS,
459 IVB_CURSOR_OFFSETS,
460 IVB_COLORS,
461
462 .__runtime_defaults.ip.ver = 9,
463 .__runtime_defaults.has_dmc = 1,
464 .__runtime_defaults.has_hdcp = 1,
465 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
466 .__runtime_defaults.cpu_transcoder_mask =
467 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
468 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP),
469 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
470 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A),
471};
472
473#define GEN9_LP_DISPLAY \
474 .dbuf.slice_mask = BIT(DBUF_S1), \
475 .has_dp_mst = 1, \
476 .has_ddi = 1, \
477 .has_fpga_dbg = 1, \
478 .has_hotplug = 1, \
479 .has_ipc = 1, \
480 .has_psr = 1, \
481 .has_psr_hw_tracking = 1, \
482 HSW_PIPE_OFFSETS, \
483 IVB_CURSOR_OFFSETS, \
484 IVB_COLORS, \
485 \
486 .__runtime_defaults.has_dmc = 1, \
487 .__runtime_defaults.has_hdcp = 1, \
488 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
489 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
490 .__runtime_defaults.cpu_transcoder_mask = \
491 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
492 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
493 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
494 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
495
496static const struct intel_display_device_info bxt_display = {
497 GEN9_LP_DISPLAY,
498 .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
499
500 .__runtime_defaults.ip.ver = 9,
501};
502
503static const struct intel_display_device_info glk_display = {
504 GEN9_LP_DISPLAY,
505 .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
506 GLK_COLORS,
507
508 .__runtime_defaults.ip.ver = 10,
509};
510
511#define ICL_DISPLAY \
512 .abox_mask = BIT(0), \
513 .dbuf.size = 2048, \
514 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
515 .has_ddi = 1, \
516 .has_dp_mst = 1, \
517 .has_fpga_dbg = 1, \
518 .has_hotplug = 1, \
519 .has_ipc = 1, \
520 .has_psr = 1, \
521 .has_psr_hw_tracking = 1, \
522 .pipe_offsets = { \
523 [TRANSCODER_A] = PIPE_A_OFFSET, \
524 [TRANSCODER_B] = PIPE_B_OFFSET, \
525 [TRANSCODER_C] = PIPE_C_OFFSET, \
526 [TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
527 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
528 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
529 }, \
530 .trans_offsets = { \
531 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
532 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
533 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
534 [TRANSCODER_EDP] = TRANSCODER_EDP_OFFSET, \
535 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
536 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
537 }, \
538 IVB_CURSOR_OFFSETS, \
539 ICL_COLORS, \
540 \
541 .__runtime_defaults.ip.ver = 11, \
542 .__runtime_defaults.has_dmc = 1, \
543 .__runtime_defaults.has_dsc = 1, \
544 .__runtime_defaults.has_hdcp = 1, \
545 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
546 .__runtime_defaults.cpu_transcoder_mask = \
547 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
548 BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
549 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
550 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
551
552static const struct intel_display_device_info icl_display = {
553 ICL_DISPLAY,
554
555 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
556};
557
558static const struct intel_display_device_info jsl_ehl_display = {
559 ICL_DISPLAY,
560
561 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
562};
563
564#define XE_D_DISPLAY \
565 .abox_mask = GENMASK(2, 1), \
566 .dbuf.size = 2048, \
567 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
568 .has_ddi = 1, \
569 .has_dp_mst = 1, \
570 .has_dsb = 1, \
571 .has_fpga_dbg = 1, \
572 .has_hotplug = 1, \
573 .has_ipc = 1, \
574 .has_psr = 1, \
575 .has_psr_hw_tracking = 1, \
576 .pipe_offsets = { \
577 [TRANSCODER_A] = PIPE_A_OFFSET, \
578 [TRANSCODER_B] = PIPE_B_OFFSET, \
579 [TRANSCODER_C] = PIPE_C_OFFSET, \
580 [TRANSCODER_D] = PIPE_D_OFFSET, \
581 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
582 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
583 }, \
584 .trans_offsets = { \
585 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
586 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
587 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
588 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
589 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
590 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
591 }, \
592 TGL_CURSOR_OFFSETS, \
593 ICL_COLORS, \
594 \
595 .__runtime_defaults.ip.ver = 12, \
596 .__runtime_defaults.has_dmc = 1, \
597 .__runtime_defaults.has_dsc = 1, \
598 .__runtime_defaults.has_hdcp = 1, \
599 .__runtime_defaults.pipe_mask = \
600 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
601 .__runtime_defaults.cpu_transcoder_mask = \
602 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
603 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
604 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
605 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A)
606
607static const struct intel_display_device_info tgl_display = {
608 XE_D_DISPLAY,
609
610 /*
611 * FIXME DDI C/combo PHY C missing due to combo PHY
612 * code making a mess on SKUs where the PHY is missing.
613 */
614 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
615 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6),
616};
617
618static const struct intel_display_device_info dg1_display = {
619 XE_D_DISPLAY,
620
621 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
622 BIT(PORT_TC1) | BIT(PORT_TC2),
623};
624
625static const struct intel_display_device_info rkl_display = {
626 XE_D_DISPLAY,
627 .abox_mask = BIT(0),
628 .has_hti = 1,
629 .has_psr_hw_tracking = 0,
630
631 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
632 .__runtime_defaults.cpu_transcoder_mask =
633 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
634 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
635 BIT(PORT_TC1) | BIT(PORT_TC2),
636};
637
638static const struct intel_display_device_info adl_s_display = {
639 XE_D_DISPLAY,
640 .has_hti = 1,
641 .has_psr_hw_tracking = 0,
642
643 .__runtime_defaults.port_mask = BIT(PORT_A) |
644 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
645};
646
647#define XE_LPD_FEATURES \
648 .abox_mask = GENMASK(1, 0), \
649 .color = { \
650 .degamma_lut_size = 129, .gamma_lut_size = 1024, \
651 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
652 DRM_COLOR_LUT_EQUAL_CHANNELS, \
653 }, \
654 .dbuf.size = 4096, \
655 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
656 BIT(DBUF_S4), \
657 .has_ddi = 1, \
658 .has_dp_mst = 1, \
659 .has_dsb = 1, \
660 .has_fpga_dbg = 1, \
661 .has_hotplug = 1, \
662 .has_ipc = 1, \
663 .has_psr = 1, \
664 .pipe_offsets = { \
665 [TRANSCODER_A] = PIPE_A_OFFSET, \
666 [TRANSCODER_B] = PIPE_B_OFFSET, \
667 [TRANSCODER_C] = PIPE_C_OFFSET, \
668 [TRANSCODER_D] = PIPE_D_OFFSET, \
669 [TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
670 [TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
671 }, \
672 .trans_offsets = { \
673 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
674 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
675 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
676 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
677 [TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
678 [TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
679 }, \
680 TGL_CURSOR_OFFSETS, \
681 \
682 .__runtime_defaults.ip.ver = 13, \
683 .__runtime_defaults.has_dmc = 1, \
684 .__runtime_defaults.has_dsc = 1, \
685 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), \
686 .__runtime_defaults.has_hdcp = 1, \
687 .__runtime_defaults.pipe_mask = \
688 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
689
690static const struct intel_display_device_info xe_lpd_display = {
691 XE_LPD_FEATURES,
692 .has_cdclk_crawl = 1,
693 .has_psr_hw_tracking = 0,
694
695 .__runtime_defaults.cpu_transcoder_mask =
696 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
697 BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
698 BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
699 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
700 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
701};
702
703static const struct intel_display_device_info xe_hpd_display = {
704 XE_LPD_FEATURES,
705 .has_cdclk_squash = 1,
706
707 .__runtime_defaults.cpu_transcoder_mask =
708 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
709 BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
710 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
711 BIT(PORT_TC1),
712};
713
714#define XE_LPDP_FEATURES \
715 .abox_mask = GENMASK(1, 0), \
716 .color = { \
717 .degamma_lut_size = 129, .gamma_lut_size = 1024, \
718 .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
719 DRM_COLOR_LUT_EQUAL_CHANNELS, \
720 }, \
721 .dbuf.size = 4096, \
722 .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
723 BIT(DBUF_S4), \
724 .has_cdclk_crawl = 1, \
725 .has_cdclk_squash = 1, \
726 .has_ddi = 1, \
727 .has_dp_mst = 1, \
728 .has_dsb = 1, \
729 .has_fpga_dbg = 1, \
730 .has_hotplug = 1, \
731 .has_ipc = 1, \
732 .has_psr = 1, \
733 .pipe_offsets = { \
734 [TRANSCODER_A] = PIPE_A_OFFSET, \
735 [TRANSCODER_B] = PIPE_B_OFFSET, \
736 [TRANSCODER_C] = PIPE_C_OFFSET, \
737 [TRANSCODER_D] = PIPE_D_OFFSET, \
738 }, \
739 .trans_offsets = { \
740 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
741 [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
742 [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
743 [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
744 }, \
745 TGL_CURSOR_OFFSETS, \
746 \
747 .__runtime_defaults.cpu_transcoder_mask = \
748 BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
749 BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
750 .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
751 .__runtime_defaults.has_dmc = 1, \
752 .__runtime_defaults.has_dsc = 1, \
753 .__runtime_defaults.has_hdcp = 1, \
754 .__runtime_defaults.pipe_mask = \
755 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
756 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
757 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
758
759static const struct intel_display_device_info xe_lpdp_display = {
760 XE_LPDP_FEATURES,
761};
762
763static const struct intel_display_device_info xe2_lpd_display = {
764 XE_LPDP_FEATURES,
765
766 .__runtime_defaults.fbc_mask =
767 BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
768 BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
769};
770
771/*
772 * Separate detection for no display cases to keep the display id array simple.
773 *
774 * IVB Q requires subvendor and subdevice matching to differentiate from IVB D
775 * GT2 server.
776 */
777static bool has_no_display(struct pci_dev *pdev)
778{
779 static const struct pci_device_id ids[] = {
780 INTEL_IVB_Q_IDS(0),
781 {}
782 };
783
784 return pci_match_id(ids, pdev);
785}
786
787#undef INTEL_VGA_DEVICE
788#define INTEL_VGA_DEVICE(id, info) { id, info }
789
790static const struct {
791 u32 devid;
792 const struct intel_display_device_info *info;
793} intel_display_ids[] = {
794 INTEL_I830_IDS(&i830_display),
795 INTEL_I845G_IDS(&i845_display),
796 INTEL_I85X_IDS(&i85x_display),
797 INTEL_I865G_IDS(&i865g_display),
798 INTEL_I915G_IDS(&i915g_display),
799 INTEL_I915GM_IDS(&i915gm_display),
800 INTEL_I945G_IDS(&i945g_display),
801 INTEL_I945GM_IDS(&i945gm_display),
802 INTEL_I965G_IDS(&i965g_display),
803 INTEL_G33_IDS(&g33_display),
804 INTEL_I965GM_IDS(&i965gm_display),
805 INTEL_GM45_IDS(&gm45_display),
806 INTEL_G45_IDS(&g45_display),
807 INTEL_PINEVIEW_G_IDS(&pnv_display),
808 INTEL_PINEVIEW_M_IDS(&pnv_display),
809 INTEL_IRONLAKE_D_IDS(&ilk_d_display),
810 INTEL_IRONLAKE_M_IDS(&ilk_m_display),
811 INTEL_SNB_D_IDS(&snb_display),
812 INTEL_SNB_M_IDS(&snb_display),
813 INTEL_IVB_M_IDS(&ivb_display),
814 INTEL_IVB_D_IDS(&ivb_display),
815 INTEL_HSW_IDS(&hsw_display),
816 INTEL_VLV_IDS(&vlv_display),
817 INTEL_BDW_IDS(&bdw_display),
818 INTEL_CHV_IDS(&chv_display),
819 INTEL_SKL_IDS(&skl_display),
820 INTEL_BXT_IDS(&bxt_display),
821 INTEL_GLK_IDS(&glk_display),
822 INTEL_KBL_IDS(&skl_display),
823 INTEL_CFL_IDS(&skl_display),
824 INTEL_ICL_11_IDS(&icl_display),
825 INTEL_EHL_IDS(&jsl_ehl_display),
826 INTEL_JSL_IDS(&jsl_ehl_display),
827 INTEL_TGL_12_IDS(&tgl_display),
828 INTEL_DG1_IDS(&dg1_display),
829 INTEL_RKL_IDS(&rkl_display),
830 INTEL_ADLS_IDS(&adl_s_display),
831 INTEL_RPLS_IDS(&adl_s_display),
832 INTEL_ADLP_IDS(&xe_lpd_display),
833 INTEL_ADLN_IDS(&xe_lpd_display),
834 INTEL_RPLP_IDS(&xe_lpd_display),
835 INTEL_DG2_IDS(&xe_hpd_display),
836
837 /*
838 * Do not add any GMD_ID-based platforms to this list. They will
839 * be probed automatically based on the IP version reported by
840 * the hardware.
841 */
842};
843
844static const struct {
845 u16 ver;
846 u16 rel;
847 const struct intel_display_device_info *display;
848} gmdid_display_map[] = {
849 { 14, 0, &xe_lpdp_display },
850 { 20, 0, &xe2_lpd_display },
851};
852
853static const struct intel_display_device_info *
854probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step)
855{
856 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
857 void __iomem *addr;
858 u32 val;
859 int i;
860
861 /* The caller expects to ver, rel and step to be initialized
862 * here, and there's no good way to check when there was a
863 * failure and no_display was returned. So initialize all these
864 * values here zero, to be sure.
865 */
866 *ver = 0;
867 *rel = 0;
868 *step = 0;
869
870 addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32));
871 if (!addr) {
872 drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n");
873 return &no_display;
874 }
875
876 val = ioread32(addr);
877 pci_iounmap(pdev, addr);
878
879 if (val == 0) {
880 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
881 return &no_display;
882 }
883
884 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
885 *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
886 *step = REG_FIELD_GET(GMD_ID_STEP, val);
887
888 for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++)
889 if (*ver == gmdid_display_map[i].ver &&
890 *rel == gmdid_display_map[i].rel)
891 return gmdid_display_map[i].display;
892
893 drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n",
894 *ver, *rel);
895 return &no_display;
896}
897
898static const struct intel_display_device_info *
899probe_display(struct drm_i915_private *i915)
900{
901 struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
902 int i;
903
904 if (has_no_display(pdev)) {
905 drm_dbg_kms(&i915->drm, "Device doesn't have display\n");
906 return &no_display;
907 }
908
909 for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) {
910 if (intel_display_ids[i].devid == pdev->device)
911 return intel_display_ids[i].info;
912 }
913
914 drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n",
915 pdev->device);
916
917 return &no_display;
918}
919
920void intel_display_device_probe(struct drm_i915_private *i915)
921{
922 const struct intel_display_device_info *info;
923 u16 ver, rel, step;
924
925 if (HAS_GMD_ID(i915))
926 info = probe_gmdid_display(i915, &ver, &rel, &step);
927 else
928 info = probe_display(i915);
929
930 DISPLAY_INFO(i915) = info;
931
932 memcpy(DISPLAY_RUNTIME_INFO(i915),
933 &DISPLAY_INFO(i915)->__runtime_defaults,
934 sizeof(*DISPLAY_RUNTIME_INFO(i915)));
935
936 if (HAS_GMD_ID(i915)) {
937 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
938 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
939 DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
940 }
941
942 intel_display_params_copy(&i915->display.params);
943}
944
945void intel_display_device_remove(struct drm_i915_private *i915)
946{
947 intel_display_params_free(&i915->display.params);
948}
949
950static void __intel_display_device_info_runtime_init(struct drm_i915_private *i915)
951{
952 struct intel_display_runtime_info *display_runtime = DISPLAY_RUNTIME_INFO(i915);
953 enum pipe pipe;
954
955 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->pipe_mask) < I915_MAX_PIPES);
956 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->cpu_transcoder_mask) < I915_MAX_TRANSCODERS);
957 BUILD_BUG_ON(BITS_PER_TYPE(display_runtime->port_mask) < I915_MAX_PORTS);
958
959 /* This covers both ULT and ULX */
960 if (IS_HASWELL_ULT(i915) || IS_BROADWELL_ULT(i915))
961 display_runtime->port_mask &= ~BIT(PORT_D);
962
963 if (IS_ICL_WITH_PORT_F(i915))
964 display_runtime->port_mask |= BIT(PORT_F);
965
966 /* Wa_14011765242: adl-s A0,A1 */
967 if (IS_ALDERLAKE_S(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_A2))
968 for_each_pipe(i915, pipe)
969 display_runtime->num_scalers[pipe] = 0;
970 else if (DISPLAY_VER(i915) >= 11) {
971 for_each_pipe(i915, pipe)
972 display_runtime->num_scalers[pipe] = 2;
973 } else if (DISPLAY_VER(i915) >= 9) {
974 display_runtime->num_scalers[PIPE_A] = 2;
975 display_runtime->num_scalers[PIPE_B] = 2;
976 display_runtime->num_scalers[PIPE_C] = 1;
977 }
978
979 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
980 for_each_pipe(i915, pipe)
981 display_runtime->num_sprites[pipe] = 4;
982 else if (DISPLAY_VER(i915) >= 11)
983 for_each_pipe(i915, pipe)
984 display_runtime->num_sprites[pipe] = 6;
985 else if (DISPLAY_VER(i915) == 10)
986 for_each_pipe(i915, pipe)
987 display_runtime->num_sprites[pipe] = 3;
988 else if (IS_BROXTON(i915)) {
989 /*
990 * Skylake and Broxton currently don't expose the topmost plane as its
991 * use is exclusive with the legacy cursor and we only want to expose
992 * one of those, not both. Until we can safely expose the topmost plane
993 * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
994 * we don't expose the topmost plane at all to prevent ABI breakage
995 * down the line.
996 */
997
998 display_runtime->num_sprites[PIPE_A] = 2;
999 display_runtime->num_sprites[PIPE_B] = 2;
1000 display_runtime->num_sprites[PIPE_C] = 1;
1001 } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
1002 for_each_pipe(i915, pipe)
1003 display_runtime->num_sprites[pipe] = 2;
1004 } else if (DISPLAY_VER(i915) >= 5 || IS_G4X(i915)) {
1005 for_each_pipe(i915, pipe)
1006 display_runtime->num_sprites[pipe] = 1;
1007 }
1008
1009 if ((IS_DGFX(i915) || DISPLAY_VER(i915) >= 14) &&
1010 !(intel_de_read(i915, GU_CNTL_PROTECTED) & DEPRESENT)) {
1011 drm_info(&i915->drm, "Display not present, disabling\n");
1012 goto display_fused_off;
1013 }
1014
1015 if (IS_DISPLAY_VER(i915, 7, 8) && HAS_PCH_SPLIT(i915)) {
1016 u32 fuse_strap = intel_de_read(i915, FUSE_STRAP);
1017 u32 sfuse_strap = intel_de_read(i915, SFUSE_STRAP);
1018
1019 /*
1020 * SFUSE_STRAP is supposed to have a bit signalling the display
1021 * is fused off. Unfortunately it seems that, at least in
1022 * certain cases, fused off display means that PCH display
1023 * reads don't land anywhere. In that case, we read 0s.
1024 *
1025 * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1026 * should be set when taking over after the firmware.
1027 */
1028 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1029 sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1030 (HAS_PCH_CPT(i915) &&
1031 !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1032 drm_info(&i915->drm,
1033 "Display fused off, disabling\n");
1034 goto display_fused_off;
1035 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
1036 drm_info(&i915->drm, "PipeC fused off\n");
1037 display_runtime->pipe_mask &= ~BIT(PIPE_C);
1038 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1039 }
1040 } else if (DISPLAY_VER(i915) >= 9) {
1041 u32 dfsm = intel_de_read(i915, SKL_DFSM);
1042
1043 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
1044 display_runtime->pipe_mask &= ~BIT(PIPE_A);
1045 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
1046 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
1047 }
1048 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
1049 display_runtime->pipe_mask &= ~BIT(PIPE_B);
1050 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
1051 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
1052 }
1053 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
1054 display_runtime->pipe_mask &= ~BIT(PIPE_C);
1055 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
1056 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
1057 }
1058
1059 if (DISPLAY_VER(i915) >= 12 &&
1060 (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
1061 display_runtime->pipe_mask &= ~BIT(PIPE_D);
1062 display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
1063 display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
1064 }
1065
1066 if (!display_runtime->pipe_mask)
1067 goto display_fused_off;
1068
1069 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
1070 display_runtime->has_hdcp = 0;
1071
1072 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
1073 display_runtime->fbc_mask = 0;
1074
1075 if (DISPLAY_VER(i915) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
1076 display_runtime->has_dmc = 0;
1077
1078 if (IS_DISPLAY_VER(i915, 10, 12) &&
1079 (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
1080 display_runtime->has_dsc = 0;
1081 }
1082
1083 if (DISPLAY_VER(i915) >= 20) {
1084 u32 cap = intel_de_read(i915, XE2LPD_DE_CAP);
1085
1086 if (REG_FIELD_GET(XE2LPD_DE_CAP_DSC_MASK, cap) ==
1087 XE2LPD_DE_CAP_DSC_REMOVED)
1088 display_runtime->has_dsc = 0;
1089
1090 if (REG_FIELD_GET(XE2LPD_DE_CAP_SCALER_MASK, cap) ==
1091 XE2LPD_DE_CAP_SCALER_SINGLE) {
1092 for_each_pipe(i915, pipe)
1093 if (display_runtime->num_scalers[pipe])
1094 display_runtime->num_scalers[pipe] = 1;
1095 }
1096 }
1097
1098 return;
1099
1100display_fused_off:
1101 memset(display_runtime, 0, sizeof(*display_runtime));
1102}
1103
1104void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
1105{
1106 if (HAS_DISPLAY(i915))
1107 __intel_display_device_info_runtime_init(i915);
1108
1109 /* Display may have been disabled by runtime init */
1110 if (!HAS_DISPLAY(i915)) {
1111 i915->drm.driver_features &= ~(DRIVER_MODESET | DRIVER_ATOMIC);
1112 i915->display.info.__device_info = &no_display;
1113 }
1114
1115 /* Disable nuclear pageflip by default on pre-g4x */
1116 if (!i915->display.params.nuclear_pageflip &&
1117 DISPLAY_VER(i915) < 5 && !IS_G4X(i915))
1118 i915->drm.driver_features &= ~DRIVER_ATOMIC;
1119}
1120
1121void intel_display_device_info_print(const struct intel_display_device_info *info,
1122 const struct intel_display_runtime_info *runtime,
1123 struct drm_printer *p)
1124{
1125 if (runtime->ip.rel)
1126 drm_printf(p, "display version: %u.%02u\n",
1127 runtime->ip.ver,
1128 runtime->ip.rel);
1129 else
1130 drm_printf(p, "display version: %u\n",
1131 runtime->ip.ver);
1132
1133#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
1134 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
1135#undef PRINT_FLAG
1136
1137 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp));
1138 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc));
1139 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc));
1140}
1141
1142/*
1143 * Assuming the device has display hardware, should it be enabled?
1144 *
1145 * It's an error to call this function if the device does not have display
1146 * hardware.
1147 *
1148 * Disabling display means taking over the display hardware, putting it to
1149 * sleep, and preventing connectors from being connected via any means.
1150 */
1151bool intel_display_device_enabled(struct drm_i915_private *i915)
1152{
1153 /* Only valid when HAS_DISPLAY() is true */
1154 drm_WARN_ON(&i915->drm, !HAS_DISPLAY(i915));
1155
1156 return !i915->display.params.disable_display &&
1157 !intel_opregion_headless_sku(i915);
1158}