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1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _VEGA12_HWMGR_H_
25#define _VEGA12_HWMGR_H_
26
27#include "hwmgr.h"
28#include "vega12/smu9_driver_if.h"
29#include "ppatomfwctrl.h"
30
31#define VEGA12_MAX_HARDWARE_POWERLEVELS 2
32
33#define WaterMarksExist 1
34#define WaterMarksLoaded 2
35
36#define VG12_PSUEDO_NUM_GFXCLK_DPM_LEVELS 16
37#define VG12_PSUEDO_NUM_SOCCLK_DPM_LEVELS 8
38#define VG12_PSUEDO_NUM_DCEFCLK_DPM_LEVELS 8
39#define VG12_PSUEDO_NUM_UCLK_DPM_LEVELS 4
40
41enum {
42 GNLD_DPM_PREFETCHER = 0,
43 GNLD_DPM_GFXCLK,
44 GNLD_DPM_UCLK,
45 GNLD_DPM_SOCCLK,
46 GNLD_DPM_UVD,
47 GNLD_DPM_VCE,
48 GNLD_ULV,
49 GNLD_DPM_MP0CLK,
50 GNLD_DPM_LINK,
51 GNLD_DPM_DCEFCLK,
52 GNLD_DS_GFXCLK,
53 GNLD_DS_SOCCLK,
54 GNLD_DS_LCLK,
55 GNLD_PPT,
56 GNLD_TDC,
57 GNLD_THERMAL,
58 GNLD_GFX_PER_CU_CG,
59 GNLD_RM,
60 GNLD_DS_DCEFCLK,
61 GNLD_ACDC,
62 GNLD_VR0HOT,
63 GNLD_VR1HOT,
64 GNLD_FW_CTF,
65 GNLD_LED_DISPLAY,
66 GNLD_FAN_CONTROL,
67 GNLD_DIDT,
68 GNLD_GFXOFF,
69 GNLD_CG,
70 GNLD_ACG,
71
72 GNLD_FEATURES_MAX
73};
74
75
76#define GNLD_DPM_MAX (GNLD_DPM_DCEFCLK + 1)
77
78#define SMC_DPM_FEATURES 0x30F
79
80struct smu_features {
81 bool supported;
82 bool enabled;
83 bool allowed;
84 uint32_t smu_feature_id;
85 uint64_t smu_feature_bitmap;
86};
87
88struct vega12_dpm_level {
89 bool enabled;
90 uint32_t value;
91 uint32_t param1;
92};
93
94#define VEGA12_MAX_DEEPSLEEP_DIVIDER_ID 5
95#define MAX_REGULAR_DPM_NUMBER 16
96#define MAX_PCIE_CONF 2
97#define VEGA12_MINIMUM_ENGINE_CLOCK 2500
98
99struct vega12_dpm_state {
100 uint32_t soft_min_level;
101 uint32_t soft_max_level;
102 uint32_t hard_min_level;
103 uint32_t hard_max_level;
104};
105
106struct vega12_single_dpm_table {
107 uint32_t count;
108 struct vega12_dpm_state dpm_state;
109 struct vega12_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER];
110};
111
112struct vega12_odn_dpm_control {
113 uint32_t count;
114 uint32_t entries[MAX_REGULAR_DPM_NUMBER];
115};
116
117struct vega12_pcie_table {
118 uint16_t count;
119 uint8_t pcie_gen[MAX_PCIE_CONF];
120 uint8_t pcie_lane[MAX_PCIE_CONF];
121 uint32_t lclk[MAX_PCIE_CONF];
122};
123
124struct vega12_dpm_table {
125 struct vega12_single_dpm_table soc_table;
126 struct vega12_single_dpm_table gfx_table;
127 struct vega12_single_dpm_table mem_table;
128 struct vega12_single_dpm_table eclk_table;
129 struct vega12_single_dpm_table vclk_table;
130 struct vega12_single_dpm_table dclk_table;
131 struct vega12_single_dpm_table dcef_table;
132 struct vega12_single_dpm_table pixel_table;
133 struct vega12_single_dpm_table display_table;
134 struct vega12_single_dpm_table phy_table;
135 struct vega12_pcie_table pcie_table;
136};
137
138#define VEGA12_MAX_LEAKAGE_COUNT 8
139struct vega12_leakage_voltage {
140 uint16_t count;
141 uint16_t leakage_id[VEGA12_MAX_LEAKAGE_COUNT];
142 uint16_t actual_voltage[VEGA12_MAX_LEAKAGE_COUNT];
143};
144
145struct vega12_display_timing {
146 uint32_t min_clock_in_sr;
147 uint32_t num_existing_displays;
148};
149
150struct vega12_dpmlevel_enable_mask {
151 uint32_t uvd_dpm_enable_mask;
152 uint32_t vce_dpm_enable_mask;
153 uint32_t samu_dpm_enable_mask;
154 uint32_t sclk_dpm_enable_mask;
155 uint32_t mclk_dpm_enable_mask;
156};
157
158struct vega12_vbios_boot_state {
159 bool bsoc_vddc_lock;
160 uint8_t uc_cooling_id;
161 uint16_t vddc;
162 uint16_t vddci;
163 uint16_t mvddc;
164 uint16_t vdd_gfx;
165 uint32_t gfx_clock;
166 uint32_t mem_clock;
167 uint32_t soc_clock;
168 uint32_t dcef_clock;
169 uint32_t eclock;
170 uint32_t dclock;
171 uint32_t vclock;
172};
173
174#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
175#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
176#define DPMTABLE_UPDATE_SCLK 0x00000004
177#define DPMTABLE_UPDATE_MCLK 0x00000008
178#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
179
180struct vega12_smc_state_table {
181 uint32_t soc_boot_level;
182 uint32_t gfx_boot_level;
183 uint32_t dcef_boot_level;
184 uint32_t mem_boot_level;
185 uint32_t uvd_boot_level;
186 uint32_t vce_boot_level;
187 uint32_t gfx_max_level;
188 uint32_t mem_max_level;
189 uint8_t vr_hot_gpio;
190 uint8_t ac_dc_gpio;
191 uint8_t therm_out_gpio;
192 uint8_t therm_out_polarity;
193 uint8_t therm_out_mode;
194 PPTable_t pp_table;
195 Watermarks_t water_marks_table;
196 AvfsDebugTable_t avfs_debug_table;
197 AvfsFuseOverride_t avfs_fuse_override_table;
198 SmuMetrics_t smu_metrics;
199 DriverSmuConfig_t driver_smu_config;
200 DpmActivityMonitorCoeffInt_t dpm_activity_monitor_coeffint;
201 OverDriveTable_t overdrive_table;
202};
203
204struct vega12_mclk_latency_entries {
205 uint32_t frequency;
206 uint32_t latency;
207};
208
209struct vega12_mclk_latency_table {
210 uint32_t count;
211 struct vega12_mclk_latency_entries entries[MAX_REGULAR_DPM_NUMBER];
212};
213
214struct vega12_registry_data {
215 uint64_t disallowed_features;
216 uint8_t ac_dc_switch_gpio_support;
217 uint8_t acg_loop_support;
218 uint8_t clock_stretcher_support;
219 uint8_t db_ramping_support;
220 uint8_t didt_mode;
221 uint8_t didt_support;
222 uint8_t edc_didt_support;
223 uint8_t force_dpm_high;
224 uint8_t fuzzy_fan_control_support;
225 uint8_t mclk_dpm_key_disabled;
226 uint8_t od_state_in_dc_support;
227 uint8_t pcie_lane_override;
228 uint8_t pcie_speed_override;
229 uint32_t pcie_clock_override;
230 uint8_t pcie_dpm_key_disabled;
231 uint8_t dcefclk_dpm_key_disabled;
232 uint8_t prefetcher_dpm_key_disabled;
233 uint8_t quick_transition_support;
234 uint8_t regulator_hot_gpio_support;
235 uint8_t master_deep_sleep_support;
236 uint8_t gfx_clk_deep_sleep_support;
237 uint8_t sclk_deep_sleep_support;
238 uint8_t lclk_deep_sleep_support;
239 uint8_t dce_fclk_deep_sleep_support;
240 uint8_t sclk_dpm_key_disabled;
241 uint8_t sclk_throttle_low_notification;
242 uint8_t skip_baco_hardware;
243 uint8_t socclk_dpm_key_disabled;
244 uint8_t sq_ramping_support;
245 uint8_t tcp_ramping_support;
246 uint8_t td_ramping_support;
247 uint8_t dbr_ramping_support;
248 uint8_t gc_didt_support;
249 uint8_t psm_didt_support;
250 uint8_t thermal_support;
251 uint8_t fw_ctf_enabled;
252 uint8_t led_dpm_enabled;
253 uint8_t fan_control_support;
254 uint8_t ulv_support;
255 uint8_t odn_feature_enable;
256 uint8_t disable_water_mark;
257 uint8_t disable_workload_policy;
258 uint32_t force_workload_policy_mask;
259 uint8_t disable_3d_fs_detection;
260 uint8_t disable_pp_tuning;
261 uint8_t disable_xlpp_tuning;
262 uint32_t perf_ui_tuning_profile_turbo;
263 uint32_t perf_ui_tuning_profile_powerSave;
264 uint32_t perf_ui_tuning_profile_xl;
265 uint16_t zrpm_stop_temp;
266 uint16_t zrpm_start_temp;
267 uint32_t stable_pstate_sclk_dpm_percentage;
268 uint8_t fps_support;
269 uint8_t vr0hot;
270 uint8_t vr1hot;
271 uint8_t disable_auto_wattman;
272 uint32_t auto_wattman_debug;
273 uint32_t auto_wattman_sample_period;
274 uint8_t auto_wattman_threshold;
275 uint8_t log_avfs_param;
276 uint8_t enable_enginess;
277 uint8_t custom_fan_support;
278 uint8_t disable_pcc_limit_control;
279};
280
281struct vega12_odn_clock_voltage_dependency_table {
282 uint32_t count;
283 struct phm_ppt_v1_clock_voltage_dependency_record
284 entries[MAX_REGULAR_DPM_NUMBER];
285};
286
287struct vega12_odn_dpm_table {
288 struct vega12_odn_dpm_control control_gfxclk_state;
289 struct vega12_odn_dpm_control control_memclk_state;
290 struct phm_odn_clock_levels odn_core_clock_dpm_levels;
291 struct phm_odn_clock_levels odn_memory_clock_dpm_levels;
292 struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_sclk;
293 struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_mclk;
294 struct vega12_odn_clock_voltage_dependency_table vdd_dependency_on_socclk;
295 uint32_t odn_mclk_min_limit;
296};
297
298struct vega12_odn_fan_table {
299 uint32_t target_fan_speed;
300 uint32_t target_temperature;
301 uint32_t min_performance_clock;
302 uint32_t min_fan_limit;
303 bool force_fan_pwm;
304};
305
306struct vega12_clock_range {
307 uint32_t ACMax;
308 uint32_t ACMin;
309 uint32_t DCMax;
310};
311
312struct vega12_hwmgr {
313 struct vega12_dpm_table dpm_table;
314 struct vega12_dpm_table golden_dpm_table;
315 struct vega12_registry_data registry_data;
316 struct vega12_vbios_boot_state vbios_boot_state;
317 struct vega12_mclk_latency_table mclk_latency_table;
318
319 struct vega12_leakage_voltage vddc_leakage;
320
321 uint32_t vddc_control;
322 struct pp_atomfwctrl_voltage_table vddc_voltage_table;
323 uint32_t mvdd_control;
324 struct pp_atomfwctrl_voltage_table mvdd_voltage_table;
325 uint32_t vddci_control;
326 struct pp_atomfwctrl_voltage_table vddci_voltage_table;
327
328 uint32_t active_auto_throttle_sources;
329 uint32_t water_marks_bitmap;
330
331 struct vega12_odn_dpm_table odn_dpm_table;
332 struct vega12_odn_fan_table odn_fan_table;
333
334 /* ---- General data ---- */
335 uint8_t need_update_dpm_table;
336
337 bool cac_enabled;
338 bool battery_state;
339 bool is_tlu_enabled;
340 bool avfs_exist;
341
342 uint32_t low_sclk_interrupt_threshold;
343
344 uint32_t total_active_cus;
345
346 struct vega12_display_timing display_timing;
347
348 /* ---- Vega12 Dyn Register Settings ---- */
349
350 uint32_t debug_settings;
351 uint32_t lowest_uclk_reserved_for_ulv;
352 uint32_t gfxclk_average_alpha;
353 uint32_t socclk_average_alpha;
354 uint32_t uclk_average_alpha;
355 uint32_t gfx_activity_average_alpha;
356 uint32_t display_voltage_mode;
357 uint32_t dcef_clk_quad_eqn_a;
358 uint32_t dcef_clk_quad_eqn_b;
359 uint32_t dcef_clk_quad_eqn_c;
360 uint32_t disp_clk_quad_eqn_a;
361 uint32_t disp_clk_quad_eqn_b;
362 uint32_t disp_clk_quad_eqn_c;
363 uint32_t pixel_clk_quad_eqn_a;
364 uint32_t pixel_clk_quad_eqn_b;
365 uint32_t pixel_clk_quad_eqn_c;
366 uint32_t phy_clk_quad_eqn_a;
367 uint32_t phy_clk_quad_eqn_b;
368 uint32_t phy_clk_quad_eqn_c;
369
370 /* ---- Thermal Temperature Setting ---- */
371 struct vega12_dpmlevel_enable_mask dpm_level_enable_mask;
372
373 /* ---- Power Gating States ---- */
374 bool uvd_power_gated;
375 bool vce_power_gated;
376 bool samu_power_gated;
377 bool need_long_memory_training;
378
379 /* Internal settings to apply the application power optimization parameters */
380 bool apply_optimized_settings;
381 uint32_t disable_dpm_mask;
382
383 /* ---- Overdrive next setting ---- */
384 uint32_t apply_overdrive_next_settings_mask;
385
386 /* ---- Workload Mask ---- */
387 uint32_t workload_mask;
388
389 /* ---- SMU9 ---- */
390 uint32_t smu_version;
391 struct smu_features smu_features[GNLD_FEATURES_MAX];
392 struct vega12_smc_state_table smc_state_table;
393
394 struct vega12_clock_range clk_range[PPCLK_COUNT];
395
396 /* ---- Gfxoff ---- */
397 bool gfxoff_controlled_by_driver;
398
399 unsigned long metrics_time;
400 SmuMetrics_t metrics_table;
401 struct gpu_metrics_v1_0 gpu_metrics_table;
402};
403
404#define VEGA12_DPM2_NEAR_TDP_DEC 10
405#define VEGA12_DPM2_ABOVE_SAFE_INC 5
406#define VEGA12_DPM2_BELOW_SAFE_INC 20
407
408#define VEGA12_DPM2_LTA_WINDOW_SIZE 7
409
410#define VEGA12_DPM2_LTS_TRUNCATE 0
411
412#define VEGA12_DPM2_TDP_SAFE_LIMIT_PERCENT 80
413
414#define VEGA12_DPM2_MAXPS_PERCENT_M 90
415#define VEGA12_DPM2_MAXPS_PERCENT_H 90
416
417#define VEGA12_DPM2_PWREFFICIENCYRATIO_MARGIN 50
418
419#define VEGA12_DPM2_SQ_RAMP_MAX_POWER 0x3FFF
420#define VEGA12_DPM2_SQ_RAMP_MIN_POWER 0x12
421#define VEGA12_DPM2_SQ_RAMP_MAX_POWER_DELTA 0x15
422#define VEGA12_DPM2_SQ_RAMP_SHORT_TERM_INTERVAL_SIZE 0x1E
423#define VEGA12_DPM2_SQ_RAMP_LONG_TERM_INTERVAL_RATIO 0xF
424
425#define VEGA12_VOLTAGE_CONTROL_NONE 0x0
426#define VEGA12_VOLTAGE_CONTROL_BY_GPIO 0x1
427#define VEGA12_VOLTAGE_CONTROL_BY_SVID2 0x2
428#define VEGA12_VOLTAGE_CONTROL_MERGED 0x3
429/* To convert to Q8.8 format for firmware */
430#define VEGA12_Q88_FORMAT_CONVERSION_UNIT 256
431
432#define VEGA12_UNUSED_GPIO_PIN 0x7F
433
434#define VEGA12_THERM_OUT_MODE_DISABLE 0x0
435#define VEGA12_THERM_OUT_MODE_THERM_ONLY 0x1
436#define VEGA12_THERM_OUT_MODE_THERM_VRHOT 0x2
437
438#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
439#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
440
441#define PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
442#define PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
443#define PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
444#define PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT 25 /* 10% * 255 = 25 */
445#define PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT 0xffffffff
446#define PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT 0xffffffff
447#define PPREGKEY_VEGA12QUADRATICEQUATION_DFLT 0xffffffff
448
449#define VEGA12_UMD_PSTATE_GFXCLK_LEVEL 0x3
450#define VEGA12_UMD_PSTATE_SOCCLK_LEVEL 0x3
451#define VEGA12_UMD_PSTATE_MCLK_LEVEL 0x2
452#define VEGA12_UMD_PSTATE_UVDCLK_LEVEL 0x3
453#define VEGA12_UMD_PSTATE_VCEMCLK_LEVEL 0x3
454
455int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
456
457#endif /* _VEGA12_HWMGR_H_ */