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1/*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef _DMUB_DCN35_H_
27#define _DMUB_DCN35_H_
28
29#include "dmub_dcn31.h"
30
31struct dmub_srv;
32
33/* DCN35 register definitions. */
34
35#define DMUB_DCN35_REGS() \
36 DMUB_SR(DMCUB_CNTL) \
37 DMUB_SR(DMCUB_CNTL2) \
38 DMUB_SR(DMCUB_SEC_CNTL) \
39 DMUB_SR(DMCUB_INBOX0_SIZE) \
40 DMUB_SR(DMCUB_INBOX0_RPTR) \
41 DMUB_SR(DMCUB_INBOX0_WPTR) \
42 DMUB_SR(DMCUB_INBOX1_BASE_ADDRESS) \
43 DMUB_SR(DMCUB_INBOX1_SIZE) \
44 DMUB_SR(DMCUB_INBOX1_RPTR) \
45 DMUB_SR(DMCUB_INBOX1_WPTR) \
46 DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \
47 DMUB_SR(DMCUB_OUTBOX0_SIZE) \
48 DMUB_SR(DMCUB_OUTBOX0_RPTR) \
49 DMUB_SR(DMCUB_OUTBOX0_WPTR) \
50 DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \
51 DMUB_SR(DMCUB_OUTBOX1_SIZE) \
52 DMUB_SR(DMCUB_OUTBOX1_RPTR) \
53 DMUB_SR(DMCUB_OUTBOX1_WPTR) \
54 DMUB_SR(DMCUB_REGION3_CW0_OFFSET) \
55 DMUB_SR(DMCUB_REGION3_CW1_OFFSET) \
56 DMUB_SR(DMCUB_REGION3_CW2_OFFSET) \
57 DMUB_SR(DMCUB_REGION3_CW3_OFFSET) \
58 DMUB_SR(DMCUB_REGION3_CW4_OFFSET) \
59 DMUB_SR(DMCUB_REGION3_CW5_OFFSET) \
60 DMUB_SR(DMCUB_REGION3_CW6_OFFSET) \
61 DMUB_SR(DMCUB_REGION3_CW7_OFFSET) \
62 DMUB_SR(DMCUB_REGION3_CW0_OFFSET_HIGH) \
63 DMUB_SR(DMCUB_REGION3_CW1_OFFSET_HIGH) \
64 DMUB_SR(DMCUB_REGION3_CW2_OFFSET_HIGH) \
65 DMUB_SR(DMCUB_REGION3_CW3_OFFSET_HIGH) \
66 DMUB_SR(DMCUB_REGION3_CW4_OFFSET_HIGH) \
67 DMUB_SR(DMCUB_REGION3_CW5_OFFSET_HIGH) \
68 DMUB_SR(DMCUB_REGION3_CW6_OFFSET_HIGH) \
69 DMUB_SR(DMCUB_REGION3_CW7_OFFSET_HIGH) \
70 DMUB_SR(DMCUB_REGION3_CW0_BASE_ADDRESS) \
71 DMUB_SR(DMCUB_REGION3_CW1_BASE_ADDRESS) \
72 DMUB_SR(DMCUB_REGION3_CW2_BASE_ADDRESS) \
73 DMUB_SR(DMCUB_REGION3_CW3_BASE_ADDRESS) \
74 DMUB_SR(DMCUB_REGION3_CW4_BASE_ADDRESS) \
75 DMUB_SR(DMCUB_REGION3_CW5_BASE_ADDRESS) \
76 DMUB_SR(DMCUB_REGION3_CW6_BASE_ADDRESS) \
77 DMUB_SR(DMCUB_REGION3_CW7_BASE_ADDRESS) \
78 DMUB_SR(DMCUB_REGION3_CW0_TOP_ADDRESS) \
79 DMUB_SR(DMCUB_REGION3_CW1_TOP_ADDRESS) \
80 DMUB_SR(DMCUB_REGION3_CW2_TOP_ADDRESS) \
81 DMUB_SR(DMCUB_REGION3_CW3_TOP_ADDRESS) \
82 DMUB_SR(DMCUB_REGION3_CW4_TOP_ADDRESS) \
83 DMUB_SR(DMCUB_REGION3_CW5_TOP_ADDRESS) \
84 DMUB_SR(DMCUB_REGION3_CW6_TOP_ADDRESS) \
85 DMUB_SR(DMCUB_REGION3_CW7_TOP_ADDRESS) \
86 DMUB_SR(DMCUB_REGION4_OFFSET) \
87 DMUB_SR(DMCUB_REGION4_OFFSET_HIGH) \
88 DMUB_SR(DMCUB_REGION4_TOP_ADDRESS) \
89 DMUB_SR(DMCUB_REGION5_OFFSET) \
90 DMUB_SR(DMCUB_REGION5_OFFSET_HIGH) \
91 DMUB_SR(DMCUB_REGION5_TOP_ADDRESS) \
92 DMUB_SR(DMCUB_REGION6_OFFSET) \
93 DMUB_SR(DMCUB_REGION6_OFFSET_HIGH) \
94 DMUB_SR(DMCUB_REGION6_TOP_ADDRESS) \
95 DMUB_SR(DMCUB_SCRATCH0) \
96 DMUB_SR(DMCUB_SCRATCH1) \
97 DMUB_SR(DMCUB_SCRATCH2) \
98 DMUB_SR(DMCUB_SCRATCH3) \
99 DMUB_SR(DMCUB_SCRATCH4) \
100 DMUB_SR(DMCUB_SCRATCH5) \
101 DMUB_SR(DMCUB_SCRATCH6) \
102 DMUB_SR(DMCUB_SCRATCH7) \
103 DMUB_SR(DMCUB_SCRATCH8) \
104 DMUB_SR(DMCUB_SCRATCH9) \
105 DMUB_SR(DMCUB_SCRATCH10) \
106 DMUB_SR(DMCUB_SCRATCH11) \
107 DMUB_SR(DMCUB_SCRATCH12) \
108 DMUB_SR(DMCUB_SCRATCH13) \
109 DMUB_SR(DMCUB_SCRATCH14) \
110 DMUB_SR(DMCUB_SCRATCH15) \
111 DMUB_SR(DMCUB_SCRATCH16) \
112 DMUB_SR(DMCUB_SCRATCH17) \
113 DMUB_SR(DMCUB_SCRATCH18) \
114 DMUB_SR(DMCUB_SCRATCH19) \
115 DMUB_SR(DMCUB_SCRATCH20) \
116 DMUB_SR(DMCUB_SCRATCH21) \
117 DMUB_SR(DMCUB_GPINT_DATAIN0) \
118 DMUB_SR(DMCUB_GPINT_DATAIN1) \
119 DMUB_SR(DMCUB_GPINT_DATAOUT) \
120 DMUB_SR(CC_DC_PIPE_DIS) \
121 DMUB_SR(MMHUBBUB_SOFT_RESET) \
122 DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
123 DMUB_SR(DCN_VM_FB_OFFSET) \
124 DMUB_SR(DMCUB_TIMER_CURRENT) \
125 DMUB_SR(DMCUB_INST_FETCH_FAULT_ADDR) \
126 DMUB_SR(DMCUB_UNDEFINED_ADDRESS_FAULT_ADDR) \
127 DMUB_SR(DMCUB_DATA_WRITE_FAULT_ADDR) \
128 DMUB_SR(DMCUB_REGION3_TMR_AXI_SPACE) \
129 DMUB_SR(DMCUB_INTERRUPT_ENABLE) \
130 DMUB_SR(DMCUB_INTERRUPT_ACK) \
131 DMUB_SR(DMU_CLK_CNTL)
132
133#define DMUB_DCN35_FIELDS() \
134 DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
135 DMUB_SF(DMCUB_CNTL, DMCUB_TRACEPORT_EN) \
136 DMUB_SF(DMCUB_CNTL2, DMCUB_SOFT_RESET) \
137 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET) \
138 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_MEM_UNIT_ID) \
139 DMUB_SF(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS) \
140 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_TOP_ADDRESS) \
141 DMUB_SF(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE) \
142 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_TOP_ADDRESS) \
143 DMUB_SF(DMCUB_REGION3_CW1_TOP_ADDRESS, DMCUB_REGION3_CW1_ENABLE) \
144 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_TOP_ADDRESS) \
145 DMUB_SF(DMCUB_REGION3_CW2_TOP_ADDRESS, DMCUB_REGION3_CW2_ENABLE) \
146 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_TOP_ADDRESS) \
147 DMUB_SF(DMCUB_REGION3_CW3_TOP_ADDRESS, DMCUB_REGION3_CW3_ENABLE) \
148 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_TOP_ADDRESS) \
149 DMUB_SF(DMCUB_REGION3_CW4_TOP_ADDRESS, DMCUB_REGION3_CW4_ENABLE) \
150 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_TOP_ADDRESS) \
151 DMUB_SF(DMCUB_REGION3_CW5_TOP_ADDRESS, DMCUB_REGION3_CW5_ENABLE) \
152 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_TOP_ADDRESS) \
153 DMUB_SF(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE) \
154 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_TOP_ADDRESS) \
155 DMUB_SF(DMCUB_REGION3_CW7_TOP_ADDRESS, DMCUB_REGION3_CW7_ENABLE) \
156 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
157 DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
158 DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_TOP_ADDRESS) \
159 DMUB_SF(DMCUB_REGION5_TOP_ADDRESS, DMCUB_REGION5_ENABLE) \
160 DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_TOP_ADDRESS) \
161 DMUB_SF(DMCUB_REGION6_TOP_ADDRESS, DMCUB_REGION6_ENABLE) \
162 DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
163 DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
164 DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
165 DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \
166 DMUB_SF(DMCUB_INBOX0_WPTR, DMCUB_INBOX0_WPTR) \
167 DMUB_SF(DMCUB_REGION3_TMR_AXI_SPACE, DMCUB_REGION3_TMR_AXI_SPACE) \
168 DMUB_SF(DMCUB_INTERRUPT_ENABLE, DMCUB_GPINT_IH_INT_EN) \
169 DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_GPINT_IH_INT_ACK) \
170 DMUB_SF(DMCUB_CNTL, DMCUB_PWAIT_MODE_STATUS) \
171 DMUB_SF(DMU_CLK_CNTL, LONO_DISPCLK_GATE_DISABLE) \
172 DMUB_SF(DMU_CLK_CNTL, LONO_SOCCLK_GATE_DISABLE) \
173 DMUB_SF(DMU_CLK_CNTL, LONO_DMCUBCLK_GATE_DISABLE)
174
175struct dmub_srv_dcn35_reg_offset {
176#define DMUB_SR(reg) uint32_t reg;
177 DMUB_DCN35_REGS()
178 DMCUB_INTERNAL_REGS()
179#undef DMUB_SR
180};
181
182struct dmub_srv_dcn35_reg_shift {
183#define DMUB_SF(reg, field) uint8_t reg##__##field;
184 DMUB_DCN35_FIELDS()
185#undef DMUB_SF
186};
187
188struct dmub_srv_dcn35_reg_mask {
189#define DMUB_SF(reg, field) uint32_t reg##__##field;
190 DMUB_DCN35_FIELDS()
191#undef DMUB_SF
192};
193
194struct dmub_srv_dcn35_regs {
195 struct dmub_srv_dcn35_reg_offset offset;
196 struct dmub_srv_dcn35_reg_mask mask;
197 struct dmub_srv_dcn35_reg_shift shift;
198};
199
200/* Hardware functions. */
201
202
203void dmub_dcn35_init(struct dmub_srv *dmub);
204
205void dmub_dcn35_reset(struct dmub_srv *dmub);
206
207void dmub_dcn35_reset_release(struct dmub_srv *dmub);
208
209void dmub_dcn35_backdoor_load(struct dmub_srv *dmub,
210 const struct dmub_window *cw0,
211 const struct dmub_window *cw1);
212
213void dmub_dcn35_backdoor_load_zfb_mode(struct dmub_srv *dmub,
214 const struct dmub_window *cw0,
215 const struct dmub_window *cw1);
216
217void dmub_dcn35_setup_windows(struct dmub_srv *dmub,
218 const struct dmub_window *cw2,
219 const struct dmub_window *cw3,
220 const struct dmub_window *cw4,
221 const struct dmub_window *cw5,
222 const struct dmub_window *cw6,
223 const struct dmub_window *region6);
224
225void dmub_dcn35_setup_mailbox(struct dmub_srv *dmub,
226 const struct dmub_region *inbox1);
227
228uint32_t dmub_dcn35_get_inbox1_wptr(struct dmub_srv *dmub);
229
230uint32_t dmub_dcn35_get_inbox1_rptr(struct dmub_srv *dmub);
231
232void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
233
234void dmub_dcn35_setup_out_mailbox(struct dmub_srv *dmub,
235 const struct dmub_region *outbox1);
236
237uint32_t dmub_dcn35_get_outbox1_wptr(struct dmub_srv *dmub);
238
239void dmub_dcn35_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
240
241bool dmub_dcn35_is_hw_init(struct dmub_srv *dmub);
242
243bool dmub_dcn35_is_supported(struct dmub_srv *dmub);
244
245void dmub_dcn35_set_gpint(struct dmub_srv *dmub,
246 union dmub_gpint_data_register reg);
247
248bool dmub_dcn35_is_gpint_acked(struct dmub_srv *dmub,
249 union dmub_gpint_data_register reg);
250
251uint32_t dmub_dcn35_get_gpint_response(struct dmub_srv *dmub);
252
253uint32_t dmub_dcn35_get_gpint_dataout(struct dmub_srv *dmub);
254
255void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmub_srv_hw_params *params);
256
257void dmub_dcn35_skip_dmub_panel_power_sequence(struct dmub_srv *dmub, bool skip);
258
259union dmub_fw_boot_status dmub_dcn35_get_fw_boot_status(struct dmub_srv *dmub);
260
261union dmub_fw_boot_options dmub_dcn35_get_fw_boot_option(struct dmub_srv *dmub);
262
263void dmub_dcn35_setup_outbox0(struct dmub_srv *dmub,
264 const struct dmub_region *outbox0);
265
266uint32_t dmub_dcn35_get_outbox0_wptr(struct dmub_srv *dmub);
267
268void dmub_dcn35_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset);
269
270uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub);
271
272void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data);
273
274void dmub_dcn35_configure_dmub_in_system_memory(struct dmub_srv *dmub);
275
276void dmub_dcn35_send_inbox0_cmd(struct dmub_srv *dmub, union dmub_inbox0_data_register data);
277
278void dmub_dcn35_clear_inbox0_ack_register(struct dmub_srv *dmub);
279
280uint32_t dmub_dcn35_read_inbox0_ack_register(struct dmub_srv *dmub);
281
282bool dmub_dcn35_should_detect(struct dmub_srv *dmub);
283
284bool dmub_dcn35_is_hw_powered_up(struct dmub_srv *dmub);
285
286void dmub_srv_dcn35_regs_init(struct dmub_srv *dmub, struct dc_context *ctx);
287
288#endif /* _DMUB_DCN35_H_ */