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1/* SPDX-License-Identifier: MIT */
2/*
3 * Copyright 2023 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27/**
28 * DOC: overview
29 *
30 * Output Pipe Timing Combiner (OPTC) includes two major functional blocks:
31 * Output Data Mapper (ODM) and Output Timing Generator (OTG).
32 *
33 * - ODM: It is Output Data Mapping block. It can combine input data from
34 * multiple OPP data pipes into one single data stream or split data from one
35 * OPP data pipe into multiple data streams or just bypass OPP data to DIO.
36 * - OTG: It is Output Timing Generator. It generates display timing signals to
37 * drive the display output.
38 */
39
40#ifndef __DC_OPTC_H__
41#define __DC_OPTC_H__
42
43#include "timing_generator.h"
44
45struct optc {
46 struct timing_generator base;
47
48 const struct dcn_optc_registers *tg_regs;
49 const struct dcn_optc_shift *tg_shift;
50 const struct dcn_optc_mask *tg_mask;
51
52 int opp_count;
53
54 uint32_t max_h_total;
55 uint32_t max_v_total;
56
57 uint32_t min_h_blank;
58
59 uint32_t min_h_sync_width;
60 uint32_t min_v_sync_width;
61 uint32_t min_v_blank;
62 uint32_t min_v_blank_interlace;
63
64 int vstartup_start;
65 int vupdate_offset;
66 int vupdate_width;
67 int vready_offset;
68 struct dc_crtc_timing orginal_patched_timing;
69 enum signal_type signal;
70};
71
72struct dcn_otg_state {
73 uint32_t v_blank_start;
74 uint32_t v_blank_end;
75 uint32_t v_sync_a_pol;
76 uint32_t v_total;
77 uint32_t v_total_max;
78 uint32_t v_total_min;
79 uint32_t v_total_min_sel;
80 uint32_t v_total_max_sel;
81 uint32_t v_sync_a_start;
82 uint32_t v_sync_a_end;
83 uint32_t h_blank_start;
84 uint32_t h_blank_end;
85 uint32_t h_sync_a_start;
86 uint32_t h_sync_a_end;
87 uint32_t h_sync_a_pol;
88 uint32_t h_total;
89 uint32_t underflow_occurred_status;
90 uint32_t otg_enabled;
91 uint32_t blank_enabled;
92 uint32_t vertical_interrupt1_en;
93 uint32_t vertical_interrupt1_line;
94 uint32_t vertical_interrupt2_en;
95 uint32_t vertical_interrupt2_line;
96};
97
98void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);
99
100bool optc1_get_hw_timing(struct timing_generator *tg, struct dc_crtc_timing *hw_crtc_timing);
101
102bool optc1_validate_timing(struct timing_generator *optc,
103 const struct dc_crtc_timing *timing);
104
105void optc1_program_timing(struct timing_generator *optc,
106 const struct dc_crtc_timing *dc_crtc_timing,
107 int vready_offset,
108 int vstartup_start,
109 int vupdate_offset,
110 int vupdate_width,
111 const enum signal_type signal,
112 bool use_vbios);
113
114void optc1_setup_vertical_interrupt0(struct timing_generator *optc,
115 uint32_t start_line,
116 uint32_t end_line);
117
118void optc1_setup_vertical_interrupt1(struct timing_generator *optc,
119 uint32_t start_line);
120
121void optc1_setup_vertical_interrupt2(struct timing_generator *optc,
122 uint32_t start_line);
123
124void optc1_program_global_sync(struct timing_generator *optc,
125 int vready_offset,
126 int vstartup_start,
127 int vupdate_offset,
128 int vupdate_width);
129
130bool optc1_disable_crtc(struct timing_generator *optc);
131
132bool optc1_is_counter_moving(struct timing_generator *optc);
133
134void optc1_get_position(struct timing_generator *optc,
135 struct crtc_position *position);
136
137uint32_t optc1_get_vblank_counter(struct timing_generator *optc);
138
139void optc1_get_crtc_scanoutpos(struct timing_generator *optc,
140 uint32_t *v_blank_start,
141 uint32_t *v_blank_end,
142 uint32_t *h_position,
143 uint32_t *v_position);
144
145void optc1_set_early_control(struct timing_generator *optc,
146 uint32_t early_cntl);
147
148void optc1_wait_for_state(struct timing_generator *optc,
149 enum crtc_state state);
150
151void optc1_set_blank(struct timing_generator *optc,
152 bool enable_blanking);
153
154bool optc1_is_blanked(struct timing_generator *optc);
155
156void optc1_program_blank_color(struct timing_generator *optc,
157 const struct tg_color *black_color);
158
159bool optc1_did_triggered_reset_occur(struct timing_generator *optc);
160
161void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst);
162
163void optc1_disable_reset_trigger(struct timing_generator *optc);
164
165void optc1_lock(struct timing_generator *optc);
166
167void optc1_unlock(struct timing_generator *optc);
168
169void optc1_enable_optc_clock(struct timing_generator *optc, bool enable);
170
171void optc1_set_drr(struct timing_generator *optc,
172 const struct drr_params *params);
173
174void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max);
175
176void optc1_set_static_screen_control(struct timing_generator *optc,
177 uint32_t event_triggers,
178 uint32_t num_frames);
179
180void optc1_program_stereo(struct timing_generator *optc,
181 const struct dc_crtc_timing *timing,
182 struct crtc_stereo_flags *flags);
183
184bool optc1_is_stereo_left_eye(struct timing_generator *optc);
185
186void optc1_clear_optc_underflow(struct timing_generator *optc);
187
188void optc1_tg_init(struct timing_generator *optc);
189
190bool optc1_is_tg_enabled(struct timing_generator *optc);
191
192bool optc1_is_optc_underflow_occurred(struct timing_generator *optc);
193
194void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable);
195
196void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable);
197
198bool optc1_get_otg_active_size(struct timing_generator *optc,
199 uint32_t *otg_active_width,
200 uint32_t *otg_active_height);
201
202void optc1_enable_crtc_reset(struct timing_generator *optc,
203 int source_tg_inst,
204 struct crtc_trigger_info *crtc_tp);
205
206bool optc1_configure_crc(struct timing_generator *optc, const struct crc_params *params);
207
208bool optc1_get_crc(struct timing_generator *optc,
209 uint32_t *r_cr,
210 uint32_t *g_y,
211 uint32_t *b_cb);
212
213bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing);
214
215void optc1_set_vtg_params(struct timing_generator *optc,
216 const struct dc_crtc_timing *dc_crtc_timing,
217 bool program_fp2);
218
219#endif