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1/* Copyright 2012-15 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25#ifndef __DC_MPCC_DCN10_H__
26#define __DC_MPCC_DCN10_H__
27
28#include "mpc.h"
29
30#define TO_DCN10_MPC(mpc_base) \
31 container_of(mpc_base, struct dcn10_mpc, base)
32
33#define MPC_COMMON_REG_LIST_DCN1_0(inst) \
34 SRII(MPCC_TOP_SEL, MPCC, inst),\
35 SRII(MPCC_BOT_SEL, MPCC, inst),\
36 SRII(MPCC_CONTROL, MPCC, inst),\
37 SRII(MPCC_STATUS, MPCC, inst),\
38 SRII(MPCC_OPP_ID, MPCC, inst),\
39 SRII(MPCC_BG_G_Y, MPCC, inst),\
40 SRII(MPCC_BG_R_CR, MPCC, inst),\
41 SRII(MPCC_BG_B_CB, MPCC, inst),\
42 SRII(MPCC_SM_CONTROL, MPCC, inst),\
43 SRII(MPCC_UPDATE_LOCK_SEL, MPCC, inst)
44
45#define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \
46 SRII(MUX, MPC_OUT, inst),\
47 VUPDATE_SRII(CUR, VUPDATE_LOCK_SET, inst)
48
49#define MPC_COMMON_REG_VARIABLE_LIST \
50 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
51 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
52 uint32_t MPCC_CONTROL[MAX_MPCC]; \
53 uint32_t MPCC_STATUS[MAX_MPCC]; \
54 uint32_t MPCC_OPP_ID[MAX_MPCC]; \
55 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
56 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
57 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
58 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
59 uint32_t MUX[MAX_OPP]; \
60 uint32_t MPCC_UPDATE_LOCK_SEL[MAX_MPCC]; \
61 uint32_t CUR[MAX_OPP];
62
63#define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\
64 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\
65 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\
66 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\
67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\
68 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\
69 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\
70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\
71 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\
72 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\
73 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\
74 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\
75 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\
76 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\
77 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\
78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\
79 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\
80 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\
81 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\
82 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\
83 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\
84 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh),\
85 SF(MPCC0_MPCC_UPDATE_LOCK_SEL, MPCC_UPDATE_LOCK_SEL, mask_sh)
86
87#define MPC_REG_FIELD_LIST(type) \
88 type MPCC_TOP_SEL;\
89 type MPCC_BOT_SEL;\
90 type MPCC_MODE;\
91 type MPCC_ALPHA_BLND_MODE;\
92 type MPCC_ALPHA_MULTIPLIED_MODE;\
93 type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\
94 type MPCC_GLOBAL_ALPHA;\
95 type MPCC_GLOBAL_GAIN;\
96 type MPCC_IDLE;\
97 type MPCC_BUSY;\
98 type MPCC_OPP_ID;\
99 type MPCC_BG_G_Y;\
100 type MPCC_BG_R_CR;\
101 type MPCC_BG_B_CB;\
102 type MPCC_SM_EN;\
103 type MPCC_SM_MODE;\
104 type MPCC_SM_FRAME_ALT;\
105 type MPCC_SM_FIELD_ALT;\
106 type MPCC_SM_FORCE_NEXT_FRAME_POL;\
107 type MPCC_SM_FORCE_NEXT_TOP_POL;\
108 type MPC_OUT_MUX;\
109 type MPCC_UPDATE_LOCK_SEL;\
110 type CUR_VUPDATE_LOCK_SET;
111
112struct dcn_mpc_registers {
113 MPC_COMMON_REG_VARIABLE_LIST
114};
115
116struct dcn_mpc_shift {
117 MPC_REG_FIELD_LIST(uint8_t)
118};
119
120struct dcn_mpc_mask {
121 MPC_REG_FIELD_LIST(uint32_t)
122};
123
124struct dcn10_mpc {
125 struct mpc base;
126
127 int mpcc_in_use_mask;
128 int num_mpcc;
129 const struct dcn_mpc_registers *mpc_regs;
130 const struct dcn_mpc_shift *mpc_shift;
131 const struct dcn_mpc_mask *mpc_mask;
132};
133
134void dcn10_mpc_construct(struct dcn10_mpc *mpcc10,
135 struct dc_context *ctx,
136 const struct dcn_mpc_registers *mpc_regs,
137 const struct dcn_mpc_shift *mpc_shift,
138 const struct dcn_mpc_mask *mpc_mask,
139 int num_mpcc);
140
141struct mpcc *mpc1_insert_plane(
142 struct mpc *mpc,
143 struct mpc_tree *tree,
144 struct mpcc_blnd_cfg *blnd_cfg,
145 struct mpcc_sm_cfg *sm_cfg,
146 struct mpcc *insert_above_mpcc,
147 int dpp_id,
148 int mpcc_id);
149
150void mpc1_remove_mpcc(
151 struct mpc *mpc,
152 struct mpc_tree *tree,
153 struct mpcc *mpcc);
154
155void mpc1_mpc_init(
156 struct mpc *mpc);
157
158void mpc1_mpc_init_single_inst(
159 struct mpc *mpc,
160 unsigned int mpcc_id);
161
162void mpc1_assert_idle_mpcc(
163 struct mpc *mpc,
164 int id);
165
166void mpc1_set_bg_color(
167 struct mpc *mpc,
168 struct tg_color *bg_color,
169 int id);
170
171void mpc1_update_stereo_mix(
172 struct mpc *mpc,
173 struct mpcc_sm_cfg *sm_cfg,
174 int mpcc_id);
175
176bool mpc1_is_mpcc_idle(
177 struct mpc *mpc,
178 int mpcc_id);
179
180void mpc1_assert_mpcc_idle_before_connect(
181 struct mpc *mpc,
182 int mpcc_id);
183
184void mpc1_init_mpcc_list_from_hw(
185 struct mpc *mpc,
186 struct mpc_tree *tree);
187
188struct mpcc *mpc1_get_mpcc(
189 struct mpc *mpc,
190 int mpcc_id);
191
192struct mpcc *mpc1_get_mpcc_for_dpp(
193 struct mpc_tree *tree,
194 int dpp_id);
195
196void mpc1_read_mpcc_state(
197 struct mpc *mpc,
198 int mpcc_inst,
199 struct mpcc_state *s);
200
201void mpc1_cursor_lock(struct mpc *mpc, int opp_id, bool lock);
202
203unsigned int mpc1_get_mpc_out_mux(struct mpc *mpc, int opp_id);
204#endif