1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23#ifndef __UMC_V12_0_H__
 24#define __UMC_V12_0_H__
 25
 26#include "soc15_common.h"
 27#include "amdgpu.h"
 28
 29#define UMC_V12_0_NODE_DIST		0x40000000
 30#define UMC_V12_0_INST_DIST		0x40000
 31
 32/* UMC register per channel offset */
 33#define UMC_V12_0_PER_CHANNEL_OFFSET	0x400
 34
 35/* UMC cross node offset */
 36#define UMC_V12_0_CROSS_NODE_OFFSET		0x100000000
 37
 38/* OdEccErrCnt max value */
 39#define UMC_V12_0_CE_CNT_MAX		0xffff
 40/* umc ce interrupt threshold */
 41#define UMC_V12_0_CE_INT_THRESHOLD	0xffff
 42/* umc ce count initial value */
 43#define UMC_V12_0_CE_CNT_INIT	(UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
 44
 45/* number of umc channel instance with memory map register access */
 46#define UMC_V12_0_CHANNEL_INSTANCE_NUM		8
 47/* number of umc instance with memory map register access */
 48#define UMC_V12_0_UMC_INSTANCE_NUM		4
 49
 50/* Total channel instances for all available umc nodes */
 51#define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \
 52	(UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
 53
 54/* one piece of normalized address is mapped to 8 pieces of physical address */
 55#define UMC_V12_0_NA_MAP_PA_NUM        8
 56/* R13 bit shift should be considered, double the number */
 57#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)
 58/* bank bits in MCA error address */
 59#define UMC_V12_0_MCA_B0_BIT 6
 60#define UMC_V12_0_MCA_B1_BIT 7
 61#define UMC_V12_0_MCA_B2_BIT 8
 62#define UMC_V12_0_MCA_B3_BIT 9
 63/* column bits in SOC physical address */
 64#define UMC_V12_0_PA_C2_BIT 15
 65#define UMC_V12_0_PA_C4_BIT 21
 66/* row bits in SOC physical address */
 67#define UMC_V12_0_PA_R13_BIT 35
 68/* channel index bits in SOC physical address */
 69#define UMC_V12_0_PA_CH4_BIT 12
 70#define UMC_V12_0_PA_CH5_BIT 13
 71#define UMC_V12_0_PA_CH6_BIT 14
 72
 73/* bank hash settings */
 74#define UMC_V12_0_XOR_EN0 1
 75#define UMC_V12_0_XOR_EN1 1
 76#define UMC_V12_0_XOR_EN2 1
 77#define UMC_V12_0_XOR_EN3 1
 78#define UMC_V12_0_COL_XOR0 0x0
 79#define UMC_V12_0_COL_XOR1 0x0
 80#define UMC_V12_0_COL_XOR2 0x800
 81#define UMC_V12_0_COL_XOR3 0x1000
 82#define UMC_V12_0_ROW_XOR0 0x11111
 83#define UMC_V12_0_ROW_XOR1 0x22222
 84#define UMC_V12_0_ROW_XOR2 0x4444
 85#define UMC_V12_0_ROW_XOR3 0x8888
 86
 87/* channel hash settings */
 88#define UMC_V12_0_HASH_4K 0
 89#define UMC_V12_0_HASH_64K 1
 90#define UMC_V12_0_HASH_2M 1
 91#define UMC_V12_0_HASH_1G 1
 92#define UMC_V12_0_HASH_1T 1
 93
 94/* XOR some bits of PA into CH4~CH6 bits (bits 12~14 of PA),
 95 * hash bit is only effective when related setting is enabled
 96 */
 97#define UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) ((((channel_idx) >> 5) & 0x1) ^ \
 98				(((pa)  >> 20) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
 99				(((pa)  >> 27) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
100				(((pa)  >> 34) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
101				(((pa)  >> 41) & 0x1ULL & UMC_V12_0_HASH_1T))
102#define UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) ((((channel_idx) >> 6) & 0x1) ^ \
103				(((pa)  >> 21) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
104				(((pa)  >> 28) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
105				(((pa)  >> 35) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
106				(((pa)  >> 42) & 0x1ULL & UMC_V12_0_HASH_1T))
107#define UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) ((((channel_idx) >> 4) & 0x1) ^ \
108				(((pa)  >> 19) & 0x1ULL & UMC_V12_0_HASH_64K) ^ \
109				(((pa)  >> 26) & 0x1ULL & UMC_V12_0_HASH_2M) ^ \
110				(((pa)  >> 33) & 0x1ULL & UMC_V12_0_HASH_1G) ^ \
111				(((pa)  >> 40) & 0x1ULL & UMC_V12_0_HASH_1T) ^ \
112				(((pa)  >> 47) & 0x1ULL & UMC_V12_0_HASH_4K))
113#define UMC_V12_0_SET_CHANNEL_HASH(channel_idx, pa) do { \
114		(pa) &= ~(0x7ULL << UMC_V12_0_PA_CH4_BIT); \
115		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH4(channel_idx, pa) << UMC_V12_0_PA_CH4_BIT); \
116		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH5(channel_idx, pa) << UMC_V12_0_PA_CH5_BIT); \
117		(pa) |= (UMC_V12_0_CHANNEL_HASH_CH6(channel_idx, pa) << UMC_V12_0_PA_CH6_BIT); \
118	} while (0)
119
120#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \
121			(((_ipid_lo) >> 12) & 0xF))
122#define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7)
123
124bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
125bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
126bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
127
128typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status);
129
130extern const uint32_t
131	umc_v12_0_channel_idx_tbl[]
132			[UMC_V12_0_UMC_INSTANCE_NUM]
133			[UMC_V12_0_CHANNEL_INSTANCE_NUM];
134
135extern struct amdgpu_umc_ras umc_v12_0_ras;
136
137#endif