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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "hdp_v7_0.h"
26
27#include "hdp/hdp_7_0_0_offset.h"
28#include "hdp/hdp_7_0_0_sh_mask.h"
29#include <uapi/linux/kfd_ioctl.h>
30
31static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev,
32 struct amdgpu_ring *ring)
33{
34 if (!ring || !ring->funcs->emit_wreg)
35 WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
36 else
37 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
38}
39
40static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev,
41 bool enable)
42{
43 uint32_t hdp_clk_cntl, hdp_clk_cntl1;
44 uint32_t hdp_mem_pwr_cntl;
45
46 if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
47 AMD_CG_SUPPORT_HDP_DS |
48 AMD_CG_SUPPORT_HDP_SD)))
49 return;
50
51 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
52 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
53
54 /* Before doing clock/power mode switch,
55 * forced on IPH & RC clock */
56 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
57 RC_MEM_CLK_SOFT_OVERRIDE, 1);
58 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
59
60 /* disable clock and power gating before any changing */
61 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
62 ATOMIC_MEM_POWER_CTRL_EN, 0);
63 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
64 ATOMIC_MEM_POWER_LS_EN, 0);
65 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
66 ATOMIC_MEM_POWER_DS_EN, 0);
67 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
68 ATOMIC_MEM_POWER_SD_EN, 0);
69 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
70 RC_MEM_POWER_CTRL_EN, 0);
71 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
72 RC_MEM_POWER_LS_EN, 0);
73 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
74 RC_MEM_POWER_DS_EN, 0);
75 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
76 RC_MEM_POWER_SD_EN, 0);
77 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
78
79 /* Already disabled above. The actions below are for "enabled" only */
80 if (enable) {
81 /* only one clock gating mode (LS/DS/SD) can be enabled */
82 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
83 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
84 HDP_MEM_POWER_CTRL,
85 ATOMIC_MEM_POWER_SD_EN, 1);
86 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
87 HDP_MEM_POWER_CTRL,
88 RC_MEM_POWER_SD_EN, 1);
89 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
90 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
91 HDP_MEM_POWER_CTRL,
92 ATOMIC_MEM_POWER_LS_EN, 1);
93 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
94 HDP_MEM_POWER_CTRL,
95 RC_MEM_POWER_LS_EN, 1);
96 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
97 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
98 HDP_MEM_POWER_CTRL,
99 ATOMIC_MEM_POWER_DS_EN, 1);
100 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
101 HDP_MEM_POWER_CTRL,
102 RC_MEM_POWER_DS_EN, 1);
103 }
104
105 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
106 * be set for SRAM LS/DS/SD */
107 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
108 AMD_CG_SUPPORT_HDP_SD)) {
109 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
110 ATOMIC_MEM_POWER_CTRL_EN, 1);
111 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
112 RC_MEM_POWER_CTRL_EN, 1);
113 WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
114 }
115 }
116
117 /* disable IPH & RC clock override after clock/power mode changing */
118 hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
119 RC_MEM_CLK_SOFT_OVERRIDE, 0);
120 WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
121}
122
123static void hdp_v7_0_get_clockgating_state(struct amdgpu_device *adev,
124 u64 *flags)
125{
126 uint32_t tmp;
127
128 /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
129 tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
130 if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
131 *flags |= AMD_CG_SUPPORT_HDP_LS;
132 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_DS_EN_MASK)
133 *flags |= AMD_CG_SUPPORT_HDP_DS;
134 else if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_SD_EN_MASK)
135 *flags |= AMD_CG_SUPPORT_HDP_SD;
136}
137
138const struct amdgpu_hdp_funcs hdp_v7_0_funcs = {
139 .flush_hdp = hdp_v7_0_flush_hdp,
140 .update_clock_gating = hdp_v7_0_update_clock_gating,
141 .get_clock_gating_state = hdp_v7_0_get_clockgating_state,
142};