1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
 2/* Copyright(c) 2022 Intel Corporation */
 3#ifndef ADF_GEN4_PM_H
 4#define ADF_GEN4_PM_H
 5
 6#include <linux/bits.h>
 7
 8struct adf_accel_dev;
 9
10enum qat_pm_host_msg {
11	PM_NO_CHANGE = 0,
12	PM_SET_MIN,
13};
14
15/* Power management registers */
16#define ADF_GEN4_PM_HOST_MSG (0x50A01C)
17
18/* Power management */
19#define ADF_GEN4_PM_POLL_DELAY_US	20
20#define ADF_GEN4_PM_POLL_TIMEOUT_US	USEC_PER_SEC
21#define ADF_GEN4_PM_MSG_POLL_DELAY_US	(10 * USEC_PER_MSEC)
22#define ADF_GEN4_PM_STATUS		(0x50A00C)
23#define ADF_GEN4_PM_INTERRUPT		(0x50A028)
24
25/* Power management source in ERRSOU2 and ERRMSK2 */
26#define ADF_GEN4_PM_SOU			BIT(18)
27
28#define ADF_GEN4_PM_IDLE_INT_EN		BIT(18)
29#define ADF_GEN4_PM_THROTTLE_INT_EN	BIT(19)
30#define ADF_GEN4_PM_DRV_ACTIVE		BIT(20)
31#define ADF_GEN4_PM_INIT_STATE		BIT(21)
32#define ADF_GEN4_PM_INT_EN_DEFAULT	(ADF_GEN4_PM_IDLE_INT_EN | \
33					ADF_GEN4_PM_THROTTLE_INT_EN)
34
35#define ADF_GEN4_PM_THR_STS	BIT(0)
36#define ADF_GEN4_PM_IDLE_STS	BIT(1)
37#define ADF_GEN4_PM_FW_INT_STS	BIT(2)
38#define ADF_GEN4_PM_INT_STS_MASK (ADF_GEN4_PM_THR_STS | \
39				 ADF_GEN4_PM_IDLE_STS | \
40				 ADF_GEN4_PM_FW_INT_STS)
41
42#define ADF_GEN4_PM_MSG_PENDING			BIT(0)
43#define ADF_GEN4_PM_MSG_PAYLOAD_BIT_MASK	GENMASK(28, 1)
44
45#define ADF_GEN4_PM_DEFAULT_IDLE_FILTER		(0x6)
46#define ADF_GEN4_PM_MAX_IDLE_FILTER		(0x7)
47#define ADF_GEN4_PM_DEFAULT_IDLE_SUPPORT	(0x1)
48
49/* PM CSRs fields masks */
50#define ADF_GEN4_PM_DOMAIN_POWER_GATED_MASK	GENMASK(15, 0)
51#define ADF_GEN4_PM_SSM_PM_ENABLE_MASK		GENMASK(15, 0)
52#define ADF_GEN4_PM_IDLE_FILTER_MASK		GENMASK(5, 3)
53#define ADF_GEN4_PM_IDLE_ENABLE_MASK		BIT(2)
54#define ADF_GEN4_PM_ENABLE_PM_MASK		BIT(21)
55#define ADF_GEN4_PM_ENABLE_PM_IDLE_MASK		BIT(22)
56#define ADF_GEN4_PM_ENABLE_DEEP_PM_IDLE_MASK	BIT(23)
57#define ADF_GEN4_PM_CURRENT_WP_MASK		GENMASK(19, 11)
58#define ADF_GEN4_PM_CPM_PM_STATE_MASK		GENMASK(22, 20)
59#define ADF_GEN4_PM_PENDING_WP_MASK		GENMASK(31, 23)
60#define ADF_GEN4_PM_THR_VALUE_MASK		GENMASK(6, 4)
61#define ADF_GEN4_PM_MIN_PWR_ACK_MASK		BIT(7)
62#define ADF_GEN4_PM_MIN_PWR_ACK_PENDING_MASK	BIT(17)
63#define ADF_GEN4_PM_CPR_ACTIVE_COUNT_MASK	BIT(0)
64#define ADF_GEN4_PM_CPR_MANAGED_COUNT_MASK	BIT(0)
65#define ADF_GEN4_PM_XLT_ACTIVE_COUNT_MASK	BIT(1)
66#define ADF_GEN4_PM_XLT_MANAGED_COUNT_MASK	BIT(1)
67#define ADF_GEN4_PM_DCPR_ACTIVE_COUNT_MASK	GENMASK(3, 2)
68#define ADF_GEN4_PM_DCPR_MANAGED_COUNT_MASK	GENMASK(3, 2)
69#define ADF_GEN4_PM_PKE_ACTIVE_COUNT_MASK	GENMASK(8, 4)
70#define ADF_GEN4_PM_PKE_MANAGED_COUNT_MASK	GENMASK(8, 4)
71#define ADF_GEN4_PM_WAT_ACTIVE_COUNT_MASK	GENMASK(13, 9)
72#define ADF_GEN4_PM_WAT_MANAGED_COUNT_MASK	GENMASK(13, 9)
73#define ADF_GEN4_PM_WCP_ACTIVE_COUNT_MASK	GENMASK(18, 14)
74#define ADF_GEN4_PM_WCP_MANAGED_COUNT_MASK	GENMASK(18, 14)
75#define ADF_GEN4_PM_UCS_ACTIVE_COUNT_MASK	GENMASK(20, 19)
76#define ADF_GEN4_PM_UCS_MANAGED_COUNT_MASK	GENMASK(20, 19)
77#define ADF_GEN4_PM_CPH_ACTIVE_COUNT_MASK	GENMASK(24, 21)
78#define ADF_GEN4_PM_CPH_MANAGED_COUNT_MASK	GENMASK(24, 21)
79#define ADF_GEN4_PM_ATH_ACTIVE_COUNT_MASK	GENMASK(28, 25)
80#define ADF_GEN4_PM_ATH_MANAGED_COUNT_MASK	GENMASK(28, 25)
81
82int adf_gen4_enable_pm(struct adf_accel_dev *accel_dev);
83bool adf_gen4_handle_pm_interrupt(struct adf_accel_dev *accel_dev);
84
85#ifdef CONFIG_DEBUG_FS
86void adf_gen4_init_dev_pm_data(struct adf_accel_dev *accel_dev);
87#else
88static inline void adf_gen4_init_dev_pm_data(struct adf_accel_dev *accel_dev)
89{
90}
91#endif /* CONFIG_DEBUG_FS */
92
93#endif