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1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2/* Copyright(c) 2020 Intel Corporation */
3#ifndef ADF_GEN2_HW_DATA_H_
4#define ADF_GEN2_HW_DATA_H_
5
6#include "adf_accel_devices.h"
7#include "adf_cfg_common.h"
8
9/* Transport access */
10#define ADF_BANK_INT_SRC_SEL_MASK_0 0x4444444CUL
11#define ADF_BANK_INT_SRC_SEL_MASK_X 0x44444444UL
12#define ADF_RING_CSR_RING_CONFIG 0x000
13#define ADF_RING_CSR_RING_LBASE 0x040
14#define ADF_RING_CSR_RING_UBASE 0x080
15#define ADF_RING_CSR_RING_HEAD 0x0C0
16#define ADF_RING_CSR_RING_TAIL 0x100
17#define ADF_RING_CSR_E_STAT 0x14C
18#define ADF_RING_CSR_INT_FLAG 0x170
19#define ADF_RING_CSR_INT_SRCSEL 0x174
20#define ADF_RING_CSR_INT_SRCSEL_2 0x178
21#define ADF_RING_CSR_INT_COL_EN 0x17C
22#define ADF_RING_CSR_INT_COL_CTL 0x180
23#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
24#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
25#define ADF_RING_BUNDLE_SIZE 0x1000
26#define ADF_GEN2_RX_RINGS_OFFSET 8
27#define ADF_GEN2_TX_RINGS_MASK 0xFF
28
29#define BUILD_RING_BASE_ADDR(addr, size) \
30 (((addr) >> 6) & (GENMASK_ULL(63, 0) << (size)))
31#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
32 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
33 ADF_RING_CSR_RING_HEAD + ((ring) << 2))
34#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
35 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
36 ADF_RING_CSR_RING_TAIL + ((ring) << 2))
37#define READ_CSR_E_STAT(csr_base_addr, bank) \
38 ADF_CSR_RD(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
39 ADF_RING_CSR_E_STAT)
40#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
41 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
42 ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
43#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
44do { \
45 u32 l_base = 0, u_base = 0; \
46 l_base = (u32)((value) & 0xFFFFFFFF); \
47 u_base = (u32)(((value) & 0xFFFFFFFF00000000ULL) >> 32); \
48 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
49 ADF_RING_CSR_RING_LBASE + ((ring) << 2), l_base); \
50 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
51 ADF_RING_CSR_RING_UBASE + ((ring) << 2), u_base); \
52} while (0)
53
54#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
55 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
56 ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
57#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
58 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
59 ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
60#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
61 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
62 ADF_RING_CSR_INT_FLAG, value)
63#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
64do { \
65 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
66 ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK_0); \
67 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
68 ADF_RING_CSR_INT_SRCSEL_2, ADF_BANK_INT_SRC_SEL_MASK_X); \
69} while (0)
70#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
71 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
72 ADF_RING_CSR_INT_COL_EN, value)
73#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
74 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
75 ADF_RING_CSR_INT_COL_CTL, \
76 ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
77#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
78 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * (bank)) + \
79 ADF_RING_CSR_INT_FLAG_AND_COL, value)
80
81/* AE to function map */
82#define AE2FUNCTION_MAP_A_OFFSET (0x3A400 + 0x190)
83#define AE2FUNCTION_MAP_B_OFFSET (0x3A400 + 0x310)
84#define AE2FUNCTION_MAP_REG_SIZE 4
85#define AE2FUNCTION_MAP_VALID BIT(7)
86
87#define READ_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index) \
88 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
89 AE2FUNCTION_MAP_REG_SIZE * (index))
90#define WRITE_CSR_AE2FUNCTION_MAP_A(pmisc_bar_addr, index, value) \
91 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_A_OFFSET + \
92 AE2FUNCTION_MAP_REG_SIZE * (index), value)
93#define READ_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index) \
94 ADF_CSR_RD(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
95 AE2FUNCTION_MAP_REG_SIZE * (index))
96#define WRITE_CSR_AE2FUNCTION_MAP_B(pmisc_bar_addr, index, value) \
97 ADF_CSR_WR(pmisc_bar_addr, AE2FUNCTION_MAP_B_OFFSET + \
98 AE2FUNCTION_MAP_REG_SIZE * (index), value)
99
100/* Admin Interface Offsets */
101#define ADF_ADMINMSGUR_OFFSET (0x3A000 + 0x574)
102#define ADF_ADMINMSGLR_OFFSET (0x3A000 + 0x578)
103#define ADF_MAILBOX_BASE_OFFSET 0x20970
104
105/* Arbiter configuration */
106#define ADF_ARB_OFFSET 0x30000
107#define ADF_ARB_WRK_2_SER_MAP_OFFSET 0x180
108#define ADF_ARB_CONFIG (BIT(31) | BIT(6) | BIT(0))
109#define ADF_ARB_REG_SLOT 0x1000
110#define ADF_ARB_RINGSRVARBEN_OFFSET 0x19C
111
112#define WRITE_CSR_RING_SRV_ARB_EN(csr_addr, index, value) \
113 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
114 (ADF_ARB_REG_SLOT * (index)), value)
115
116/* Power gating */
117#define ADF_POWERGATE_DC BIT(23)
118#define ADF_POWERGATE_PKE BIT(24)
119
120/* Default ring mapping */
121#define ADF_GEN2_DEFAULT_RING_TO_SRV_MAP \
122 (CRYPTO << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
123 CRYPTO << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
124 UNUSED << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
125 COMP << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
126
127/* WDT timers
128 *
129 * Timeout is in cycles. Clock speed may vary across products but this
130 * value should be a few milli-seconds.
131 */
132#define ADF_SSM_WDT_DEFAULT_VALUE 0x200000
133#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x2000000
134#define ADF_SSMWDT_OFFSET 0x54
135#define ADF_SSMWDTPKE_OFFSET 0x58
136#define ADF_SSMWDT(i) (ADF_SSMWDT_OFFSET + ((i) * 0x4000))
137#define ADF_SSMWDTPKE(i) (ADF_SSMWDTPKE_OFFSET + ((i) * 0x4000))
138
139/* Error detection and correction */
140#define ADF_GEN2_AE_CTX_ENABLES(i) ((i) * 0x1000 + 0x20818)
141#define ADF_GEN2_AE_MISC_CONTROL(i) ((i) * 0x1000 + 0x20960)
142#define ADF_GEN2_ENABLE_AE_ECC_ERR BIT(28)
143#define ADF_GEN2_ENABLE_AE_ECC_PARITY_CORR (BIT(24) | BIT(12))
144#define ADF_GEN2_UERRSSMSH(i) ((i) * 0x4000 + 0x18)
145#define ADF_GEN2_CERRSSMSH(i) ((i) * 0x4000 + 0x10)
146#define ADF_GEN2_ERRSSMSH_EN BIT(3)
147
148/* Number of heartbeat counter pairs */
149#define ADF_NUM_HB_CNT_PER_AE ADF_NUM_THREADS_PER_AE
150
151/* Interrupts */
152#define ADF_GEN2_SMIAPF0_MASK_OFFSET (0x3A000 + 0x28)
153#define ADF_GEN2_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
154#define ADF_GEN2_SMIA1_MASK 0x1
155
156u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
157u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
158void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
159void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
160 int num_a_regs, int num_b_regs);
161void adf_gen2_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
162void adf_gen2_get_admin_info(struct admin_info *admin_csrs_info);
163void adf_gen2_get_arb_info(struct arb_info *arb_info);
164void adf_gen2_enable_ints(struct adf_accel_dev *accel_dev);
165u32 adf_gen2_get_accel_cap(struct adf_accel_dev *accel_dev);
166void adf_gen2_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
167
168#endif