1// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
  2/* Copyright(c) 2014 - 2021 Intel Corporation */
  3#include <adf_accel_devices.h>
  4#include <adf_admin.h>
  5#include <adf_clock.h>
  6#include <adf_common_drv.h>
  7#include <adf_gen2_config.h>
  8#include <adf_gen2_dc.h>
  9#include <adf_gen2_hw_data.h>
 10#include <adf_gen2_pfvf.h>
 11#include "adf_c62x_hw_data.h"
 12#include "adf_heartbeat.h"
 13#include "icp_qat_hw.h"
 14
 15/* Worker thread to service arbiter mappings */
 16static const u32 thrd_to_arb_map[ADF_C62X_MAX_ACCELENGINES] = {
 17	0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA,
 18	0x11222AAA, 0x12222AAA, 0x11222AAA, 0x12222AAA, 0x11222AAA
 19};
 20
 21static struct adf_hw_device_class c62x_class = {
 22	.name = ADF_C62X_DEVICE_NAME,
 23	.type = DEV_C62X,
 24	.instances = 0
 25};
 26
 27static u32 get_accel_mask(struct adf_hw_device_data *self)
 28{
 29	u32 straps = self->straps;
 30	u32 fuses = self->fuses;
 31	u32 accel;
 32
 33	accel = ~(fuses | straps) >> ADF_C62X_ACCELERATORS_REG_OFFSET;
 34	accel &= ADF_C62X_ACCELERATORS_MASK;
 35
 36	return accel;
 37}
 38
 39static u32 get_ae_mask(struct adf_hw_device_data *self)
 40{
 41	u32 straps = self->straps;
 42	u32 fuses = self->fuses;
 43	unsigned long disabled;
 44	u32 ae_disable;
 45	int accel;
 46
 47	/* If an accel is disabled, then disable the corresponding two AEs */
 48	disabled = ~get_accel_mask(self) & ADF_C62X_ACCELERATORS_MASK;
 49	ae_disable = BIT(1) | BIT(0);
 50	for_each_set_bit(accel, &disabled, ADF_C62X_MAX_ACCELERATORS)
 51		straps |= ae_disable << (accel << 1);
 52
 53	return ~(fuses | straps) & ADF_C62X_ACCELENGINES_MASK;
 54}
 55
 56static u32 get_ts_clock(struct adf_hw_device_data *self)
 57{
 58	/*
 59	 * Timestamp update interval is 16 AE clock ticks for c62x.
 60	 */
 61	return self->clock_frequency / 16;
 62}
 63
 64static int measure_clock(struct adf_accel_dev *accel_dev)
 65{
 66	u32 frequency;
 67	int ret;
 68
 69	ret = adf_dev_measure_clock(accel_dev, &frequency, ADF_C62X_MIN_AE_FREQ,
 70				    ADF_C62X_MAX_AE_FREQ);
 71	if (ret)
 72		return ret;
 73
 74	accel_dev->hw_device->clock_frequency = frequency;
 75	return 0;
 76}
 77
 78static u32 get_misc_bar_id(struct adf_hw_device_data *self)
 79{
 80	return ADF_C62X_PMISC_BAR;
 81}
 82
 83static u32 get_etr_bar_id(struct adf_hw_device_data *self)
 84{
 85	return ADF_C62X_ETR_BAR;
 86}
 87
 88static u32 get_sram_bar_id(struct adf_hw_device_data *self)
 89{
 90	return ADF_C62X_SRAM_BAR;
 91}
 92
 93static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
 94{
 95	int aes = self->get_num_aes(self);
 96
 97	if (aes == 8)
 98		return DEV_SKU_2;
 99	else if (aes == 10)
100		return DEV_SKU_4;
101
102	return DEV_SKU_UNKNOWN;
103}
104
105static const u32 *adf_get_arbiter_mapping(struct adf_accel_dev *accel_dev)
106{
107	return thrd_to_arb_map;
108}
109
110static void configure_iov_threads(struct adf_accel_dev *accel_dev, bool enable)
111{
112	adf_gen2_cfg_iov_thds(accel_dev, enable,
113			      ADF_C62X_AE2FUNC_MAP_GRP_A_NUM_REGS,
114			      ADF_C62X_AE2FUNC_MAP_GRP_B_NUM_REGS);
115}
116
117void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
118{
119	hw_data->dev_class = &c62x_class;
120	hw_data->instance_id = c62x_class.instances++;
121	hw_data->num_banks = ADF_C62X_ETR_MAX_BANKS;
122	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
123	hw_data->num_accel = ADF_C62X_MAX_ACCELERATORS;
124	hw_data->num_logical_accel = 1;
125	hw_data->num_engines = ADF_C62X_MAX_ACCELENGINES;
126	hw_data->tx_rx_gap = ADF_GEN2_RX_RINGS_OFFSET;
127	hw_data->tx_rings_mask = ADF_GEN2_TX_RINGS_MASK;
128	hw_data->ring_to_svc_map = ADF_GEN2_DEFAULT_RING_TO_SRV_MAP;
129	hw_data->alloc_irq = adf_isr_resource_alloc;
130	hw_data->free_irq = adf_isr_resource_free;
131	hw_data->enable_error_correction = adf_gen2_enable_error_correction;
132	hw_data->get_accel_mask = get_accel_mask;
133	hw_data->get_ae_mask = get_ae_mask;
134	hw_data->get_accel_cap = adf_gen2_get_accel_cap;
135	hw_data->get_num_accels = adf_gen2_get_num_accels;
136	hw_data->get_num_aes = adf_gen2_get_num_aes;
137	hw_data->get_sram_bar_id = get_sram_bar_id;
138	hw_data->get_etr_bar_id = get_etr_bar_id;
139	hw_data->get_misc_bar_id = get_misc_bar_id;
140	hw_data->get_admin_info = adf_gen2_get_admin_info;
141	hw_data->get_arb_info = adf_gen2_get_arb_info;
142	hw_data->get_sku = get_sku;
143	hw_data->fw_name = ADF_C62X_FW;
144	hw_data->fw_mmp_name = ADF_C62X_MMP;
145	hw_data->init_admin_comms = adf_init_admin_comms;
146	hw_data->exit_admin_comms = adf_exit_admin_comms;
147	hw_data->configure_iov_threads = configure_iov_threads;
148	hw_data->send_admin_init = adf_send_admin_init;
149	hw_data->init_arb = adf_init_arb;
150	hw_data->exit_arb = adf_exit_arb;
151	hw_data->get_arb_mapping = adf_get_arbiter_mapping;
152	hw_data->enable_ints = adf_gen2_enable_ints;
153	hw_data->reset_device = adf_reset_flr;
154	hw_data->set_ssm_wdtimer = adf_gen2_set_ssm_wdtimer;
155	hw_data->disable_iov = adf_disable_sriov;
156	hw_data->dev_config = adf_gen2_dev_config;
157	hw_data->measure_clock = measure_clock;
158	hw_data->get_hb_clock = get_ts_clock;
159	hw_data->num_hb_ctrs = ADF_NUM_HB_CNT_PER_AE;
160	hw_data->check_hb_ctrs = adf_heartbeat_check_ctrs;
161
162	adf_gen2_init_pf_pfvf_ops(&hw_data->pfvf_ops);
163	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
164	adf_gen2_init_dc_ops(&hw_data->dc_ops);
165}
166
167void adf_clean_hw_data_c62x(struct adf_hw_device_data *hw_data)
168{
169	hw_data->dev_class->instances--;
170}