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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 | // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2017, Intel Corporation */ #include <linux/clk-provider.h> #include <linux/io.h> #include <linux/slab.h> #include "stratix10-clk.h" #include "clk.h" #define SOCFPGA_CS_PDBG_CLK "cs_pdbg_clk" #define to_socfpga_gate_clk(p) container_of(p, struct socfpga_gate_clk, hw.hw) #define SOCFPGA_EMAC0_CLK "emac0_clk" #define SOCFPGA_EMAC1_CLK "emac1_clk" #define SOCFPGA_EMAC2_CLK "emac2_clk" #define AGILEX_BYPASS_OFFSET 0xC #define STRATIX10_BYPASS_OFFSET 0x2C #define BOOTCLK_BYPASS 2 static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); u32 div = 1, val; if (socfpgaclk->fixed_div) { div = socfpgaclk->fixed_div; } else if (socfpgaclk->div_reg) { val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val &= GENMASK(socfpgaclk->width - 1, 0); div = (1 << val); } return parent_rate / div; } static unsigned long socfpga_dbg_clk_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); u32 div, val; val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift; val &= GENMASK(socfpgaclk->width - 1, 0); div = (1 << val); div = div ? 4 : 1; return parent_rate / div; } static u8 socfpga_gate_get_parent(struct clk_hw *hwclk) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); u32 mask, second_bypass; u8 parent = 0; const char *name = clk_hw_get_name(hwclk); if (socfpgaclk->bypass_reg) { mask = (0x1 << socfpgaclk->bypass_shift); parent = ((readl(socfpgaclk->bypass_reg) & mask) >> socfpgaclk->bypass_shift); } if (streq(name, SOCFPGA_EMAC0_CLK) || streq(name, SOCFPGA_EMAC1_CLK) || streq(name, SOCFPGA_EMAC2_CLK)) { second_bypass = readl(socfpgaclk->bypass_reg - STRATIX10_BYPASS_OFFSET); /* EMACA bypass to bootclk @0xB0 offset */ if (second_bypass & 0x1) if (parent == 0) /* only applicable if parent is maca */ parent = BOOTCLK_BYPASS; if (second_bypass & 0x2) if (parent == 1) /* only applicable if parent is macb */ parent = BOOTCLK_BYPASS; } return parent; } static u8 socfpga_agilex_gate_get_parent(struct clk_hw *hwclk) { struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); u32 mask, second_bypass; u8 parent = 0; const char *name = clk_hw_get_name(hwclk); if (socfpgaclk->bypass_reg) { mask = (0x1 << socfpgaclk->bypass_shift); parent = ((readl(socfpgaclk->bypass_reg) & mask) >> socfpgaclk->bypass_shift); } if (streq(name, SOCFPGA_EMAC0_CLK) || streq(name, SOCFPGA_EMAC1_CLK) || streq(name, SOCFPGA_EMAC2_CLK)) { second_bypass = readl(socfpgaclk->bypass_reg - AGILEX_BYPASS_OFFSET); /* EMACA bypass to bootclk @0x88 offset */ if (second_bypass & 0x1) if (parent == 0) /* only applicable if parent is maca */ parent = BOOTCLK_BYPASS; if (second_bypass & 0x2) if (parent == 1) /* only applicable if parent is macb */ parent = BOOTCLK_BYPASS; } return parent; } static struct clk_ops gateclk_ops = { .recalc_rate = socfpga_gate_clk_recalc_rate, .get_parent = socfpga_gate_get_parent, }; static const struct clk_ops agilex_gateclk_ops = { .recalc_rate = socfpga_gate_clk_recalc_rate, .get_parent = socfpga_agilex_gate_get_parent, }; static const struct clk_ops dbgclk_ops = { .recalc_rate = socfpga_dbg_clk_recalc_rate, .get_parent = socfpga_gate_get_parent, }; struct clk_hw *s10_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; struct clk_init_data init; const char *parent_name = clks->parent_name; int ret; socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); if (!socfpga_clk) return NULL; socfpga_clk->hw.reg = regbase + clks->gate_reg; socfpga_clk->hw.bit_idx = clks->gate_idx; gateclk_ops.enable = clk_gate_ops.enable; gateclk_ops.disable = clk_gate_ops.disable; socfpga_clk->fixed_div = clks->fixed_div; if (clks->div_reg) socfpga_clk->div_reg = regbase + clks->div_reg; else socfpga_clk->div_reg = NULL; socfpga_clk->width = clks->div_width; socfpga_clk->shift = clks->div_offset; if (clks->bypass_reg) socfpga_clk->bypass_reg = regbase + clks->bypass_reg; else socfpga_clk->bypass_reg = NULL; socfpga_clk->bypass_shift = clks->bypass_shift; if (streq(clks->name, "cs_pdbg_clk")) init.ops = &dbgclk_ops; else init.ops = &gateclk_ops; init.name = clks->name; init.flags = clks->flags; init.num_parents = clks->num_parents; init.parent_names = parent_name ? &parent_name : NULL; if (init.parent_names == NULL) init.parent_data = clks->parent_data; socfpga_clk->hw.hw.init = &init; hw_clk = &socfpga_clk->hw.hw; ret = clk_hw_register(NULL, &socfpga_clk->hw.hw); if (ret) { kfree(socfpga_clk); return ERR_PTR(ret); } return hw_clk; } struct clk_hw *agilex_register_gate(const struct stratix10_gate_clock *clks, void __iomem *regbase) { struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; struct clk_init_data init; const char *parent_name = clks->parent_name; int ret; socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL); if (!socfpga_clk) return NULL; socfpga_clk->hw.reg = regbase + clks->gate_reg; socfpga_clk->hw.bit_idx = clks->gate_idx; gateclk_ops.enable = clk_gate_ops.enable; gateclk_ops.disable = clk_gate_ops.disable; socfpga_clk->fixed_div = clks->fixed_div; if (clks->div_reg) socfpga_clk->div_reg = regbase + clks->div_reg; else socfpga_clk->div_reg = NULL; socfpga_clk->width = clks->div_width; socfpga_clk->shift = clks->div_offset; if (clks->bypass_reg) socfpga_clk->bypass_reg = regbase + clks->bypass_reg; else socfpga_clk->bypass_reg = NULL; socfpga_clk->bypass_shift = clks->bypass_shift; if (streq(clks->name, "cs_pdbg_clk")) init.ops = &dbgclk_ops; else init.ops = &agilex_gateclk_ops; init.name = clks->name; init.flags = clks->flags; init.num_parents = clks->num_parents; init.parent_names = parent_name ? &parent_name : NULL; if (init.parent_names == NULL) init.parent_data = clks->parent_data; socfpga_clk->hw.hw.init = &init; hw_clk = &socfpga_clk->hw.hw; ret = clk_hw_register(NULL, &socfpga_clk->hw.hw); if (ret) { kfree(socfpga_clk); return ERR_PTR(ret); } return hw_clk; } |