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1// SPDX-License-Identifier: GPL-2.0-only
2//
3// Copyright (c) 2021 MediaTek Inc.
4// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
5
6#include "clk-fhctl.h"
7#include "clk-gate.h"
8#include "clk-mtk.h"
9#include "clk-pll.h"
10#include "clk-pllfh.h"
11
12#include <dt-bindings/clock/mt8195-clk.h>
13#include <linux/mod_devicetable.h>
14#include <linux/platform_device.h>
15
16static const struct mtk_gate_regs apmixed_cg_regs = {
17 .set_ofs = 0x8,
18 .clr_ofs = 0x8,
19 .sta_ofs = 0x8,
20};
21
22#define GATE_APMIXED(_id, _name, _parent, _shift) \
23 GATE_MTK(_id, _name, _parent, &apmixed_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
24
25static const struct mtk_gate apmixed_clks[] = {
26 GATE_APMIXED(CLK_APMIXED_PLL_SSUSB26M, "pll_ssusb26m", "clk26m", 1),
27};
28
29#define MT8195_PLL_FMAX (3800UL * MHZ)
30#define MT8195_PLL_FMIN (1500UL * MHZ)
31#define MT8195_INTEGER_BITS 8
32
33#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \
34 _rst_bar_mask, _pcwbits, _pd_reg, _pd_shift, \
35 _tuner_reg, _tuner_en_reg, _tuner_en_bit, \
36 _pcw_reg, _pcw_shift, _pcw_chg_reg, \
37 _en_reg, _pll_en_bit) { \
38 .id = _id, \
39 .name = _name, \
40 .reg = _reg, \
41 .pwr_reg = _pwr_reg, \
42 .en_mask = _en_mask, \
43 .flags = _flags, \
44 .rst_bar_mask = _rst_bar_mask, \
45 .fmax = MT8195_PLL_FMAX, \
46 .fmin = MT8195_PLL_FMIN, \
47 .pcwbits = _pcwbits, \
48 .pcwibits = MT8195_INTEGER_BITS, \
49 .pd_reg = _pd_reg, \
50 .pd_shift = _pd_shift, \
51 .tuner_reg = _tuner_reg, \
52 .tuner_en_reg = _tuner_en_reg, \
53 .tuner_en_bit = _tuner_en_bit, \
54 .pcw_reg = _pcw_reg, \
55 .pcw_shift = _pcw_shift, \
56 .pcw_chg_reg = _pcw_chg_reg, \
57 .en_reg = _en_reg, \
58 .pll_en_bit = _pll_en_bit, \
59 }
60
61static const struct mtk_pll_data plls[] = {
62 PLL(CLK_APMIXED_NNAPLL, "nnapll", 0x0390, 0x03a0, 0,
63 0, 0, 22, 0x0398, 24, 0, 0, 0, 0x0398, 0, 0x0398, 0, 9),
64 PLL(CLK_APMIXED_RESPLL, "respll", 0x0190, 0x0320, 0,
65 0, 0, 22, 0x0198, 24, 0, 0, 0, 0x0198, 0, 0x0198, 0, 9),
66 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x0360, 0x0370, 0,
67 0, 0, 22, 0x0368, 24, 0, 0, 0, 0x0368, 0, 0x0368, 0, 9),
68 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0710, 0x0720, 0,
69 0, 0, 22, 0x0718, 24, 0, 0, 0, 0x0718, 0, 0x0718, 0, 9),
70 PLL(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x00a0, 0x00b0, 0,
71 0, 0, 22, 0x00a8, 24, 0, 0, 0, 0x00a8, 0, 0x00a8, 0, 9),
72 PLL(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x00c0, 0x00d0, 0,
73 0, 0, 22, 0x00c8, 24, 0, 0, 0, 0x00c8, 0, 0x00c8, 0, 9),
74 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x00e0, 0x00f0, 0xff000000,
75 HAVE_RST_BAR, BIT(23), 22, 0x00e8, 24, 0, 0, 0, 0x00e8, 0, 0x00e8, 0, 9),
76 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x01d0, 0x01e0, 0xff000000,
77 HAVE_RST_BAR, BIT(23), 22, 0x01d8, 24, 0, 0, 0, 0x01d8, 0, 0x01d8, 0, 9),
78 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x0890, 0x08a0, 0,
79 0, 0, 22, 0x0898, 24, 0, 0, 0, 0x0898, 0, 0x0898, 0, 9),
80 PLL(CLK_APMIXED_IMGPLL, "imgpll", 0x0100, 0x0110, 0,
81 0, 0, 22, 0x0108, 24, 0, 0, 0, 0x0108, 0, 0x0108, 0, 9),
82 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x01f0, 0x0700, 0xff000000,
83 HAVE_RST_BAR, BIT(23), 22, 0x01f8, 24, 0, 0, 0, 0x01f8, 0, 0x01f8, 0, 9),
84 PLL(CLK_APMIXED_HDMIPLL1, "hdmipll1", 0x08c0, 0x08d0, 0,
85 0, 0, 22, 0x08c8, 24, 0, 0, 0, 0x08c8, 0, 0x08c8, 0, 9),
86 PLL(CLK_APMIXED_HDMIPLL2, "hdmipll2", 0x0870, 0x0880, 0,
87 0, 0, 22, 0x0878, 24, 0, 0, 0, 0x0878, 0, 0x0878, 0, 9),
88 PLL(CLK_APMIXED_HDMIRX_APLL, "hdmirx_apll", 0x08e0, 0x0dd4, 0,
89 0, 0, 32, 0x08e8, 24, 0, 0, 0, 0x08ec, 0, 0x08e8, 0, 9),
90 PLL(CLK_APMIXED_USB1PLL, "usb1pll", 0x01a0, 0x01b0, 0,
91 0, 0, 22, 0x01a8, 24, 0, 0, 0, 0x01a8, 0, 0x01a8, 0, 9),
92 PLL(CLK_APMIXED_ADSPPLL, "adsppll", 0x07e0, 0x07f0, 0,
93 0, 0, 22, 0x07e8, 24, 0, 0, 0, 0x07e8, 0, 0x07e8, 0, 9),
94 PLL(CLK_APMIXED_APLL1, "apll1", 0x07c0, 0x0dc0, 0,
95 0, 0, 32, 0x07c8, 24, 0x0470, 0x0000, 12, 0x07cc, 0, 0x07c8, 0, 9),
96 PLL(CLK_APMIXED_APLL2, "apll2", 0x0780, 0x0dc4, 0,
97 0, 0, 32, 0x0788, 24, 0x0474, 0x0000, 13, 0x078c, 0, 0x0788, 0, 9),
98 PLL(CLK_APMIXED_APLL3, "apll3", 0x0760, 0x0dc8, 0,
99 0, 0, 32, 0x0768, 24, 0x0478, 0x0000, 14, 0x076c, 0, 0x0768, 0, 9),
100 PLL(CLK_APMIXED_APLL4, "apll4", 0x0740, 0x0dcc, 0,
101 0, 0, 32, 0x0748, 24, 0x047C, 0x0000, 15, 0x074c, 0, 0x0748, 0, 9),
102 PLL(CLK_APMIXED_APLL5, "apll5", 0x07a0, 0x0dd0, 0x100000,
103 0, 0, 32, 0x07a8, 24, 0x0480, 0x0000, 16, 0x07ac, 0, 0x07a8, 0, 9),
104 PLL(CLK_APMIXED_MFGPLL, "mfgpll", 0x0340, 0x0350, 0,
105 0, 0, 22, 0x0348, 24, 0, 0, 0, 0x0348, 0, 0x0348, 0, 9),
106 PLL(CLK_APMIXED_DGIPLL, "dgipll", 0x0150, 0x0160, 0,
107 0, 0, 22, 0x0158, 24, 0, 0, 0, 0x0158, 0, 0x0158, 0, 9),
108};
109
110enum fh_pll_id {
111 FH_ARMPLL_LL,
112 FH_ARMPLL_BL,
113 FH_MEMPLL,
114 FH_ADSPPLL,
115 FH_NNAPLL,
116 FH_CCIPLL,
117 FH_MFGPLL,
118 FH_TVDPLL2,
119 FH_MPLL,
120 FH_MMPLL,
121 FH_MAINPLL,
122 FH_MSDCPLL,
123 FH_IMGPLL,
124 FH_VDECPLL,
125 FH_TVDPLL1,
126 FH_NR_FH,
127};
128
129#define FH(_pllid, _fhid, _offset) { \
130 .data = { \
131 .pll_id = _pllid, \
132 .fh_id = _fhid, \
133 .fh_ver = FHCTL_PLLFH_V2, \
134 .fhx_offset = _offset, \
135 .dds_mask = GENMASK(21, 0), \
136 .slope0_value = 0x6003c97, \
137 .slope1_value = 0x6003c97, \
138 .sfstrx_en = BIT(2), \
139 .frddsx_en = BIT(1), \
140 .fhctlx_en = BIT(0), \
141 .tgl_org = BIT(31), \
142 .dvfs_tri = BIT(31), \
143 .pcwchg = BIT(31), \
144 .dt_val = 0x0, \
145 .df_val = 0x9, \
146 .updnlmt_shft = 16, \
147 .msk_frddsx_dys = GENMASK(23, 20), \
148 .msk_frddsx_dts = GENMASK(19, 16), \
149 }, \
150 }
151
152static struct mtk_pllfh_data pllfhs[] = {
153 FH(CLK_APMIXED_ADSPPLL, FH_ADSPPLL, 0x78),
154 FH(CLK_APMIXED_NNAPLL, FH_NNAPLL, 0x8c),
155 FH(CLK_APMIXED_MFGPLL, FH_MFGPLL, 0xb4),
156 FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL2, 0xc8),
157 FH(CLK_APMIXED_MMPLL, FH_MMPLL, 0xf0),
158 FH(CLK_APMIXED_MAINPLL, FH_MAINPLL, 0x104),
159 FH(CLK_APMIXED_MSDCPLL, FH_MSDCPLL, 0x118),
160 FH(CLK_APMIXED_IMGPLL, FH_IMGPLL, 0x12c),
161 FH(CLK_APMIXED_VDECPLL, FH_VDECPLL, 0x140),
162 FH(CLK_APMIXED_TVDPLL2, FH_TVDPLL1, 0x154),
163};
164
165static const struct of_device_id of_match_clk_mt8195_apmixed[] = {
166 { .compatible = "mediatek,mt8195-apmixedsys", },
167 {}
168};
169MODULE_DEVICE_TABLE(of, of_match_clk_mt8195_apmixed);
170
171static int clk_mt8195_apmixed_probe(struct platform_device *pdev)
172{
173 struct clk_hw_onecell_data *clk_data;
174 struct device_node *node = pdev->dev.of_node;
175 const u8 *fhctl_node = "mediatek,mt8195-fhctl";
176 int r;
177
178 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
179 if (!clk_data)
180 return -ENOMEM;
181
182 fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
183
184 r = mtk_clk_register_pllfhs(node, plls, ARRAY_SIZE(plls),
185 pllfhs, ARRAY_SIZE(pllfhs), clk_data);
186 if (r)
187 goto free_apmixed_data;
188
189 r = mtk_clk_register_gates(&pdev->dev, node, apmixed_clks,
190 ARRAY_SIZE(apmixed_clks), clk_data);
191 if (r)
192 goto unregister_plls;
193
194 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
195 if (r)
196 goto unregister_gates;
197
198 platform_set_drvdata(pdev, clk_data);
199
200 return r;
201
202unregister_gates:
203 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
204unregister_plls:
205 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
206 ARRAY_SIZE(pllfhs), clk_data);
207free_apmixed_data:
208 mtk_free_clk_data(clk_data);
209 return r;
210}
211
212static void clk_mt8195_apmixed_remove(struct platform_device *pdev)
213{
214 struct device_node *node = pdev->dev.of_node;
215 struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
216
217 of_clk_del_provider(node);
218 mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
219 mtk_clk_unregister_pllfhs(plls, ARRAY_SIZE(plls), pllfhs,
220 ARRAY_SIZE(pllfhs), clk_data);
221 mtk_free_clk_data(clk_data);
222}
223
224static struct platform_driver clk_mt8195_apmixed_drv = {
225 .probe = clk_mt8195_apmixed_probe,
226 .remove_new = clk_mt8195_apmixed_remove,
227 .driver = {
228 .name = "clk-mt8195-apmixed",
229 .of_match_table = of_match_clk_mt8195_apmixed,
230 },
231};
232module_platform_driver(clk_mt8195_apmixed_drv);
233MODULE_LICENSE("GPL");