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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 | // SPDX-License-Identifier: GPL-2.0-or-later /* * Copyright (C) 2007 Lemote Inc. * Author: Fuxin Zhang, zhangfx@lemote.com */ #include <linux/export.h> #include <linux/init.h> #include <linux/interrupt.h> #include <asm/irq_cpu.h> #include <asm/i8259.h> #include <asm/mipsregs.h> #include <loongson.h> #include <machine.h> #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ #define LOONGSON_INT_BIT_INT0 (1 << 11) #define LOONGSON_INT_BIT_INT1 (1 << 12) /* * The generic i8259_irq() make the kernel hang on booting. Since we cannot * get the irq via the IRR directly, we access the ISR instead. */ int mach_i8259_irq(void) { int irq, isr; irq = -1; if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { raw_spin_lock(&i8259A_lock); isr = inb(PIC_MASTER_CMD) & ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); if (!isr) isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; irq = ffs(isr) - 1; if (unlikely(irq == 7)) { /* * This may be a spurious interrupt. * * Read the interrupt status register (ISR). If the most * significant bit is not set then there is no valid * interrupt. */ outb(0x0B, PIC_MASTER_ISR); /* ISR register */ if (~inb(PIC_MASTER_ISR) & 0x80) irq = -1; } raw_spin_unlock(&i8259A_lock); } return irq; } EXPORT_SYMBOL(mach_i8259_irq); static void i8259_irqdispatch(void) { int irq; irq = mach_i8259_irq(); if (irq >= 0) do_IRQ(irq); else spurious_interrupt(); } void mach_irq_dispatch(unsigned int pending) { if (pending & CAUSEF_IP7) do_IRQ(LOONGSON_TIMER_IRQ); else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ bonito_irqdispatch(); } else if (pending & CAUSEF_IP3) /* CPU UART */ do_IRQ(LOONGSON_UART_IRQ); else if (pending & CAUSEF_IP2) /* South Bridge */ i8259_irqdispatch(); else spurious_interrupt(); } static irqreturn_t ip6_action(int cpl, void *dev_id) { return IRQ_HANDLED; } void __init mach_init_irq(void) { /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt * 32-63 ------> bonito irq */ /* setup cs5536 as high level trigger */ LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); /* Sets the first-level interrupt dispatcher. */ mips_cpu_irq_init(); init_i8259_irqs(); bonito_irq_init(); /* setup north bridge irq (bonito) */ if (request_irq(LOONGSON_NORTH_BRIDGE_IRQ, ip6_action, IRQF_SHARED | IRQF_NO_THREAD, "cascade", ip6_action)) pr_err("Failed to register north bridge cascade interrupt\n"); /* setup source bridge irq (i8259) */ if (request_irq(LOONGSON_SOUTH_BRIDGE_IRQ, no_action, IRQF_NO_THREAD | IRQF_NO_SUSPEND, "cascade", NULL)) pr_err("Failed to register south bridge cascade interrupt\n"); } |