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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4 */
5#ifndef _ASM_LOONGARCH_H
6#define _ASM_LOONGARCH_H
7
8#include <linux/bits.h>
9#include <linux/linkage.h>
10#include <linux/types.h>
11
12#ifndef __ASSEMBLY__
13#include <larchintrin.h>
14
15/* CPUCFG */
16#define read_cpucfg(reg) __cpucfg(reg)
17
18#endif /* !__ASSEMBLY__ */
19
20#ifdef __ASSEMBLY__
21
22/* LoongArch Registers */
23#define REG_ZERO 0x0
24#define REG_RA 0x1
25#define REG_TP 0x2
26#define REG_SP 0x3
27#define REG_A0 0x4 /* Reused as V0 for return value */
28#define REG_A1 0x5 /* Reused as V1 for return value */
29#define REG_A2 0x6
30#define REG_A3 0x7
31#define REG_A4 0x8
32#define REG_A5 0x9
33#define REG_A6 0xa
34#define REG_A7 0xb
35#define REG_T0 0xc
36#define REG_T1 0xd
37#define REG_T2 0xe
38#define REG_T3 0xf
39#define REG_T4 0x10
40#define REG_T5 0x11
41#define REG_T6 0x12
42#define REG_T7 0x13
43#define REG_T8 0x14
44#define REG_U0 0x15 /* Kernel uses it as percpu base */
45#define REG_FP 0x16
46#define REG_S0 0x17
47#define REG_S1 0x18
48#define REG_S2 0x19
49#define REG_S3 0x1a
50#define REG_S4 0x1b
51#define REG_S5 0x1c
52#define REG_S6 0x1d
53#define REG_S7 0x1e
54#define REG_S8 0x1f
55
56#endif /* __ASSEMBLY__ */
57
58/* Bit fields for CPUCFG registers */
59#define LOONGARCH_CPUCFG0 0x0
60#define CPUCFG0_PRID GENMASK(31, 0)
61
62#define LOONGARCH_CPUCFG1 0x1
63#define CPUCFG1_ISGR32 BIT(0)
64#define CPUCFG1_ISGR64 BIT(1)
65#define CPUCFG1_PAGING BIT(2)
66#define CPUCFG1_IOCSR BIT(3)
67#define CPUCFG1_PABITS GENMASK(11, 4)
68#define CPUCFG1_VABITS GENMASK(19, 12)
69#define CPUCFG1_UAL BIT(20)
70#define CPUCFG1_RI BIT(21)
71#define CPUCFG1_EP BIT(22)
72#define CPUCFG1_RPLV BIT(23)
73#define CPUCFG1_HUGEPG BIT(24)
74#define CPUCFG1_CRC32 BIT(25)
75#define CPUCFG1_MSGINT BIT(26)
76
77#define LOONGARCH_CPUCFG2 0x2
78#define CPUCFG2_FP BIT(0)
79#define CPUCFG2_FPSP BIT(1)
80#define CPUCFG2_FPDP BIT(2)
81#define CPUCFG2_FPVERS GENMASK(5, 3)
82#define CPUCFG2_LSX BIT(6)
83#define CPUCFG2_LASX BIT(7)
84#define CPUCFG2_COMPLEX BIT(8)
85#define CPUCFG2_CRYPTO BIT(9)
86#define CPUCFG2_LVZP BIT(10)
87#define CPUCFG2_LVZVER GENMASK(13, 11)
88#define CPUCFG2_LLFTP BIT(14)
89#define CPUCFG2_LLFTPREV GENMASK(17, 15)
90#define CPUCFG2_X86BT BIT(18)
91#define CPUCFG2_ARMBT BIT(19)
92#define CPUCFG2_MIPSBT BIT(20)
93#define CPUCFG2_LSPW BIT(21)
94#define CPUCFG2_LAM BIT(22)
95#define CPUCFG2_PTW BIT(24)
96
97#define LOONGARCH_CPUCFG3 0x3
98#define CPUCFG3_CCDMA BIT(0)
99#define CPUCFG3_SFB BIT(1)
100#define CPUCFG3_UCACC BIT(2)
101#define CPUCFG3_LLEXC BIT(3)
102#define CPUCFG3_SCDLY BIT(4)
103#define CPUCFG3_LLDBAR BIT(5)
104#define CPUCFG3_ITLBT BIT(6)
105#define CPUCFG3_ICACHET BIT(7)
106#define CPUCFG3_SPW_LVL GENMASK(10, 8)
107#define CPUCFG3_SPW_HG_HF BIT(11)
108#define CPUCFG3_RVA BIT(12)
109#define CPUCFG3_RVAMAX GENMASK(16, 13)
110
111#define LOONGARCH_CPUCFG4 0x4
112#define CPUCFG4_CCFREQ GENMASK(31, 0)
113
114#define LOONGARCH_CPUCFG5 0x5
115#define CPUCFG5_CCMUL GENMASK(15, 0)
116#define CPUCFG5_CCDIV GENMASK(31, 16)
117
118#define LOONGARCH_CPUCFG6 0x6
119#define CPUCFG6_PMP BIT(0)
120#define CPUCFG6_PAMVER GENMASK(3, 1)
121#define CPUCFG6_PMNUM GENMASK(7, 4)
122#define CPUCFG6_PMBITS GENMASK(13, 8)
123#define CPUCFG6_UPM BIT(14)
124
125#define LOONGARCH_CPUCFG16 0x10
126#define CPUCFG16_L1_IUPRE BIT(0)
127#define CPUCFG16_L1_IUUNIFY BIT(1)
128#define CPUCFG16_L1_DPRE BIT(2)
129#define CPUCFG16_L2_IUPRE BIT(3)
130#define CPUCFG16_L2_IUUNIFY BIT(4)
131#define CPUCFG16_L2_IUPRIV BIT(5)
132#define CPUCFG16_L2_IUINCL BIT(6)
133#define CPUCFG16_L2_DPRE BIT(7)
134#define CPUCFG16_L2_DPRIV BIT(8)
135#define CPUCFG16_L2_DINCL BIT(9)
136#define CPUCFG16_L3_IUPRE BIT(10)
137#define CPUCFG16_L3_IUUNIFY BIT(11)
138#define CPUCFG16_L3_IUPRIV BIT(12)
139#define CPUCFG16_L3_IUINCL BIT(13)
140#define CPUCFG16_L3_DPRE BIT(14)
141#define CPUCFG16_L3_DPRIV BIT(15)
142#define CPUCFG16_L3_DINCL BIT(16)
143
144#define LOONGARCH_CPUCFG17 0x11
145#define LOONGARCH_CPUCFG18 0x12
146#define LOONGARCH_CPUCFG19 0x13
147#define LOONGARCH_CPUCFG20 0x14
148#define CPUCFG_CACHE_WAYS_M GENMASK(15, 0)
149#define CPUCFG_CACHE_SETS_M GENMASK(23, 16)
150#define CPUCFG_CACHE_LSIZE_M GENMASK(30, 24)
151#define CPUCFG_CACHE_WAYS 0
152#define CPUCFG_CACHE_SETS 16
153#define CPUCFG_CACHE_LSIZE 24
154
155#define LOONGARCH_CPUCFG48 0x30
156#define CPUCFG48_MCSR_LCK BIT(0)
157#define CPUCFG48_NAP_EN BIT(1)
158#define CPUCFG48_VFPU_CG BIT(2)
159#define CPUCFG48_RAM_CG BIT(3)
160
161#ifndef __ASSEMBLY__
162
163/* CSR */
164#define csr_read32(reg) __csrrd_w(reg)
165#define csr_read64(reg) __csrrd_d(reg)
166#define csr_write32(val, reg) __csrwr_w(val, reg)
167#define csr_write64(val, reg) __csrwr_d(val, reg)
168#define csr_xchg32(val, mask, reg) __csrxchg_w(val, mask, reg)
169#define csr_xchg64(val, mask, reg) __csrxchg_d(val, mask, reg)
170
171/* IOCSR */
172#define iocsr_read32(reg) __iocsrrd_w(reg)
173#define iocsr_read64(reg) __iocsrrd_d(reg)
174#define iocsr_write32(val, reg) __iocsrwr_w(val, reg)
175#define iocsr_write64(val, reg) __iocsrwr_d(val, reg)
176
177#endif /* !__ASSEMBLY__ */
178
179/* CSR register number */
180
181/* Basic CSR registers */
182#define LOONGARCH_CSR_CRMD 0x0 /* Current mode info */
183#define CSR_CRMD_WE_SHIFT 9
184#define CSR_CRMD_WE (_ULCAST_(0x1) << CSR_CRMD_WE_SHIFT)
185#define CSR_CRMD_DACM_SHIFT 7
186#define CSR_CRMD_DACM_WIDTH 2
187#define CSR_CRMD_DACM (_ULCAST_(0x3) << CSR_CRMD_DACM_SHIFT)
188#define CSR_CRMD_DACF_SHIFT 5
189#define CSR_CRMD_DACF_WIDTH 2
190#define CSR_CRMD_DACF (_ULCAST_(0x3) << CSR_CRMD_DACF_SHIFT)
191#define CSR_CRMD_PG_SHIFT 4
192#define CSR_CRMD_PG (_ULCAST_(0x1) << CSR_CRMD_PG_SHIFT)
193#define CSR_CRMD_DA_SHIFT 3
194#define CSR_CRMD_DA (_ULCAST_(0x1) << CSR_CRMD_DA_SHIFT)
195#define CSR_CRMD_IE_SHIFT 2
196#define CSR_CRMD_IE (_ULCAST_(0x1) << CSR_CRMD_IE_SHIFT)
197#define CSR_CRMD_PLV_SHIFT 0
198#define CSR_CRMD_PLV_WIDTH 2
199#define CSR_CRMD_PLV (_ULCAST_(0x3) << CSR_CRMD_PLV_SHIFT)
200
201#define PLV_KERN 0
202#define PLV_USER 3
203#define PLV_MASK 0x3
204
205#define LOONGARCH_CSR_PRMD 0x1 /* Prev-exception mode info */
206#define CSR_PRMD_PWE_SHIFT 3
207#define CSR_PRMD_PWE (_ULCAST_(0x1) << CSR_PRMD_PWE_SHIFT)
208#define CSR_PRMD_PIE_SHIFT 2
209#define CSR_PRMD_PIE (_ULCAST_(0x1) << CSR_PRMD_PIE_SHIFT)
210#define CSR_PRMD_PPLV_SHIFT 0
211#define CSR_PRMD_PPLV_WIDTH 2
212#define CSR_PRMD_PPLV (_ULCAST_(0x3) << CSR_PRMD_PPLV_SHIFT)
213
214#define LOONGARCH_CSR_EUEN 0x2 /* Extended unit enable */
215#define CSR_EUEN_LBTEN_SHIFT 3
216#define CSR_EUEN_LBTEN (_ULCAST_(0x1) << CSR_EUEN_LBTEN_SHIFT)
217#define CSR_EUEN_LASXEN_SHIFT 2
218#define CSR_EUEN_LASXEN (_ULCAST_(0x1) << CSR_EUEN_LASXEN_SHIFT)
219#define CSR_EUEN_LSXEN_SHIFT 1
220#define CSR_EUEN_LSXEN (_ULCAST_(0x1) << CSR_EUEN_LSXEN_SHIFT)
221#define CSR_EUEN_FPEN_SHIFT 0
222#define CSR_EUEN_FPEN (_ULCAST_(0x1) << CSR_EUEN_FPEN_SHIFT)
223
224#define LOONGARCH_CSR_MISC 0x3 /* Misc config */
225
226#define LOONGARCH_CSR_ECFG 0x4 /* Exception config */
227#define CSR_ECFG_VS_SHIFT 16
228#define CSR_ECFG_VS_WIDTH 3
229#define CSR_ECFG_VS_SHIFT_END (CSR_ECFG_VS_SHIFT + CSR_ECFG_VS_WIDTH - 1)
230#define CSR_ECFG_VS (_ULCAST_(0x7) << CSR_ECFG_VS_SHIFT)
231#define CSR_ECFG_IM_SHIFT 0
232#define CSR_ECFG_IM_WIDTH 14
233#define CSR_ECFG_IM (_ULCAST_(0x3fff) << CSR_ECFG_IM_SHIFT)
234
235#define LOONGARCH_CSR_ESTAT 0x5 /* Exception status */
236#define CSR_ESTAT_ESUBCODE_SHIFT 22
237#define CSR_ESTAT_ESUBCODE_WIDTH 9
238#define CSR_ESTAT_ESUBCODE (_ULCAST_(0x1ff) << CSR_ESTAT_ESUBCODE_SHIFT)
239#define CSR_ESTAT_EXC_SHIFT 16
240#define CSR_ESTAT_EXC_WIDTH 6
241#define CSR_ESTAT_EXC (_ULCAST_(0x3f) << CSR_ESTAT_EXC_SHIFT)
242#define CSR_ESTAT_IS_SHIFT 0
243#define CSR_ESTAT_IS_WIDTH 14
244#define CSR_ESTAT_IS (_ULCAST_(0x3fff) << CSR_ESTAT_IS_SHIFT)
245
246#define LOONGARCH_CSR_ERA 0x6 /* ERA */
247
248#define LOONGARCH_CSR_BADV 0x7 /* Bad virtual address */
249
250#define LOONGARCH_CSR_BADI 0x8 /* Bad instruction */
251
252#define LOONGARCH_CSR_EENTRY 0xc /* Exception entry */
253
254/* TLB related CSR registers */
255#define LOONGARCH_CSR_TLBIDX 0x10 /* TLB Index, EHINV, PageSize, NP */
256#define CSR_TLBIDX_EHINV_SHIFT 31
257#define CSR_TLBIDX_EHINV (_ULCAST_(1) << CSR_TLBIDX_EHINV_SHIFT)
258#define CSR_TLBIDX_PS_SHIFT 24
259#define CSR_TLBIDX_PS_WIDTH 6
260#define CSR_TLBIDX_PS (_ULCAST_(0x3f) << CSR_TLBIDX_PS_SHIFT)
261#define CSR_TLBIDX_IDX_SHIFT 0
262#define CSR_TLBIDX_IDX_WIDTH 12
263#define CSR_TLBIDX_IDX (_ULCAST_(0xfff) << CSR_TLBIDX_IDX_SHIFT)
264#define CSR_TLBIDX_SIZEM 0x3f000000
265#define CSR_TLBIDX_SIZE CSR_TLBIDX_PS_SHIFT
266#define CSR_TLBIDX_IDXM 0xfff
267#define CSR_INVALID_ENTRY(e) (CSR_TLBIDX_EHINV | e)
268
269#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
270
271#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
272#define CSR_TLBLO0_RPLV_SHIFT 63
273#define CSR_TLBLO0_RPLV (_ULCAST_(0x1) << CSR_TLBLO0_RPLV_SHIFT)
274#define CSR_TLBLO0_NX_SHIFT 62
275#define CSR_TLBLO0_NX (_ULCAST_(0x1) << CSR_TLBLO0_NX_SHIFT)
276#define CSR_TLBLO0_NR_SHIFT 61
277#define CSR_TLBLO0_NR (_ULCAST_(0x1) << CSR_TLBLO0_NR_SHIFT)
278#define CSR_TLBLO0_PFN_SHIFT 12
279#define CSR_TLBLO0_PFN_WIDTH 36
280#define CSR_TLBLO0_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO0_PFN_SHIFT)
281#define CSR_TLBLO0_GLOBAL_SHIFT 6
282#define CSR_TLBLO0_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO0_GLOBAL_SHIFT)
283#define CSR_TLBLO0_CCA_SHIFT 4
284#define CSR_TLBLO0_CCA_WIDTH 2
285#define CSR_TLBLO0_CCA (_ULCAST_(0x3) << CSR_TLBLO0_CCA_SHIFT)
286#define CSR_TLBLO0_PLV_SHIFT 2
287#define CSR_TLBLO0_PLV_WIDTH 2
288#define CSR_TLBLO0_PLV (_ULCAST_(0x3) << CSR_TLBLO0_PLV_SHIFT)
289#define CSR_TLBLO0_WE_SHIFT 1
290#define CSR_TLBLO0_WE (_ULCAST_(0x1) << CSR_TLBLO0_WE_SHIFT)
291#define CSR_TLBLO0_V_SHIFT 0
292#define CSR_TLBLO0_V (_ULCAST_(0x1) << CSR_TLBLO0_V_SHIFT)
293
294#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
295#define CSR_TLBLO1_RPLV_SHIFT 63
296#define CSR_TLBLO1_RPLV (_ULCAST_(0x1) << CSR_TLBLO1_RPLV_SHIFT)
297#define CSR_TLBLO1_NX_SHIFT 62
298#define CSR_TLBLO1_NX (_ULCAST_(0x1) << CSR_TLBLO1_NX_SHIFT)
299#define CSR_TLBLO1_NR_SHIFT 61
300#define CSR_TLBLO1_NR (_ULCAST_(0x1) << CSR_TLBLO1_NR_SHIFT)
301#define CSR_TLBLO1_PFN_SHIFT 12
302#define CSR_TLBLO1_PFN_WIDTH 36
303#define CSR_TLBLO1_PFN (_ULCAST_(0xfffffffff) << CSR_TLBLO1_PFN_SHIFT)
304#define CSR_TLBLO1_GLOBAL_SHIFT 6
305#define CSR_TLBLO1_GLOBAL (_ULCAST_(0x1) << CSR_TLBLO1_GLOBAL_SHIFT)
306#define CSR_TLBLO1_CCA_SHIFT 4
307#define CSR_TLBLO1_CCA_WIDTH 2
308#define CSR_TLBLO1_CCA (_ULCAST_(0x3) << CSR_TLBLO1_CCA_SHIFT)
309#define CSR_TLBLO1_PLV_SHIFT 2
310#define CSR_TLBLO1_PLV_WIDTH 2
311#define CSR_TLBLO1_PLV (_ULCAST_(0x3) << CSR_TLBLO1_PLV_SHIFT)
312#define CSR_TLBLO1_WE_SHIFT 1
313#define CSR_TLBLO1_WE (_ULCAST_(0x1) << CSR_TLBLO1_WE_SHIFT)
314#define CSR_TLBLO1_V_SHIFT 0
315#define CSR_TLBLO1_V (_ULCAST_(0x1) << CSR_TLBLO1_V_SHIFT)
316
317#define LOONGARCH_CSR_GTLBC 0x15 /* Guest TLB control */
318#define CSR_GTLBC_TGID_SHIFT 16
319#define CSR_GTLBC_TGID_WIDTH 8
320#define CSR_GTLBC_TGID_SHIFT_END (CSR_GTLBC_TGID_SHIFT + CSR_GTLBC_TGID_WIDTH - 1)
321#define CSR_GTLBC_TGID (_ULCAST_(0xff) << CSR_GTLBC_TGID_SHIFT)
322#define CSR_GTLBC_TOTI_SHIFT 13
323#define CSR_GTLBC_TOTI (_ULCAST_(0x1) << CSR_GTLBC_TOTI_SHIFT)
324#define CSR_GTLBC_USETGID_SHIFT 12
325#define CSR_GTLBC_USETGID (_ULCAST_(0x1) << CSR_GTLBC_USETGID_SHIFT)
326#define CSR_GTLBC_GMTLBSZ_SHIFT 0
327#define CSR_GTLBC_GMTLBSZ_WIDTH 6
328#define CSR_GTLBC_GMTLBSZ (_ULCAST_(0x3f) << CSR_GTLBC_GMTLBSZ_SHIFT)
329
330#define LOONGARCH_CSR_TRGP 0x16 /* TLBR read guest info */
331#define CSR_TRGP_RID_SHIFT 16
332#define CSR_TRGP_RID_WIDTH 8
333#define CSR_TRGP_RID (_ULCAST_(0xff) << CSR_TRGP_RID_SHIFT)
334#define CSR_TRGP_GTLB_SHIFT 0
335#define CSR_TRGP_GTLB (1 << CSR_TRGP_GTLB_SHIFT)
336
337#define LOONGARCH_CSR_ASID 0x18 /* ASID */
338#define CSR_ASID_BIT_SHIFT 16 /* ASIDBits */
339#define CSR_ASID_BIT_WIDTH 8
340#define CSR_ASID_BIT (_ULCAST_(0xff) << CSR_ASID_BIT_SHIFT)
341#define CSR_ASID_ASID_SHIFT 0
342#define CSR_ASID_ASID_WIDTH 10
343#define CSR_ASID_ASID (_ULCAST_(0x3ff) << CSR_ASID_ASID_SHIFT)
344
345#define LOONGARCH_CSR_PGDL 0x19 /* Page table base address when VA[VALEN-1] = 0 */
346
347#define LOONGARCH_CSR_PGDH 0x1a /* Page table base address when VA[VALEN-1] = 1 */
348
349#define LOONGARCH_CSR_PGD 0x1b /* Page table base */
350
351#define LOONGARCH_CSR_PWCTL0 0x1c /* PWCtl0 */
352#define CSR_PWCTL0_PTEW_SHIFT 30
353#define CSR_PWCTL0_PTEW_WIDTH 2
354#define CSR_PWCTL0_PTEW (_ULCAST_(0x3) << CSR_PWCTL0_PTEW_SHIFT)
355#define CSR_PWCTL0_DIR1WIDTH_SHIFT 25
356#define CSR_PWCTL0_DIR1WIDTH_WIDTH 5
357#define CSR_PWCTL0_DIR1WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1WIDTH_SHIFT)
358#define CSR_PWCTL0_DIR1BASE_SHIFT 20
359#define CSR_PWCTL0_DIR1BASE_WIDTH 5
360#define CSR_PWCTL0_DIR1BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR1BASE_SHIFT)
361#define CSR_PWCTL0_DIR0WIDTH_SHIFT 15
362#define CSR_PWCTL0_DIR0WIDTH_WIDTH 5
363#define CSR_PWCTL0_DIR0WIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0WIDTH_SHIFT)
364#define CSR_PWCTL0_DIR0BASE_SHIFT 10
365#define CSR_PWCTL0_DIR0BASE_WIDTH 5
366#define CSR_PWCTL0_DIR0BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR0BASE_SHIFT)
367#define CSR_PWCTL0_PTWIDTH_SHIFT 5
368#define CSR_PWCTL0_PTWIDTH_WIDTH 5
369#define CSR_PWCTL0_PTWIDTH (_ULCAST_(0x1f) << CSR_PWCTL0_PTWIDTH_SHIFT)
370#define CSR_PWCTL0_PTBASE_SHIFT 0
371#define CSR_PWCTL0_PTBASE_WIDTH 5
372#define CSR_PWCTL0_PTBASE (_ULCAST_(0x1f) << CSR_PWCTL0_PTBASE_SHIFT)
373
374#define LOONGARCH_CSR_PWCTL1 0x1d /* PWCtl1 */
375#define CSR_PWCTL1_PTW_SHIFT 24
376#define CSR_PWCTL1_PTW_WIDTH 1
377#define CSR_PWCTL1_PTW (_ULCAST_(0x1) << CSR_PWCTL1_PTW_SHIFT)
378#define CSR_PWCTL1_DIR3WIDTH_SHIFT 18
379#define CSR_PWCTL1_DIR3WIDTH_WIDTH 5
380#define CSR_PWCTL1_DIR3WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR3WIDTH_SHIFT)
381#define CSR_PWCTL1_DIR3BASE_SHIFT 12
382#define CSR_PWCTL1_DIR3BASE_WIDTH 5
383#define CSR_PWCTL1_DIR3BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR3BASE_SHIFT)
384#define CSR_PWCTL1_DIR2WIDTH_SHIFT 6
385#define CSR_PWCTL1_DIR2WIDTH_WIDTH 5
386#define CSR_PWCTL1_DIR2WIDTH (_ULCAST_(0x1f) << CSR_PWCTL1_DIR2WIDTH_SHIFT)
387#define CSR_PWCTL1_DIR2BASE_SHIFT 0
388#define CSR_PWCTL1_DIR2BASE_WIDTH 5
389#define CSR_PWCTL1_DIR2BASE (_ULCAST_(0x1f) << CSR_PWCTL0_DIR2BASE_SHIFT)
390
391#define LOONGARCH_CSR_STLBPGSIZE 0x1e
392#define CSR_STLBPGSIZE_PS_WIDTH 6
393#define CSR_STLBPGSIZE_PS (_ULCAST_(0x3f))
394
395#define LOONGARCH_CSR_RVACFG 0x1f
396#define CSR_RVACFG_RDVA_WIDTH 4
397#define CSR_RVACFG_RDVA (_ULCAST_(0xf))
398
399/* Config CSR registers */
400#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
401#define CSR_CPUID_COREID_WIDTH 9
402#define CSR_CPUID_COREID _ULCAST_(0x1ff)
403
404#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
405#define CSR_CONF1_VSMAX_SHIFT 12
406#define CSR_CONF1_VSMAX_WIDTH 3
407#define CSR_CONF1_VSMAX (_ULCAST_(7) << CSR_CONF1_VSMAX_SHIFT)
408#define CSR_CONF1_TMRBITS_SHIFT 4
409#define CSR_CONF1_TMRBITS_WIDTH 8
410#define CSR_CONF1_TMRBITS (_ULCAST_(0xff) << CSR_CONF1_TMRBITS_SHIFT)
411#define CSR_CONF1_KSNUM_WIDTH 4
412#define CSR_CONF1_KSNUM _ULCAST_(0xf)
413
414#define LOONGARCH_CSR_PRCFG2 0x22 /* Config2 */
415#define CSR_CONF2_PGMASK_SUPP 0x3ffff000
416
417#define LOONGARCH_CSR_PRCFG3 0x23 /* Config3 */
418#define CSR_CONF3_STLBIDX_SHIFT 20
419#define CSR_CONF3_STLBIDX_WIDTH 6
420#define CSR_CONF3_STLBIDX (_ULCAST_(0x3f) << CSR_CONF3_STLBIDX_SHIFT)
421#define CSR_CONF3_STLBWAYS_SHIFT 12
422#define CSR_CONF3_STLBWAYS_WIDTH 8
423#define CSR_CONF3_STLBWAYS (_ULCAST_(0xff) << CSR_CONF3_STLBWAYS_SHIFT)
424#define CSR_CONF3_MTLBSIZE_SHIFT 4
425#define CSR_CONF3_MTLBSIZE_WIDTH 8
426#define CSR_CONF3_MTLBSIZE (_ULCAST_(0xff) << CSR_CONF3_MTLBSIZE_SHIFT)
427#define CSR_CONF3_TLBTYPE_SHIFT 0
428#define CSR_CONF3_TLBTYPE_WIDTH 4
429#define CSR_CONF3_TLBTYPE (_ULCAST_(0xf) << CSR_CONF3_TLBTYPE_SHIFT)
430
431/* KSave registers */
432#define LOONGARCH_CSR_KS0 0x30
433#define LOONGARCH_CSR_KS1 0x31
434#define LOONGARCH_CSR_KS2 0x32
435#define LOONGARCH_CSR_KS3 0x33
436#define LOONGARCH_CSR_KS4 0x34
437#define LOONGARCH_CSR_KS5 0x35
438#define LOONGARCH_CSR_KS6 0x36
439#define LOONGARCH_CSR_KS7 0x37
440#define LOONGARCH_CSR_KS8 0x38
441
442/* Exception allocated KS0, KS1 and KS2 statically */
443#define EXCEPTION_KS0 LOONGARCH_CSR_KS0
444#define EXCEPTION_KS1 LOONGARCH_CSR_KS1
445#define EXCEPTION_KS2 LOONGARCH_CSR_KS2
446#define EXC_KSAVE_MASK (1 << 0 | 1 << 1 | 1 << 2)
447
448/* Percpu-data base allocated KS3 statically */
449#define PERCPU_BASE_KS LOONGARCH_CSR_KS3
450#define PERCPU_KSAVE_MASK (1 << 3)
451
452/* KVM allocated KS4 and KS5 statically */
453#define KVM_VCPU_KS LOONGARCH_CSR_KS4
454#define KVM_TEMP_KS LOONGARCH_CSR_KS5
455#define KVM_KSAVE_MASK (1 << 4 | 1 << 5)
456
457/* Timer registers */
458#define LOONGARCH_CSR_TMID 0x40 /* Timer ID */
459
460#define LOONGARCH_CSR_TCFG 0x41 /* Timer config */
461#define CSR_TCFG_VAL_SHIFT 2
462#define CSR_TCFG_VAL_WIDTH 48
463#define CSR_TCFG_VAL (_ULCAST_(0x3fffffffffff) << CSR_TCFG_VAL_SHIFT)
464#define CSR_TCFG_PERIOD_SHIFT 1
465#define CSR_TCFG_PERIOD (_ULCAST_(0x1) << CSR_TCFG_PERIOD_SHIFT)
466#define CSR_TCFG_EN (_ULCAST_(0x1))
467
468#define LOONGARCH_CSR_TVAL 0x42 /* Timer value */
469
470#define LOONGARCH_CSR_CNTC 0x43 /* Timer offset */
471
472#define LOONGARCH_CSR_TINTCLR 0x44 /* Timer interrupt clear */
473#define CSR_TINTCLR_TI_SHIFT 0
474#define CSR_TINTCLR_TI (1 << CSR_TINTCLR_TI_SHIFT)
475
476/* Guest registers */
477#define LOONGARCH_CSR_GSTAT 0x50 /* Guest status */
478#define CSR_GSTAT_GID_SHIFT 16
479#define CSR_GSTAT_GID_WIDTH 8
480#define CSR_GSTAT_GID_SHIFT_END (CSR_GSTAT_GID_SHIFT + CSR_GSTAT_GID_WIDTH - 1)
481#define CSR_GSTAT_GID (_ULCAST_(0xff) << CSR_GSTAT_GID_SHIFT)
482#define CSR_GSTAT_GIDBIT_SHIFT 4
483#define CSR_GSTAT_GIDBIT_WIDTH 6
484#define CSR_GSTAT_GIDBIT (_ULCAST_(0x3f) << CSR_GSTAT_GIDBIT_SHIFT)
485#define CSR_GSTAT_PVM_SHIFT 1
486#define CSR_GSTAT_PVM (_ULCAST_(0x1) << CSR_GSTAT_PVM_SHIFT)
487#define CSR_GSTAT_VM_SHIFT 0
488#define CSR_GSTAT_VM (_ULCAST_(0x1) << CSR_GSTAT_VM_SHIFT)
489
490#define LOONGARCH_CSR_GCFG 0x51 /* Guest config */
491#define CSR_GCFG_GPERF_SHIFT 24
492#define CSR_GCFG_GPERF_WIDTH 3
493#define CSR_GCFG_GPERF (_ULCAST_(0x7) << CSR_GCFG_GPERF_SHIFT)
494#define CSR_GCFG_GCI_SHIFT 20
495#define CSR_GCFG_GCI_WIDTH 2
496#define CSR_GCFG_GCI (_ULCAST_(0x3) << CSR_GCFG_GCI_SHIFT)
497#define CSR_GCFG_GCI_ALL (_ULCAST_(0x0) << CSR_GCFG_GCI_SHIFT)
498#define CSR_GCFG_GCI_HIT (_ULCAST_(0x1) << CSR_GCFG_GCI_SHIFT)
499#define CSR_GCFG_GCI_SECURE (_ULCAST_(0x2) << CSR_GCFG_GCI_SHIFT)
500#define CSR_GCFG_GCIP_SHIFT 16
501#define CSR_GCFG_GCIP (_ULCAST_(0xf) << CSR_GCFG_GCIP_SHIFT)
502#define CSR_GCFG_GCIP_ALL (_ULCAST_(0x1) << CSR_GCFG_GCIP_SHIFT)
503#define CSR_GCFG_GCIP_HIT (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 1))
504#define CSR_GCFG_GCIP_SECURE (_ULCAST_(0x1) << (CSR_GCFG_GCIP_SHIFT + 2))
505#define CSR_GCFG_TORU_SHIFT 15
506#define CSR_GCFG_TORU (_ULCAST_(0x1) << CSR_GCFG_TORU_SHIFT)
507#define CSR_GCFG_TORUP_SHIFT 14
508#define CSR_GCFG_TORUP (_ULCAST_(0x1) << CSR_GCFG_TORUP_SHIFT)
509#define CSR_GCFG_TOP_SHIFT 13
510#define CSR_GCFG_TOP (_ULCAST_(0x1) << CSR_GCFG_TOP_SHIFT)
511#define CSR_GCFG_TOPP_SHIFT 12
512#define CSR_GCFG_TOPP (_ULCAST_(0x1) << CSR_GCFG_TOPP_SHIFT)
513#define CSR_GCFG_TOE_SHIFT 11
514#define CSR_GCFG_TOE (_ULCAST_(0x1) << CSR_GCFG_TOE_SHIFT)
515#define CSR_GCFG_TOEP_SHIFT 10
516#define CSR_GCFG_TOEP (_ULCAST_(0x1) << CSR_GCFG_TOEP_SHIFT)
517#define CSR_GCFG_TIT_SHIFT 9
518#define CSR_GCFG_TIT (_ULCAST_(0x1) << CSR_GCFG_TIT_SHIFT)
519#define CSR_GCFG_TITP_SHIFT 8
520#define CSR_GCFG_TITP (_ULCAST_(0x1) << CSR_GCFG_TITP_SHIFT)
521#define CSR_GCFG_SIT_SHIFT 7
522#define CSR_GCFG_SIT (_ULCAST_(0x1) << CSR_GCFG_SIT_SHIFT)
523#define CSR_GCFG_SITP_SHIFT 6
524#define CSR_GCFG_SITP (_ULCAST_(0x1) << CSR_GCFG_SITP_SHIFT)
525#define CSR_GCFG_MATC_SHITF 4
526#define CSR_GCFG_MATC_WIDTH 2
527#define CSR_GCFG_MATC_MASK (_ULCAST_(0x3) << CSR_GCFG_MATC_SHITF)
528#define CSR_GCFG_MATC_GUEST (_ULCAST_(0x0) << CSR_GCFG_MATC_SHITF)
529#define CSR_GCFG_MATC_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATC_SHITF)
530#define CSR_GCFG_MATC_NEST (_ULCAST_(0x2) << CSR_GCFG_MATC_SHITF)
531#define CSR_GCFG_MATP_NEST_SHIFT 2
532#define CSR_GCFG_MATP_NEST (_ULCAST_(0x1) << CSR_GCFG_MATP_NEST_SHIFT)
533#define CSR_GCFG_MATP_ROOT_SHIFT 1
534#define CSR_GCFG_MATP_ROOT (_ULCAST_(0x1) << CSR_GCFG_MATP_ROOT_SHIFT)
535#define CSR_GCFG_MATP_GUEST_SHIFT 0
536#define CSR_GCFG_MATP_GUEST (_ULCAST_(0x1) << CSR_GCFG_MATP_GUEST_SHIFT)
537
538#define LOONGARCH_CSR_GINTC 0x52 /* Guest interrupt control */
539#define CSR_GINTC_HC_SHIFT 16
540#define CSR_GINTC_HC_WIDTH 8
541#define CSR_GINTC_HC (_ULCAST_(0xff) << CSR_GINTC_HC_SHIFT)
542#define CSR_GINTC_PIP_SHIFT 8
543#define CSR_GINTC_PIP_WIDTH 8
544#define CSR_GINTC_PIP (_ULCAST_(0xff) << CSR_GINTC_PIP_SHIFT)
545#define CSR_GINTC_VIP_SHIFT 0
546#define CSR_GINTC_VIP_WIDTH 8
547#define CSR_GINTC_VIP (_ULCAST_(0xff))
548
549#define LOONGARCH_CSR_GCNTC 0x53 /* Guest timer offset */
550
551/* LLBCTL register */
552#define LOONGARCH_CSR_LLBCTL 0x60 /* LLBit control */
553#define CSR_LLBCTL_ROLLB_SHIFT 0
554#define CSR_LLBCTL_ROLLB (_ULCAST_(1) << CSR_LLBCTL_ROLLB_SHIFT)
555#define CSR_LLBCTL_WCLLB_SHIFT 1
556#define CSR_LLBCTL_WCLLB (_ULCAST_(1) << CSR_LLBCTL_WCLLB_SHIFT)
557#define CSR_LLBCTL_KLO_SHIFT 2
558#define CSR_LLBCTL_KLO (_ULCAST_(1) << CSR_LLBCTL_KLO_SHIFT)
559
560/* Implement dependent */
561#define LOONGARCH_CSR_IMPCTL1 0x80 /* Loongson config1 */
562#define CSR_MISPEC_SHIFT 20
563#define CSR_MISPEC_WIDTH 8
564#define CSR_MISPEC (_ULCAST_(0xff) << CSR_MISPEC_SHIFT)
565#define CSR_SSEN_SHIFT 18
566#define CSR_SSEN (_ULCAST_(1) << CSR_SSEN_SHIFT)
567#define CSR_SCRAND_SHIFT 17
568#define CSR_SCRAND (_ULCAST_(1) << CSR_SCRAND_SHIFT)
569#define CSR_LLEXCL_SHIFT 16
570#define CSR_LLEXCL (_ULCAST_(1) << CSR_LLEXCL_SHIFT)
571#define CSR_DISVC_SHIFT 15
572#define CSR_DISVC (_ULCAST_(1) << CSR_DISVC_SHIFT)
573#define CSR_VCLRU_SHIFT 14
574#define CSR_VCLRU (_ULCAST_(1) << CSR_VCLRU_SHIFT)
575#define CSR_DCLRU_SHIFT 13
576#define CSR_DCLRU (_ULCAST_(1) << CSR_DCLRU_SHIFT)
577#define CSR_FASTLDQ_SHIFT 12
578#define CSR_FASTLDQ (_ULCAST_(1) << CSR_FASTLDQ_SHIFT)
579#define CSR_USERCAC_SHIFT 11
580#define CSR_USERCAC (_ULCAST_(1) << CSR_USERCAC_SHIFT)
581#define CSR_ANTI_MISPEC_SHIFT 10
582#define CSR_ANTI_MISPEC (_ULCAST_(1) << CSR_ANTI_MISPEC_SHIFT)
583#define CSR_AUTO_FLUSHSFB_SHIFT 9
584#define CSR_AUTO_FLUSHSFB (_ULCAST_(1) << CSR_AUTO_FLUSHSFB_SHIFT)
585#define CSR_STFILL_SHIFT 8
586#define CSR_STFILL (_ULCAST_(1) << CSR_STFILL_SHIFT)
587#define CSR_LIFEP_SHIFT 7
588#define CSR_LIFEP (_ULCAST_(1) << CSR_LIFEP_SHIFT)
589#define CSR_LLSYNC_SHIFT 6
590#define CSR_LLSYNC (_ULCAST_(1) << CSR_LLSYNC_SHIFT)
591#define CSR_BRBTDIS_SHIFT 5
592#define CSR_BRBTDIS (_ULCAST_(1) << CSR_BRBTDIS_SHIFT)
593#define CSR_RASDIS_SHIFT 4
594#define CSR_RASDIS (_ULCAST_(1) << CSR_RASDIS_SHIFT)
595#define CSR_STPRE_SHIFT 2
596#define CSR_STPRE_WIDTH 2
597#define CSR_STPRE (_ULCAST_(3) << CSR_STPRE_SHIFT)
598#define CSR_INSTPRE_SHIFT 1
599#define CSR_INSTPRE (_ULCAST_(1) << CSR_INSTPRE_SHIFT)
600#define CSR_DATAPRE_SHIFT 0
601#define CSR_DATAPRE (_ULCAST_(1) << CSR_DATAPRE_SHIFT)
602
603#define LOONGARCH_CSR_IMPCTL2 0x81 /* Loongson config2 */
604#define CSR_FLUSH_MTLB_SHIFT 0
605#define CSR_FLUSH_MTLB (_ULCAST_(1) << CSR_FLUSH_MTLB_SHIFT)
606#define CSR_FLUSH_STLB_SHIFT 1
607#define CSR_FLUSH_STLB (_ULCAST_(1) << CSR_FLUSH_STLB_SHIFT)
608#define CSR_FLUSH_DTLB_SHIFT 2
609#define CSR_FLUSH_DTLB (_ULCAST_(1) << CSR_FLUSH_DTLB_SHIFT)
610#define CSR_FLUSH_ITLB_SHIFT 3
611#define CSR_FLUSH_ITLB (_ULCAST_(1) << CSR_FLUSH_ITLB_SHIFT)
612#define CSR_FLUSH_BTAC_SHIFT 4
613#define CSR_FLUSH_BTAC (_ULCAST_(1) << CSR_FLUSH_BTAC_SHIFT)
614
615#define LOONGARCH_CSR_GNMI 0x82
616
617/* TLB Refill registers */
618#define LOONGARCH_CSR_TLBRENTRY 0x88 /* TLB refill exception entry */
619#define LOONGARCH_CSR_TLBRBADV 0x89 /* TLB refill badvaddr */
620#define LOONGARCH_CSR_TLBRERA 0x8a /* TLB refill ERA */
621#define LOONGARCH_CSR_TLBRSAVE 0x8b /* KSave for TLB refill exception */
622#define LOONGARCH_CSR_TLBRELO0 0x8c /* TLB refill entrylo0 */
623#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
624#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
625#define CSR_TLBREHI_PS_SHIFT 0
626#define CSR_TLBREHI_PS (_ULCAST_(0x3f) << CSR_TLBREHI_PS_SHIFT)
627#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
628
629/* Machine Error registers */
630#define LOONGARCH_CSR_MERRCTL 0x90 /* MERRCTL */
631#define LOONGARCH_CSR_MERRINFO1 0x91 /* MError info1 */
632#define LOONGARCH_CSR_MERRINFO2 0x92 /* MError info2 */
633#define LOONGARCH_CSR_MERRENTRY 0x93 /* MError exception entry */
634#define LOONGARCH_CSR_MERRERA 0x94 /* MError exception ERA */
635#define LOONGARCH_CSR_MERRSAVE 0x95 /* KSave for machine error exception */
636
637#define LOONGARCH_CSR_CTAG 0x98 /* TagLo + TagHi */
638
639#define LOONGARCH_CSR_PRID 0xc0
640
641/* Shadow MCSR : 0xc0 ~ 0xff */
642#define LOONGARCH_CSR_MCSR0 0xc0 /* CPUCFG0 and CPUCFG1 */
643#define MCSR0_INT_IMPL_SHIFT 58
644#define MCSR0_INT_IMPL 0
645#define MCSR0_IOCSR_BRD_SHIFT 57
646#define MCSR0_IOCSR_BRD (_ULCAST_(1) << MCSR0_IOCSR_BRD_SHIFT)
647#define MCSR0_HUGEPG_SHIFT 56
648#define MCSR0_HUGEPG (_ULCAST_(1) << MCSR0_HUGEPG_SHIFT)
649#define MCSR0_RPLMTLB_SHIFT 55
650#define MCSR0_RPLMTLB (_ULCAST_(1) << MCSR0_RPLMTLB_SHIFT)
651#define MCSR0_EP_SHIFT 54
652#define MCSR0_EP (_ULCAST_(1) << MCSR0_EP_SHIFT)
653#define MCSR0_RI_SHIFT 53
654#define MCSR0_RI (_ULCAST_(1) << MCSR0_RI_SHIFT)
655#define MCSR0_UAL_SHIFT 52
656#define MCSR0_UAL (_ULCAST_(1) << MCSR0_UAL_SHIFT)
657#define MCSR0_VABIT_SHIFT 44
658#define MCSR0_VABIT_WIDTH 8
659#define MCSR0_VABIT (_ULCAST_(0xff) << MCSR0_VABIT_SHIFT)
660#define VABIT_DEFAULT 0x2f
661#define MCSR0_PABIT_SHIFT 36
662#define MCSR0_PABIT_WIDTH 8
663#define MCSR0_PABIT (_ULCAST_(0xff) << MCSR0_PABIT_SHIFT)
664#define PABIT_DEFAULT 0x2f
665#define MCSR0_IOCSR_SHIFT 35
666#define MCSR0_IOCSR (_ULCAST_(1) << MCSR0_IOCSR_SHIFT)
667#define MCSR0_PAGING_SHIFT 34
668#define MCSR0_PAGING (_ULCAST_(1) << MCSR0_PAGING_SHIFT)
669#define MCSR0_GR64_SHIFT 33
670#define MCSR0_GR64 (_ULCAST_(1) << MCSR0_GR64_SHIFT)
671#define GR64_DEFAULT 1
672#define MCSR0_GR32_SHIFT 32
673#define MCSR0_GR32 (_ULCAST_(1) << MCSR0_GR32_SHIFT)
674#define GR32_DEFAULT 0
675#define MCSR0_PRID_WIDTH 32
676#define MCSR0_PRID 0x14C010
677
678#define LOONGARCH_CSR_MCSR1 0xc1 /* CPUCFG2 and CPUCFG3 */
679#define MCSR1_HPFOLD_SHIFT 43
680#define MCSR1_HPFOLD (_ULCAST_(1) << MCSR1_HPFOLD_SHIFT)
681#define MCSR1_SPW_LVL_SHIFT 40
682#define MCSR1_SPW_LVL_WIDTH 3
683#define MCSR1_SPW_LVL (_ULCAST_(7) << MCSR1_SPW_LVL_SHIFT)
684#define MCSR1_ICACHET_SHIFT 39
685#define MCSR1_ICACHET (_ULCAST_(1) << MCSR1_ICACHET_SHIFT)
686#define MCSR1_ITLBT_SHIFT 38
687#define MCSR1_ITLBT (_ULCAST_(1) << MCSR1_ITLBT_SHIFT)
688#define MCSR1_LLDBAR_SHIFT 37
689#define MCSR1_LLDBAR (_ULCAST_(1) << MCSR1_LLDBAR_SHIFT)
690#define MCSR1_SCDLY_SHIFT 36
691#define MCSR1_SCDLY (_ULCAST_(1) << MCSR1_SCDLY_SHIFT)
692#define MCSR1_LLEXC_SHIFT 35
693#define MCSR1_LLEXC (_ULCAST_(1) << MCSR1_LLEXC_SHIFT)
694#define MCSR1_UCACC_SHIFT 34
695#define MCSR1_UCACC (_ULCAST_(1) << MCSR1_UCACC_SHIFT)
696#define MCSR1_SFB_SHIFT 33
697#define MCSR1_SFB (_ULCAST_(1) << MCSR1_SFB_SHIFT)
698#define MCSR1_CCDMA_SHIFT 32
699#define MCSR1_CCDMA (_ULCAST_(1) << MCSR1_CCDMA_SHIFT)
700#define MCSR1_LAMO_SHIFT 22
701#define MCSR1_LAMO (_ULCAST_(1) << MCSR1_LAMO_SHIFT)
702#define MCSR1_LSPW_SHIFT 21
703#define MCSR1_LSPW (_ULCAST_(1) << MCSR1_LSPW_SHIFT)
704#define MCSR1_MIPSBT_SHIFT 20
705#define MCSR1_MIPSBT (_ULCAST_(1) << MCSR1_MIPSBT_SHIFT)
706#define MCSR1_ARMBT_SHIFT 19
707#define MCSR1_ARMBT (_ULCAST_(1) << MCSR1_ARMBT_SHIFT)
708#define MCSR1_X86BT_SHIFT 18
709#define MCSR1_X86BT (_ULCAST_(1) << MCSR1_X86BT_SHIFT)
710#define MCSR1_LLFTPVERS_SHIFT 15
711#define MCSR1_LLFTPVERS_WIDTH 3
712#define MCSR1_LLFTPVERS (_ULCAST_(7) << MCSR1_LLFTPVERS_SHIFT)
713#define MCSR1_LLFTP_SHIFT 14
714#define MCSR1_LLFTP (_ULCAST_(1) << MCSR1_LLFTP_SHIFT)
715#define MCSR1_VZVERS_SHIFT 11
716#define MCSR1_VZVERS_WIDTH 3
717#define MCSR1_VZVERS (_ULCAST_(7) << MCSR1_VZVERS_SHIFT)
718#define MCSR1_VZ_SHIFT 10
719#define MCSR1_VZ (_ULCAST_(1) << MCSR1_VZ_SHIFT)
720#define MCSR1_CRYPTO_SHIFT 9
721#define MCSR1_CRYPTO (_ULCAST_(1) << MCSR1_CRYPTO_SHIFT)
722#define MCSR1_COMPLEX_SHIFT 8
723#define MCSR1_COMPLEX (_ULCAST_(1) << MCSR1_COMPLEX_SHIFT)
724#define MCSR1_LASX_SHIFT 7
725#define MCSR1_LASX (_ULCAST_(1) << MCSR1_LASX_SHIFT)
726#define MCSR1_LSX_SHIFT 6
727#define MCSR1_LSX (_ULCAST_(1) << MCSR1_LSX_SHIFT)
728#define MCSR1_FPVERS_SHIFT 3
729#define MCSR1_FPVERS_WIDTH 3
730#define MCSR1_FPVERS (_ULCAST_(7) << MCSR1_FPVERS_SHIFT)
731#define MCSR1_FPDP_SHIFT 2
732#define MCSR1_FPDP (_ULCAST_(1) << MCSR1_FPDP_SHIFT)
733#define MCSR1_FPSP_SHIFT 1
734#define MCSR1_FPSP (_ULCAST_(1) << MCSR1_FPSP_SHIFT)
735#define MCSR1_FP_SHIFT 0
736#define MCSR1_FP (_ULCAST_(1) << MCSR1_FP_SHIFT)
737
738#define LOONGARCH_CSR_MCSR2 0xc2 /* CPUCFG4 and CPUCFG5 */
739#define MCSR2_CCDIV_SHIFT 48
740#define MCSR2_CCDIV_WIDTH 16
741#define MCSR2_CCDIV (_ULCAST_(0xffff) << MCSR2_CCDIV_SHIFT)
742#define MCSR2_CCMUL_SHIFT 32
743#define MCSR2_CCMUL_WIDTH 16
744#define MCSR2_CCMUL (_ULCAST_(0xffff) << MCSR2_CCMUL_SHIFT)
745#define MCSR2_CCFREQ_WIDTH 32
746#define MCSR2_CCFREQ (_ULCAST_(0xffffffff))
747#define CCFREQ_DEFAULT 0x5f5e100 /* 100MHz */
748
749#define LOONGARCH_CSR_MCSR3 0xc3 /* CPUCFG6 */
750#define MCSR3_UPM_SHIFT 14
751#define MCSR3_UPM (_ULCAST_(1) << MCSR3_UPM_SHIFT)
752#define MCSR3_PMBITS_SHIFT 8
753#define MCSR3_PMBITS_WIDTH 6
754#define MCSR3_PMBITS (_ULCAST_(0x3f) << MCSR3_PMBITS_SHIFT)
755#define PMBITS_DEFAULT 0x40
756#define MCSR3_PMNUM_SHIFT 4
757#define MCSR3_PMNUM_WIDTH 4
758#define MCSR3_PMNUM (_ULCAST_(0xf) << MCSR3_PMNUM_SHIFT)
759#define MCSR3_PAMVER_SHIFT 1
760#define MCSR3_PAMVER_WIDTH 3
761#define MCSR3_PAMVER (_ULCAST_(0x7) << MCSR3_PAMVER_SHIFT)
762#define MCSR3_PMP_SHIFT 0
763#define MCSR3_PMP (_ULCAST_(1) << MCSR3_PMP_SHIFT)
764
765#define LOONGARCH_CSR_MCSR8 0xc8 /* CPUCFG16 and CPUCFG17 */
766#define MCSR8_L1I_SIZE_SHIFT 56
767#define MCSR8_L1I_SIZE_WIDTH 7
768#define MCSR8_L1I_SIZE (_ULCAST_(0x7f) << MCSR8_L1I_SIZE_SHIFT)
769#define MCSR8_L1I_IDX_SHIFT 48
770#define MCSR8_L1I_IDX_WIDTH 8
771#define MCSR8_L1I_IDX (_ULCAST_(0xff) << MCSR8_L1I_IDX_SHIFT)
772#define MCSR8_L1I_WAY_SHIFT 32
773#define MCSR8_L1I_WAY_WIDTH 16
774#define MCSR8_L1I_WAY (_ULCAST_(0xffff) << MCSR8_L1I_WAY_SHIFT)
775#define MCSR8_L3DINCL_SHIFT 16
776#define MCSR8_L3DINCL (_ULCAST_(1) << MCSR8_L3DINCL_SHIFT)
777#define MCSR8_L3DPRIV_SHIFT 15
778#define MCSR8_L3DPRIV (_ULCAST_(1) << MCSR8_L3DPRIV_SHIFT)
779#define MCSR8_L3DPRE_SHIFT 14
780#define MCSR8_L3DPRE (_ULCAST_(1) << MCSR8_L3DPRE_SHIFT)
781#define MCSR8_L3IUINCL_SHIFT 13
782#define MCSR8_L3IUINCL (_ULCAST_(1) << MCSR8_L3IUINCL_SHIFT)
783#define MCSR8_L3IUPRIV_SHIFT 12
784#define MCSR8_L3IUPRIV (_ULCAST_(1) << MCSR8_L3IUPRIV_SHIFT)
785#define MCSR8_L3IUUNIFY_SHIFT 11
786#define MCSR8_L3IUUNIFY (_ULCAST_(1) << MCSR8_L3IUUNIFY_SHIFT)
787#define MCSR8_L3IUPRE_SHIFT 10
788#define MCSR8_L3IUPRE (_ULCAST_(1) << MCSR8_L3IUPRE_SHIFT)
789#define MCSR8_L2DINCL_SHIFT 9
790#define MCSR8_L2DINCL (_ULCAST_(1) << MCSR8_L2DINCL_SHIFT)
791#define MCSR8_L2DPRIV_SHIFT 8
792#define MCSR8_L2DPRIV (_ULCAST_(1) << MCSR8_L2DPRIV_SHIFT)
793#define MCSR8_L2DPRE_SHIFT 7
794#define MCSR8_L2DPRE (_ULCAST_(1) << MCSR8_L2DPRE_SHIFT)
795#define MCSR8_L2IUINCL_SHIFT 6
796#define MCSR8_L2IUINCL (_ULCAST_(1) << MCSR8_L2IUINCL_SHIFT)
797#define MCSR8_L2IUPRIV_SHIFT 5
798#define MCSR8_L2IUPRIV (_ULCAST_(1) << MCSR8_L2IUPRIV_SHIFT)
799#define MCSR8_L2IUUNIFY_SHIFT 4
800#define MCSR8_L2IUUNIFY (_ULCAST_(1) << MCSR8_L2IUUNIFY_SHIFT)
801#define MCSR8_L2IUPRE_SHIFT 3
802#define MCSR8_L2IUPRE (_ULCAST_(1) << MCSR8_L2IUPRE_SHIFT)
803#define MCSR8_L1DPRE_SHIFT 2
804#define MCSR8_L1DPRE (_ULCAST_(1) << MCSR8_L1DPRE_SHIFT)
805#define MCSR8_L1IUUNIFY_SHIFT 1
806#define MCSR8_L1IUUNIFY (_ULCAST_(1) << MCSR8_L1IUUNIFY_SHIFT)
807#define MCSR8_L1IUPRE_SHIFT 0
808#define MCSR8_L1IUPRE (_ULCAST_(1) << MCSR8_L1IUPRE_SHIFT)
809
810#define LOONGARCH_CSR_MCSR9 0xc9 /* CPUCFG18 and CPUCFG19 */
811#define MCSR9_L2U_SIZE_SHIFT 56
812#define MCSR9_L2U_SIZE_WIDTH 7
813#define MCSR9_L2U_SIZE (_ULCAST_(0x7f) << MCSR9_L2U_SIZE_SHIFT)
814#define MCSR9_L2U_IDX_SHIFT 48
815#define MCSR9_L2U_IDX_WIDTH 8
816#define MCSR9_L2U_IDX (_ULCAST_(0xff) << MCSR9_IDX_LOG_SHIFT)
817#define MCSR9_L2U_WAY_SHIFT 32
818#define MCSR9_L2U_WAY_WIDTH 16
819#define MCSR9_L2U_WAY (_ULCAST_(0xffff) << MCSR9_L2U_WAY_SHIFT)
820#define MCSR9_L1D_SIZE_SHIFT 24
821#define MCSR9_L1D_SIZE_WIDTH 7
822#define MCSR9_L1D_SIZE (_ULCAST_(0x7f) << MCSR9_L1D_SIZE_SHIFT)
823#define MCSR9_L1D_IDX_SHIFT 16
824#define MCSR9_L1D_IDX_WIDTH 8
825#define MCSR9_L1D_IDX (_ULCAST_(0xff) << MCSR9_L1D_IDX_SHIFT)
826#define MCSR9_L1D_WAY_SHIFT 0
827#define MCSR9_L1D_WAY_WIDTH 16
828#define MCSR9_L1D_WAY (_ULCAST_(0xffff) << MCSR9_L1D_WAY_SHIFT)
829
830#define LOONGARCH_CSR_MCSR10 0xca /* CPUCFG20 */
831#define MCSR10_L3U_SIZE_SHIFT 24
832#define MCSR10_L3U_SIZE_WIDTH 7
833#define MCSR10_L3U_SIZE (_ULCAST_(0x7f) << MCSR10_L3U_SIZE_SHIFT)
834#define MCSR10_L3U_IDX_SHIFT 16
835#define MCSR10_L3U_IDX_WIDTH 8
836#define MCSR10_L3U_IDX (_ULCAST_(0xff) << MCSR10_L3U_IDX_SHIFT)
837#define MCSR10_L3U_WAY_SHIFT 0
838#define MCSR10_L3U_WAY_WIDTH 16
839#define MCSR10_L3U_WAY (_ULCAST_(0xffff) << MCSR10_L3U_WAY_SHIFT)
840
841#define LOONGARCH_CSR_MCSR24 0xf0 /* cpucfg48 */
842#define MCSR24_RAMCG_SHIFT 3
843#define MCSR24_RAMCG (_ULCAST_(1) << MCSR24_RAMCG_SHIFT)
844#define MCSR24_VFPUCG_SHIFT 2
845#define MCSR24_VFPUCG (_ULCAST_(1) << MCSR24_VFPUCG_SHIFT)
846#define MCSR24_NAPEN_SHIFT 1
847#define MCSR24_NAPEN (_ULCAST_(1) << MCSR24_NAPEN_SHIFT)
848#define MCSR24_MCSRLOCK_SHIFT 0
849#define MCSR24_MCSRLOCK (_ULCAST_(1) << MCSR24_MCSRLOCK_SHIFT)
850
851/* Uncached accelerate windows registers */
852#define LOONGARCH_CSR_UCAWIN 0x100
853#define LOONGARCH_CSR_UCAWIN0_LO 0x102
854#define LOONGARCH_CSR_UCAWIN0_HI 0x103
855#define LOONGARCH_CSR_UCAWIN1_LO 0x104
856#define LOONGARCH_CSR_UCAWIN1_HI 0x105
857#define LOONGARCH_CSR_UCAWIN2_LO 0x106
858#define LOONGARCH_CSR_UCAWIN2_HI 0x107
859#define LOONGARCH_CSR_UCAWIN3_LO 0x108
860#define LOONGARCH_CSR_UCAWIN3_HI 0x109
861
862/* Direct Map windows registers */
863#define LOONGARCH_CSR_DMWIN0 0x180 /* 64 direct map win0: MEM & IF */
864#define LOONGARCH_CSR_DMWIN1 0x181 /* 64 direct map win1: MEM & IF */
865#define LOONGARCH_CSR_DMWIN2 0x182 /* 64 direct map win2: MEM */
866#define LOONGARCH_CSR_DMWIN3 0x183 /* 64 direct map win3: MEM */
867
868/* Direct Map window 0/1 */
869#define CSR_DMW0_PLV0 _CONST64_(1 << 0)
870#define CSR_DMW0_VSEG _CONST64_(0x8000)
871#define CSR_DMW0_BASE (CSR_DMW0_VSEG << DMW_PABITS)
872#define CSR_DMW0_INIT (CSR_DMW0_BASE | CSR_DMW0_PLV0)
873
874#define CSR_DMW1_PLV0 _CONST64_(1 << 0)
875#define CSR_DMW1_MAT _CONST64_(1 << 4)
876#define CSR_DMW1_VSEG _CONST64_(0x9000)
877#define CSR_DMW1_BASE (CSR_DMW1_VSEG << DMW_PABITS)
878#define CSR_DMW1_INIT (CSR_DMW1_BASE | CSR_DMW1_MAT | CSR_DMW1_PLV0)
879
880/* Performance Counter registers */
881#define LOONGARCH_CSR_PERFCTRL0 0x200 /* 32 perf event 0 config */
882#define LOONGARCH_CSR_PERFCNTR0 0x201 /* 64 perf event 0 count value */
883#define LOONGARCH_CSR_PERFCTRL1 0x202 /* 32 perf event 1 config */
884#define LOONGARCH_CSR_PERFCNTR1 0x203 /* 64 perf event 1 count value */
885#define LOONGARCH_CSR_PERFCTRL2 0x204 /* 32 perf event 2 config */
886#define LOONGARCH_CSR_PERFCNTR2 0x205 /* 64 perf event 2 count value */
887#define LOONGARCH_CSR_PERFCTRL3 0x206 /* 32 perf event 3 config */
888#define LOONGARCH_CSR_PERFCNTR3 0x207 /* 64 perf event 3 count value */
889#define CSR_PERFCTRL_PLV0 (_ULCAST_(1) << 16)
890#define CSR_PERFCTRL_PLV1 (_ULCAST_(1) << 17)
891#define CSR_PERFCTRL_PLV2 (_ULCAST_(1) << 18)
892#define CSR_PERFCTRL_PLV3 (_ULCAST_(1) << 19)
893#define CSR_PERFCTRL_IE (_ULCAST_(1) << 20)
894#define CSR_PERFCTRL_EVENT 0x3ff
895
896/* Debug registers */
897#define LOONGARCH_CSR_MWPC 0x300 /* data breakpoint config */
898#define LOONGARCH_CSR_MWPS 0x301 /* data breakpoint status */
899
900#define LOONGARCH_CSR_DB0ADDR 0x310 /* data breakpoint 0 address */
901#define LOONGARCH_CSR_DB0MASK 0x311 /* data breakpoint 0 mask */
902#define LOONGARCH_CSR_DB0CTRL 0x312 /* data breakpoint 0 control */
903#define LOONGARCH_CSR_DB0ASID 0x313 /* data breakpoint 0 asid */
904
905#define LOONGARCH_CSR_DB1ADDR 0x318 /* data breakpoint 1 address */
906#define LOONGARCH_CSR_DB1MASK 0x319 /* data breakpoint 1 mask */
907#define LOONGARCH_CSR_DB1CTRL 0x31a /* data breakpoint 1 control */
908#define LOONGARCH_CSR_DB1ASID 0x31b /* data breakpoint 1 asid */
909
910#define LOONGARCH_CSR_DB2ADDR 0x320 /* data breakpoint 2 address */
911#define LOONGARCH_CSR_DB2MASK 0x321 /* data breakpoint 2 mask */
912#define LOONGARCH_CSR_DB2CTRL 0x322 /* data breakpoint 2 control */
913#define LOONGARCH_CSR_DB2ASID 0x323 /* data breakpoint 2 asid */
914
915#define LOONGARCH_CSR_DB3ADDR 0x328 /* data breakpoint 3 address */
916#define LOONGARCH_CSR_DB3MASK 0x329 /* data breakpoint 3 mask */
917#define LOONGARCH_CSR_DB3CTRL 0x32a /* data breakpoint 3 control */
918#define LOONGARCH_CSR_DB3ASID 0x32b /* data breakpoint 3 asid */
919
920#define LOONGARCH_CSR_DB4ADDR 0x330 /* data breakpoint 4 address */
921#define LOONGARCH_CSR_DB4MASK 0x331 /* data breakpoint 4 maks */
922#define LOONGARCH_CSR_DB4CTRL 0x332 /* data breakpoint 4 control */
923#define LOONGARCH_CSR_DB4ASID 0x333 /* data breakpoint 4 asid */
924
925#define LOONGARCH_CSR_DB5ADDR 0x338 /* data breakpoint 5 address */
926#define LOONGARCH_CSR_DB5MASK 0x339 /* data breakpoint 5 mask */
927#define LOONGARCH_CSR_DB5CTRL 0x33a /* data breakpoint 5 control */
928#define LOONGARCH_CSR_DB5ASID 0x33b /* data breakpoint 5 asid */
929
930#define LOONGARCH_CSR_DB6ADDR 0x340 /* data breakpoint 6 address */
931#define LOONGARCH_CSR_DB6MASK 0x341 /* data breakpoint 6 mask */
932#define LOONGARCH_CSR_DB6CTRL 0x342 /* data breakpoint 6 control */
933#define LOONGARCH_CSR_DB6ASID 0x343 /* data breakpoint 6 asid */
934
935#define LOONGARCH_CSR_DB7ADDR 0x348 /* data breakpoint 7 address */
936#define LOONGARCH_CSR_DB7MASK 0x349 /* data breakpoint 7 mask */
937#define LOONGARCH_CSR_DB7CTRL 0x34a /* data breakpoint 7 control */
938#define LOONGARCH_CSR_DB7ASID 0x34b /* data breakpoint 7 asid */
939
940#define LOONGARCH_CSR_FWPC 0x380 /* instruction breakpoint config */
941#define LOONGARCH_CSR_FWPS 0x381 /* instruction breakpoint status */
942
943#define LOONGARCH_CSR_IB0ADDR 0x390 /* inst breakpoint 0 address */
944#define LOONGARCH_CSR_IB0MASK 0x391 /* inst breakpoint 0 mask */
945#define LOONGARCH_CSR_IB0CTRL 0x392 /* inst breakpoint 0 control */
946#define LOONGARCH_CSR_IB0ASID 0x393 /* inst breakpoint 0 asid */
947
948#define LOONGARCH_CSR_IB1ADDR 0x398 /* inst breakpoint 1 address */
949#define LOONGARCH_CSR_IB1MASK 0x399 /* inst breakpoint 1 mask */
950#define LOONGARCH_CSR_IB1CTRL 0x39a /* inst breakpoint 1 control */
951#define LOONGARCH_CSR_IB1ASID 0x39b /* inst breakpoint 1 asid */
952
953#define LOONGARCH_CSR_IB2ADDR 0x3a0 /* inst breakpoint 2 address */
954#define LOONGARCH_CSR_IB2MASK 0x3a1 /* inst breakpoint 2 mask */
955#define LOONGARCH_CSR_IB2CTRL 0x3a2 /* inst breakpoint 2 control */
956#define LOONGARCH_CSR_IB2ASID 0x3a3 /* inst breakpoint 2 asid */
957
958#define LOONGARCH_CSR_IB3ADDR 0x3a8 /* inst breakpoint 3 address */
959#define LOONGARCH_CSR_IB3MASK 0x3a9 /* breakpoint 3 mask */
960#define LOONGARCH_CSR_IB3CTRL 0x3aa /* inst breakpoint 3 control */
961#define LOONGARCH_CSR_IB3ASID 0x3ab /* inst breakpoint 3 asid */
962
963#define LOONGARCH_CSR_IB4ADDR 0x3b0 /* inst breakpoint 4 address */
964#define LOONGARCH_CSR_IB4MASK 0x3b1 /* inst breakpoint 4 mask */
965#define LOONGARCH_CSR_IB4CTRL 0x3b2 /* inst breakpoint 4 control */
966#define LOONGARCH_CSR_IB4ASID 0x3b3 /* inst breakpoint 4 asid */
967
968#define LOONGARCH_CSR_IB5ADDR 0x3b8 /* inst breakpoint 5 address */
969#define LOONGARCH_CSR_IB5MASK 0x3b9 /* inst breakpoint 5 mask */
970#define LOONGARCH_CSR_IB5CTRL 0x3ba /* inst breakpoint 5 control */
971#define LOONGARCH_CSR_IB5ASID 0x3bb /* inst breakpoint 5 asid */
972
973#define LOONGARCH_CSR_IB6ADDR 0x3c0 /* inst breakpoint 6 address */
974#define LOONGARCH_CSR_IB6MASK 0x3c1 /* inst breakpoint 6 mask */
975#define LOONGARCH_CSR_IB6CTRL 0x3c2 /* inst breakpoint 6 control */
976#define LOONGARCH_CSR_IB6ASID 0x3c3 /* inst breakpoint 6 asid */
977
978#define LOONGARCH_CSR_IB7ADDR 0x3c8 /* inst breakpoint 7 address */
979#define LOONGARCH_CSR_IB7MASK 0x3c9 /* inst breakpoint 7 mask */
980#define LOONGARCH_CSR_IB7CTRL 0x3ca /* inst breakpoint 7 control */
981#define LOONGARCH_CSR_IB7ASID 0x3cb /* inst breakpoint 7 asid */
982
983#define LOONGARCH_CSR_DEBUG 0x500 /* debug config */
984#define LOONGARCH_CSR_DERA 0x501 /* debug era */
985#define LOONGARCH_CSR_DESAVE 0x502 /* debug save */
986
987#define CSR_FWPC_SKIP_SHIFT 16
988#define CSR_FWPC_SKIP (_ULCAST_(1) << CSR_FWPC_SKIP_SHIFT)
989
990/*
991 * CSR_ECFG IM
992 */
993#define ECFG0_IM 0x00001fff
994#define ECFGB_SIP0 0
995#define ECFGF_SIP0 (_ULCAST_(1) << ECFGB_SIP0)
996#define ECFGB_SIP1 1
997#define ECFGF_SIP1 (_ULCAST_(1) << ECFGB_SIP1)
998#define ECFGB_IP0 2
999#define ECFGF_IP0 (_ULCAST_(1) << ECFGB_IP0)
1000#define ECFGB_IP1 3
1001#define ECFGF_IP1 (_ULCAST_(1) << ECFGB_IP1)
1002#define ECFGB_IP2 4
1003#define ECFGF_IP2 (_ULCAST_(1) << ECFGB_IP2)
1004#define ECFGB_IP3 5
1005#define ECFGF_IP3 (_ULCAST_(1) << ECFGB_IP3)
1006#define ECFGB_IP4 6
1007#define ECFGF_IP4 (_ULCAST_(1) << ECFGB_IP4)
1008#define ECFGB_IP5 7
1009#define ECFGF_IP5 (_ULCAST_(1) << ECFGB_IP5)
1010#define ECFGB_IP6 8
1011#define ECFGF_IP6 (_ULCAST_(1) << ECFGB_IP6)
1012#define ECFGB_IP7 9
1013#define ECFGF_IP7 (_ULCAST_(1) << ECFGB_IP7)
1014#define ECFGB_PMC 10
1015#define ECFGF_PMC (_ULCAST_(1) << ECFGB_PMC)
1016#define ECFGB_TIMER 11
1017#define ECFGF_TIMER (_ULCAST_(1) << ECFGB_TIMER)
1018#define ECFGB_IPI 12
1019#define ECFGF_IPI (_ULCAST_(1) << ECFGB_IPI)
1020#define ECFGF(hwirq) (_ULCAST_(1) << hwirq)
1021
1022#define ESTATF_IP 0x00003fff
1023
1024#define LOONGARCH_IOCSR_FEATURES 0x8
1025#define IOCSRF_TEMP BIT_ULL(0)
1026#define IOCSRF_NODECNT BIT_ULL(1)
1027#define IOCSRF_MSI BIT_ULL(2)
1028#define IOCSRF_EXTIOI BIT_ULL(3)
1029#define IOCSRF_CSRIPI BIT_ULL(4)
1030#define IOCSRF_FREQCSR BIT_ULL(5)
1031#define IOCSRF_FREQSCALE BIT_ULL(6)
1032#define IOCSRF_DVFSV1 BIT_ULL(7)
1033#define IOCSRF_EIODECODE BIT_ULL(9)
1034#define IOCSRF_FLATMODE BIT_ULL(10)
1035#define IOCSRF_VM BIT_ULL(11)
1036
1037#define LOONGARCH_IOCSR_VENDOR 0x10
1038
1039#define LOONGARCH_IOCSR_CPUNAME 0x20
1040
1041#define LOONGARCH_IOCSR_NODECNT 0x408
1042
1043#define LOONGARCH_IOCSR_MISC_FUNC 0x420
1044#define IOCSR_MISC_FUNC_TIMER_RESET BIT_ULL(21)
1045#define IOCSR_MISC_FUNC_EXT_IOI_EN BIT_ULL(48)
1046
1047#define LOONGARCH_IOCSR_CPUTEMP 0x428
1048
1049/* PerCore CSR, only accessible by local cores */
1050#define LOONGARCH_IOCSR_IPI_STATUS 0x1000
1051#define LOONGARCH_IOCSR_IPI_EN 0x1004
1052#define LOONGARCH_IOCSR_IPI_SET 0x1008
1053#define LOONGARCH_IOCSR_IPI_CLEAR 0x100c
1054#define LOONGARCH_IOCSR_MBUF0 0x1020
1055#define LOONGARCH_IOCSR_MBUF1 0x1028
1056#define LOONGARCH_IOCSR_MBUF2 0x1030
1057#define LOONGARCH_IOCSR_MBUF3 0x1038
1058
1059#define LOONGARCH_IOCSR_IPI_SEND 0x1040
1060#define IOCSR_IPI_SEND_IP_SHIFT 0
1061#define IOCSR_IPI_SEND_CPU_SHIFT 16
1062#define IOCSR_IPI_SEND_BLOCKING BIT(31)
1063
1064#define LOONGARCH_IOCSR_MBUF_SEND 0x1048
1065#define IOCSR_MBUF_SEND_BLOCKING BIT_ULL(31)
1066#define IOCSR_MBUF_SEND_BOX_SHIFT 2
1067#define IOCSR_MBUF_SEND_BOX_LO(box) (box << 1)
1068#define IOCSR_MBUF_SEND_BOX_HI(box) ((box << 1) + 1)
1069#define IOCSR_MBUF_SEND_CPU_SHIFT 16
1070#define IOCSR_MBUF_SEND_BUF_SHIFT 32
1071#define IOCSR_MBUF_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1072
1073#define LOONGARCH_IOCSR_ANY_SEND 0x1158
1074#define IOCSR_ANY_SEND_BLOCKING BIT_ULL(31)
1075#define IOCSR_ANY_SEND_CPU_SHIFT 16
1076#define IOCSR_ANY_SEND_MASK_SHIFT 27
1077#define IOCSR_ANY_SEND_BUF_SHIFT 32
1078#define IOCSR_ANY_SEND_H32_MASK 0xFFFFFFFF00000000ULL
1079
1080/* Register offset and bit definition for CSR access */
1081#define LOONGARCH_IOCSR_TIMER_CFG 0x1060
1082#define LOONGARCH_IOCSR_TIMER_TICK 0x1070
1083#define IOCSR_TIMER_CFG_RESERVED (_ULCAST_(1) << 63)
1084#define IOCSR_TIMER_CFG_PERIODIC (_ULCAST_(1) << 62)
1085#define IOCSR_TIMER_CFG_EN (_ULCAST_(1) << 61)
1086#define IOCSR_TIMER_MASK 0x0ffffffffffffULL
1087#define IOCSR_TIMER_INITVAL_RST (_ULCAST_(0xffff) << 48)
1088
1089#define LOONGARCH_IOCSR_EXTIOI_NODEMAP_BASE 0x14a0
1090#define LOONGARCH_IOCSR_EXTIOI_IPMAP_BASE 0x14c0
1091#define LOONGARCH_IOCSR_EXTIOI_EN_BASE 0x1600
1092#define LOONGARCH_IOCSR_EXTIOI_BOUNCE_BASE 0x1680
1093#define LOONGARCH_IOCSR_EXTIOI_ISR_BASE 0x1800
1094#define LOONGARCH_IOCSR_EXTIOI_ROUTE_BASE 0x1c00
1095#define IOCSR_EXTIOI_VECTOR_NUM 256
1096
1097#ifndef __ASSEMBLY__
1098
1099static __always_inline u64 drdtime(void)
1100{
1101 u64 val = 0;
1102
1103 __asm__ __volatile__(
1104 "rdtime.d %0, $zero\n\t"
1105 : "=r"(val)
1106 :
1107 );
1108 return val;
1109}
1110
1111static inline unsigned int get_csr_cpuid(void)
1112{
1113 return csr_read32(LOONGARCH_CSR_CPUID);
1114}
1115
1116static inline void csr_any_send(unsigned int addr, unsigned int data,
1117 unsigned int data_mask, unsigned int cpu)
1118{
1119 uint64_t val = 0;
1120
1121 val = IOCSR_ANY_SEND_BLOCKING | addr;
1122 val |= (cpu << IOCSR_ANY_SEND_CPU_SHIFT);
1123 val |= (data_mask << IOCSR_ANY_SEND_MASK_SHIFT);
1124 val |= ((uint64_t)data << IOCSR_ANY_SEND_BUF_SHIFT);
1125 iocsr_write64(val, LOONGARCH_IOCSR_ANY_SEND);
1126}
1127
1128static inline unsigned int read_csr_excode(void)
1129{
1130 return (csr_read32(LOONGARCH_CSR_ESTAT) & CSR_ESTAT_EXC) >> CSR_ESTAT_EXC_SHIFT;
1131}
1132
1133static inline void write_csr_index(unsigned int idx)
1134{
1135 csr_xchg32(idx, CSR_TLBIDX_IDXM, LOONGARCH_CSR_TLBIDX);
1136}
1137
1138static inline unsigned int read_csr_pagesize(void)
1139{
1140 return (csr_read32(LOONGARCH_CSR_TLBIDX) & CSR_TLBIDX_SIZEM) >> CSR_TLBIDX_SIZE;
1141}
1142
1143static inline void write_csr_pagesize(unsigned int size)
1144{
1145 csr_xchg32(size << CSR_TLBIDX_SIZE, CSR_TLBIDX_SIZEM, LOONGARCH_CSR_TLBIDX);
1146}
1147
1148static inline unsigned int read_csr_tlbrefill_pagesize(void)
1149{
1150 return (csr_read64(LOONGARCH_CSR_TLBREHI) & CSR_TLBREHI_PS) >> CSR_TLBREHI_PS_SHIFT;
1151}
1152
1153static inline void write_csr_tlbrefill_pagesize(unsigned int size)
1154{
1155 csr_xchg64(size << CSR_TLBREHI_PS_SHIFT, CSR_TLBREHI_PS, LOONGARCH_CSR_TLBREHI);
1156}
1157
1158#define read_csr_asid() csr_read32(LOONGARCH_CSR_ASID)
1159#define write_csr_asid(val) csr_write32(val, LOONGARCH_CSR_ASID)
1160#define read_csr_entryhi() csr_read64(LOONGARCH_CSR_TLBEHI)
1161#define write_csr_entryhi(val) csr_write64(val, LOONGARCH_CSR_TLBEHI)
1162#define read_csr_entrylo0() csr_read64(LOONGARCH_CSR_TLBELO0)
1163#define write_csr_entrylo0(val) csr_write64(val, LOONGARCH_CSR_TLBELO0)
1164#define read_csr_entrylo1() csr_read64(LOONGARCH_CSR_TLBELO1)
1165#define write_csr_entrylo1(val) csr_write64(val, LOONGARCH_CSR_TLBELO1)
1166#define read_csr_ecfg() csr_read32(LOONGARCH_CSR_ECFG)
1167#define write_csr_ecfg(val) csr_write32(val, LOONGARCH_CSR_ECFG)
1168#define read_csr_estat() csr_read32(LOONGARCH_CSR_ESTAT)
1169#define write_csr_estat(val) csr_write32(val, LOONGARCH_CSR_ESTAT)
1170#define read_csr_tlbidx() csr_read32(LOONGARCH_CSR_TLBIDX)
1171#define write_csr_tlbidx(val) csr_write32(val, LOONGARCH_CSR_TLBIDX)
1172#define read_csr_euen() csr_read32(LOONGARCH_CSR_EUEN)
1173#define write_csr_euen(val) csr_write32(val, LOONGARCH_CSR_EUEN)
1174#define read_csr_cpuid() csr_read32(LOONGARCH_CSR_CPUID)
1175#define read_csr_prcfg1() csr_read64(LOONGARCH_CSR_PRCFG1)
1176#define write_csr_prcfg1(val) csr_write64(val, LOONGARCH_CSR_PRCFG1)
1177#define read_csr_prcfg2() csr_read64(LOONGARCH_CSR_PRCFG2)
1178#define write_csr_prcfg2(val) csr_write64(val, LOONGARCH_CSR_PRCFG2)
1179#define read_csr_prcfg3() csr_read64(LOONGARCH_CSR_PRCFG3)
1180#define write_csr_prcfg3(val) csr_write64(val, LOONGARCH_CSR_PRCFG3)
1181#define read_csr_stlbpgsize() csr_read32(LOONGARCH_CSR_STLBPGSIZE)
1182#define write_csr_stlbpgsize(val) csr_write32(val, LOONGARCH_CSR_STLBPGSIZE)
1183#define read_csr_rvacfg() csr_read32(LOONGARCH_CSR_RVACFG)
1184#define write_csr_rvacfg(val) csr_write32(val, LOONGARCH_CSR_RVACFG)
1185#define write_csr_tintclear(val) csr_write32(val, LOONGARCH_CSR_TINTCLR)
1186#define read_csr_impctl1() csr_read64(LOONGARCH_CSR_IMPCTL1)
1187#define write_csr_impctl1(val) csr_write64(val, LOONGARCH_CSR_IMPCTL1)
1188#define write_csr_impctl2(val) csr_write64(val, LOONGARCH_CSR_IMPCTL2)
1189
1190#define read_csr_perfctrl0() csr_read64(LOONGARCH_CSR_PERFCTRL0)
1191#define read_csr_perfcntr0() csr_read64(LOONGARCH_CSR_PERFCNTR0)
1192#define read_csr_perfctrl1() csr_read64(LOONGARCH_CSR_PERFCTRL1)
1193#define read_csr_perfcntr1() csr_read64(LOONGARCH_CSR_PERFCNTR1)
1194#define read_csr_perfctrl2() csr_read64(LOONGARCH_CSR_PERFCTRL2)
1195#define read_csr_perfcntr2() csr_read64(LOONGARCH_CSR_PERFCNTR2)
1196#define read_csr_perfctrl3() csr_read64(LOONGARCH_CSR_PERFCTRL3)
1197#define read_csr_perfcntr3() csr_read64(LOONGARCH_CSR_PERFCNTR3)
1198#define write_csr_perfctrl0(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL0)
1199#define write_csr_perfcntr0(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR0)
1200#define write_csr_perfctrl1(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL1)
1201#define write_csr_perfcntr1(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR1)
1202#define write_csr_perfctrl2(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL2)
1203#define write_csr_perfcntr2(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR2)
1204#define write_csr_perfctrl3(val) csr_write64(val, LOONGARCH_CSR_PERFCTRL3)
1205#define write_csr_perfcntr3(val) csr_write64(val, LOONGARCH_CSR_PERFCNTR3)
1206
1207/*
1208 * Manipulate bits in a register.
1209 */
1210#define __BUILD_CSR_COMMON(name) \
1211static inline unsigned long \
1212set_##name(unsigned long set) \
1213{ \
1214 unsigned long res, new; \
1215 \
1216 res = read_##name(); \
1217 new = res | set; \
1218 write_##name(new); \
1219 \
1220 return res; \
1221} \
1222 \
1223static inline unsigned long \
1224clear_##name(unsigned long clear) \
1225{ \
1226 unsigned long res, new; \
1227 \
1228 res = read_##name(); \
1229 new = res & ~clear; \
1230 write_##name(new); \
1231 \
1232 return res; \
1233} \
1234 \
1235static inline unsigned long \
1236change_##name(unsigned long change, unsigned long val) \
1237{ \
1238 unsigned long res, new; \
1239 \
1240 res = read_##name(); \
1241 new = res & ~change; \
1242 new |= (val & change); \
1243 write_##name(new); \
1244 \
1245 return res; \
1246}
1247
1248#define __BUILD_CSR_OP(name) __BUILD_CSR_COMMON(csr_##name)
1249
1250__BUILD_CSR_OP(euen)
1251__BUILD_CSR_OP(ecfg)
1252__BUILD_CSR_OP(tlbidx)
1253
1254#define set_csr_estat(val) \
1255 csr_xchg32(val, val, LOONGARCH_CSR_ESTAT)
1256#define clear_csr_estat(val) \
1257 csr_xchg32(~(val), val, LOONGARCH_CSR_ESTAT)
1258
1259#endif /* __ASSEMBLY__ */
1260
1261/* Generic EntryLo bit definitions */
1262#define ENTRYLO_V (_ULCAST_(1) << 0)
1263#define ENTRYLO_D (_ULCAST_(1) << 1)
1264#define ENTRYLO_PLV_SHIFT 2
1265#define ENTRYLO_PLV (_ULCAST_(3) << ENTRYLO_PLV_SHIFT)
1266#define ENTRYLO_C_SHIFT 4
1267#define ENTRYLO_C (_ULCAST_(3) << ENTRYLO_C_SHIFT)
1268#define ENTRYLO_G (_ULCAST_(1) << 6)
1269#define ENTRYLO_NR (_ULCAST_(1) << 61)
1270#define ENTRYLO_NX (_ULCAST_(1) << 62)
1271
1272/* Values for PageSize register */
1273#define PS_4K 0x0000000c
1274#define PS_8K 0x0000000d
1275#define PS_16K 0x0000000e
1276#define PS_32K 0x0000000f
1277#define PS_64K 0x00000010
1278#define PS_128K 0x00000011
1279#define PS_256K 0x00000012
1280#define PS_512K 0x00000013
1281#define PS_1M 0x00000014
1282#define PS_2M 0x00000015
1283#define PS_4M 0x00000016
1284#define PS_8M 0x00000017
1285#define PS_16M 0x00000018
1286#define PS_32M 0x00000019
1287#define PS_64M 0x0000001a
1288#define PS_128M 0x0000001b
1289#define PS_256M 0x0000001c
1290#define PS_512M 0x0000001d
1291#define PS_1G 0x0000001e
1292
1293/* Default page size for a given kernel configuration */
1294#ifdef CONFIG_PAGE_SIZE_4KB
1295#define PS_DEFAULT_SIZE PS_4K
1296#elif defined(CONFIG_PAGE_SIZE_16KB)
1297#define PS_DEFAULT_SIZE PS_16K
1298#elif defined(CONFIG_PAGE_SIZE_64KB)
1299#define PS_DEFAULT_SIZE PS_64K
1300#else
1301#error Bad page size configuration!
1302#endif
1303
1304/* Default huge tlb size for a given kernel configuration */
1305#ifdef CONFIG_PAGE_SIZE_4KB
1306#define PS_HUGE_SIZE PS_1M
1307#elif defined(CONFIG_PAGE_SIZE_16KB)
1308#define PS_HUGE_SIZE PS_16M
1309#elif defined(CONFIG_PAGE_SIZE_64KB)
1310#define PS_HUGE_SIZE PS_256M
1311#else
1312#error Bad page size configuration for hugetlbfs!
1313#endif
1314
1315/* ExStatus.ExcCode */
1316#define EXCCODE_RSV 0 /* Reserved */
1317#define EXCCODE_TLBL 1 /* TLB miss on a load */
1318#define EXCCODE_TLBS 2 /* TLB miss on a store */
1319#define EXCCODE_TLBI 3 /* TLB miss on a ifetch */
1320#define EXCCODE_TLBM 4 /* TLB modified fault */
1321#define EXCCODE_TLBNR 5 /* TLB Read-Inhibit exception */
1322#define EXCCODE_TLBNX 6 /* TLB Execution-Inhibit exception */
1323#define EXCCODE_TLBPE 7 /* TLB Privilege Error */
1324#define EXCCODE_ADE 8 /* Address Error */
1325 #define EXSUBCODE_ADEF 0 /* Fetch Instruction */
1326 #define EXSUBCODE_ADEM 1 /* Access Memory*/
1327#define EXCCODE_ALE 9 /* Unalign Access */
1328#define EXCCODE_BCE 10 /* Bounds Check Error */
1329#define EXCCODE_SYS 11 /* System call */
1330#define EXCCODE_BP 12 /* Breakpoint */
1331#define EXCCODE_INE 13 /* Inst. Not Exist */
1332#define EXCCODE_IPE 14 /* Inst. Privileged Error */
1333#define EXCCODE_FPDIS 15 /* FPU Disabled */
1334#define EXCCODE_LSXDIS 16 /* LSX Disabled */
1335#define EXCCODE_LASXDIS 17 /* LASX Disabled */
1336#define EXCCODE_FPE 18 /* Floating Point Exception */
1337 #define EXCSUBCODE_FPE 0 /* Floating Point Exception */
1338 #define EXCSUBCODE_VFPE 1 /* Vector Exception */
1339#define EXCCODE_WATCH 19 /* WatchPoint Exception */
1340 #define EXCSUBCODE_WPEF 0 /* ... on Instruction Fetch */
1341 #define EXCSUBCODE_WPEM 1 /* ... on Memory Accesses */
1342#define EXCCODE_BTDIS 20 /* Binary Trans. Disabled */
1343#define EXCCODE_BTE 21 /* Binary Trans. Exception */
1344#define EXCCODE_GSPR 22 /* Guest Privileged Error */
1345#define EXCCODE_HVC 23 /* Hypercall */
1346#define EXCCODE_GCM 24 /* Guest CSR modified */
1347 #define EXCSUBCODE_GCSC 0 /* Software caused */
1348 #define EXCSUBCODE_GCHC 1 /* Hardware caused */
1349#define EXCCODE_SE 25 /* Security */
1350
1351/* Interrupt numbers */
1352#define INT_SWI0 0 /* Software Interrupts */
1353#define INT_SWI1 1
1354#define INT_HWI0 2 /* Hardware Interrupts */
1355#define INT_HWI1 3
1356#define INT_HWI2 4
1357#define INT_HWI3 5
1358#define INT_HWI4 6
1359#define INT_HWI5 7
1360#define INT_HWI6 8
1361#define INT_HWI7 9
1362#define INT_PCOV 10 /* Performance Counter Overflow */
1363#define INT_TI 11 /* Timer */
1364#define INT_IPI 12
1365#define INT_NMI 13
1366
1367/* ExcCodes corresponding to interrupts */
1368#define EXCCODE_INT_NUM (INT_NMI + 1)
1369#define EXCCODE_INT_START 64
1370#define EXCCODE_INT_END (EXCCODE_INT_START + EXCCODE_INT_NUM - 1)
1371
1372/* FPU Status Register Names */
1373#ifndef CONFIG_AS_HAS_FCSR_CLASS
1374#define LOONGARCH_FCSR0 $r0
1375#define LOONGARCH_FCSR1 $r1
1376#define LOONGARCH_FCSR2 $r2
1377#define LOONGARCH_FCSR3 $r3
1378#else
1379#define LOONGARCH_FCSR0 $fcsr0
1380#define LOONGARCH_FCSR1 $fcsr1
1381#define LOONGARCH_FCSR2 $fcsr2
1382#define LOONGARCH_FCSR3 $fcsr3
1383#endif
1384
1385/* FPU Status Register Values */
1386#define FPU_CSR_RSVD 0xe0e0fce0
1387
1388/*
1389 * X the exception cause indicator
1390 * E the exception enable
1391 * S the sticky/flag bit
1392 */
1393#define FPU_CSR_ALL_X 0x1f000000
1394#define FPU_CSR_INV_X 0x10000000
1395#define FPU_CSR_DIV_X 0x08000000
1396#define FPU_CSR_OVF_X 0x04000000
1397#define FPU_CSR_UDF_X 0x02000000
1398#define FPU_CSR_INE_X 0x01000000
1399
1400#define FPU_CSR_ALL_S 0x001f0000
1401#define FPU_CSR_INV_S 0x00100000
1402#define FPU_CSR_DIV_S 0x00080000
1403#define FPU_CSR_OVF_S 0x00040000
1404#define FPU_CSR_UDF_S 0x00020000
1405#define FPU_CSR_INE_S 0x00010000
1406
1407#define FPU_CSR_ALL_E 0x0000001f
1408#define FPU_CSR_INV_E 0x00000010
1409#define FPU_CSR_DIV_E 0x00000008
1410#define FPU_CSR_OVF_E 0x00000004
1411#define FPU_CSR_UDF_E 0x00000002
1412#define FPU_CSR_INE_E 0x00000001
1413
1414/* Bits 8 and 9 of FPU Status Register specify the rounding mode */
1415#define FPU_CSR_RM 0x300
1416#define FPU_CSR_RN 0x000 /* nearest */
1417#define FPU_CSR_RZ 0x100 /* towards zero */
1418#define FPU_CSR_RU 0x200 /* towards +Infinity */
1419#define FPU_CSR_RD 0x300 /* towards -Infinity */
1420
1421/* Bit 6 of FPU Status Register specify the LBT TOP simulation mode */
1422#define FPU_CSR_TM_SHIFT 0x6
1423#define FPU_CSR_TM (_ULCAST_(1) << FPU_CSR_TM_SHIFT)
1424
1425#define read_fcsr(source) \
1426({ \
1427 unsigned int __res; \
1428\
1429 __asm__ __volatile__( \
1430 " movfcsr2gr %0, "__stringify(source)" \n" \
1431 : "=r" (__res)); \
1432 __res; \
1433})
1434
1435#define write_fcsr(dest, val) \
1436do { \
1437 __asm__ __volatile__( \
1438 " movgr2fcsr "__stringify(dest)", %0 \n" \
1439 : : "r" (val)); \
1440} while (0)
1441
1442#endif /* _ASM_LOONGARCH_H */