1// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
  2/*
  3 * Realtek RTD1395 SoC family
  4 *
  5 * Copyright (c) 2019 Andreas Färber
  6 */
  7
  8/memreserve/	0x0000000000000000 0x000000000002f000;
  9/memreserve/	0x000000000002f000 0x00000000000d1000;
 10
 11#include <dt-bindings/interrupt-controller/arm-gic.h>
 12#include <dt-bindings/reset/realtek,rtd1295.h>
 13
 14/ {
 15	interrupt-parent = <&gic>;
 16	#address-cells = <1>;
 17	#size-cells = <1>;
 18
 19	reserved-memory {
 20		#address-cells = <1>;
 21		#size-cells = <1>;
 22		ranges;
 23
 24		rpc_comm: rpc@2f000 {
 25			reg = <0x2f000 0x1000>;
 26		};
 27
 28		rpc_ringbuf: rpc@1ffe000 {
 29			reg = <0x1ffe000 0x4000>;
 30		};
 31
 32		tee: tee@10100000 {
 33			reg = <0x10100000 0xf00000>;
 34			no-map;
 35		};
 36	};
 37
 38	arm_pmu: arm-pmu {
 39		compatible = "arm,cortex-a53-pmu";
 40		interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 41	};
 42
 43	osc27M: osc {
 44		compatible = "fixed-clock";
 45		clock-frequency = <27000000>;
 46		#clock-cells = <0>;
 47		clock-output-names = "osc27M";
 48	};
 49
 50	soc {
 51		compatible = "simple-bus";
 52		#address-cells = <1>;
 53		#size-cells = <1>;
 54		ranges = <0x00000000 0x00000000 0x0001f000>, /* boot ROM */
 55			 <0x98000000 0x98000000 0x68000000>;
 56
 57		rbus: bus@98000000 {
 58			compatible = "simple-bus";
 59			reg = <0x98000000 0x200000>;
 60			#address-cells = <1>;
 61			#size-cells = <1>;
 62			ranges = <0x0 0x98000000 0x200000>;
 63
 64			crt: syscon@0 {
 65				compatible = "syscon", "simple-mfd";
 66				reg = <0x0 0x1000>;
 67				reg-io-width = <4>;
 68				#address-cells = <1>;
 69				#size-cells = <1>;
 70				ranges = <0x0 0x0 0x1000>;
 71			};
 72
 73			iso: syscon@7000 {
 74				compatible = "syscon", "simple-mfd";
 75				reg = <0x7000 0x1000>;
 76				reg-io-width = <4>;
 77				#address-cells = <1>;
 78				#size-cells = <1>;
 79				ranges = <0x0 0x7000 0x1000>;
 80			};
 81
 82			sb2: syscon@1a000 {
 83				compatible = "syscon", "simple-mfd";
 84				reg = <0x1a000 0x1000>;
 85				reg-io-width = <4>;
 86				#address-cells = <1>;
 87				#size-cells = <1>;
 88				ranges = <0x0 0x1a000 0x1000>;
 89			};
 90
 91			misc: syscon@1b000 {
 92				compatible = "syscon", "simple-mfd";
 93				reg = <0x1b000 0x1000>;
 94				reg-io-width = <4>;
 95				#address-cells = <1>;
 96				#size-cells = <1>;
 97				ranges = <0x0 0x1b000 0x1000>;
 98			};
 99
100			scpu_wrapper: syscon@1d000 {
101				compatible = "syscon", "simple-mfd";
102				reg = <0x1d000 0x2000>;
103				reg-io-width = <4>;
104				#address-cells = <1>;
105				#size-cells = <1>;
106				ranges = <0x0 0x1d000 0x2000>;
107			};
108		};
109
110		gic: interrupt-controller@ff011000 {
111			compatible = "arm,gic-400";
112			reg = <0xff011000 0x1000>,
113			      <0xff012000 0x2000>,
114			      <0xff014000 0x2000>,
115			      <0xff016000 0x2000>;
116			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
117			interrupt-controller;
118			#interrupt-cells = <3>;
119		};
120	};
121};
122
123&crt {
124	reset1: reset-controller@0 {
125		compatible = "snps,dw-low-reset";
126		reg = <0x0 0x4>;
127		#reset-cells = <1>;
128	};
129
130	reset2: reset-controller@4 {
131		compatible = "snps,dw-low-reset";
132		reg = <0x4 0x4>;
133		#reset-cells = <1>;
134	};
135
136	reset3: reset-controller@8 {
137		compatible = "snps,dw-low-reset";
138		reg = <0x8 0x4>;
139		#reset-cells = <1>;
140	};
141
142	reset4: reset-controller@50 {
143		compatible = "snps,dw-low-reset";
144		reg = <0x50 0x4>;
145		#reset-cells = <1>;
146	};
147};
148
149&iso {
150	iso_reset: reset-controller@88 {
151		compatible = "snps,dw-low-reset";
152		reg = <0x88 0x4>;
153		#reset-cells = <1>;
154	};
155
156	wdt: watchdog@680 {
157		compatible = "realtek,rtd1295-watchdog";
158		reg = <0x680 0x100>;
159		clocks = <&osc27M>;
160	};
161
162	uart0: serial@800 {
163		compatible = "snps,dw-apb-uart";
164		reg = <0x800 0x400>;
165		reg-shift = <2>;
166		reg-io-width = <4>;
167		clock-frequency = <27000000>;
168		resets = <&iso_reset RTD1295_ISO_RSTN_UR0>;
169		status = "disabled";
170	};
171};
172
173&misc {
174	uart1: serial@200 {
175		compatible = "snps,dw-apb-uart";
176		reg = <0x200 0x100>;
177		reg-shift = <2>;
178		reg-io-width = <4>;
179		clock-frequency = <432000000>;
180		resets = <&reset2 RTD1295_RSTN_UR1>;
181		status = "disabled";
182	};
183
184	uart2: serial@400 {
185		compatible = "snps,dw-apb-uart";
186		reg = <0x400 0x100>;
187		reg-shift = <2>;
188		reg-io-width = <4>;
189		clock-frequency = <432000000>;
190		resets = <&reset2 RTD1295_RSTN_UR2>;
191		status = "disabled";
192	};
193};