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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2023, Linaro Ltd
4 *
5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain.
6 */
7
8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h>
9#include <dt-bindings/clock/qcom,gcc-qcm2290.h>
10#include <dt-bindings/clock/qcom,rpmcc.h>
11#include <dt-bindings/dma/qcom-gpi.h>
12#include <dt-bindings/firmware/qcom,scm.h>
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interconnect/qcom,qcm2290.h>
16#include <dt-bindings/interconnect/qcom,rpm-icc.h>
17#include <dt-bindings/power/qcom-rpmpd.h>
18
19/ {
20 interrupt-parent = <&intc>;
21
22 #address-cells = <2>;
23 #size-cells = <2>;
24
25 chosen { };
26
27 clocks {
28 xo_board: xo-board {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 };
32
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 clock-frequency = <32764>;
36 #clock-cells = <0>;
37 };
38 };
39
40 cpus {
41 #address-cells = <2>;
42 #size-cells = <0>;
43
44 CPU0: cpu@0 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a53";
47 reg = <0x0 0x0>;
48 clocks = <&cpufreq_hw 0>;
49 capacity-dmips-mhz = <1024>;
50 dynamic-power-coefficient = <100>;
51 enable-method = "psci";
52 next-level-cache = <&L2_0>;
53 qcom,freq-domain = <&cpufreq_hw 0>;
54 power-domains = <&CPU_PD0>;
55 power-domain-names = "psci";
56 L2_0: l2-cache {
57 compatible = "cache";
58 cache-level = <2>;
59 cache-unified;
60 };
61 };
62
63 CPU1: cpu@1 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a53";
66 reg = <0x0 0x1>;
67 clocks = <&cpufreq_hw 0>;
68 capacity-dmips-mhz = <1024>;
69 dynamic-power-coefficient = <100>;
70 enable-method = "psci";
71 next-level-cache = <&L2_0>;
72 qcom,freq-domain = <&cpufreq_hw 0>;
73 power-domains = <&CPU_PD1>;
74 power-domain-names = "psci";
75 };
76
77 CPU2: cpu@2 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a53";
80 reg = <0x0 0x2>;
81 clocks = <&cpufreq_hw 0>;
82 capacity-dmips-mhz = <1024>;
83 dynamic-power-coefficient = <100>;
84 enable-method = "psci";
85 next-level-cache = <&L2_0>;
86 qcom,freq-domain = <&cpufreq_hw 0>;
87 power-domains = <&CPU_PD2>;
88 power-domain-names = "psci";
89 };
90
91 CPU3: cpu@3 {
92 device_type = "cpu";
93 compatible = "arm,cortex-a53";
94 reg = <0x0 0x3>;
95 clocks = <&cpufreq_hw 0>;
96 capacity-dmips-mhz = <1024>;
97 dynamic-power-coefficient = <100>;
98 enable-method = "psci";
99 next-level-cache = <&L2_0>;
100 qcom,freq-domain = <&cpufreq_hw 0>;
101 power-domains = <&CPU_PD3>;
102 power-domain-names = "psci";
103 };
104
105 cpu-map {
106 cluster0 {
107 core0 {
108 cpu = <&CPU0>;
109 };
110
111 core1 {
112 cpu = <&CPU1>;
113 };
114
115 core2 {
116 cpu = <&CPU2>;
117 };
118
119 core3 {
120 cpu = <&CPU3>;
121 };
122 };
123 };
124
125 domain-idle-states {
126 CLUSTER_SLEEP: cluster-sleep-0 {
127 compatible = "domain-idle-state";
128 arm,psci-suspend-param = <0x41000043>;
129 entry-latency-us = <800>;
130 exit-latency-us = <2118>;
131 min-residency-us = <7376>;
132 };
133 };
134
135 idle-states {
136 entry-method = "psci";
137
138 CPU_SLEEP: cpu-sleep-0 {
139 compatible = "arm,idle-state";
140 idle-state-name = "power-collapse";
141 arm,psci-suspend-param = <0x40000003>;
142 entry-latency-us = <290>;
143 exit-latency-us = <376>;
144 min-residency-us = <1182>;
145 local-timer-stop;
146 };
147 };
148 };
149
150 firmware {
151 scm: scm {
152 compatible = "qcom,scm-qcm2290", "qcom,scm";
153 clocks = <&rpmcc RPM_SMD_CE1_CLK>;
154 clock-names = "core";
155 #reset-cells = <1>;
156 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
157 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
158 };
159 };
160
161 memory@40000000 {
162 device_type = "memory";
163 /* We expect the bootloader to fill in the size */
164 reg = <0 0x40000000 0 0>;
165 };
166
167 pmu {
168 compatible = "arm,armv8-pmuv3";
169 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
170 };
171
172 psci {
173 compatible = "arm,psci-1.0";
174 method = "smc";
175
176 CPU_PD0: power-domain-cpu0 {
177 #power-domain-cells = <0>;
178 power-domains = <&CLUSTER_PD>;
179 domain-idle-states = <&CPU_SLEEP>;
180 };
181
182 CPU_PD1: power-domain-cpu1 {
183 #power-domain-cells = <0>;
184 power-domains = <&CLUSTER_PD>;
185 domain-idle-states = <&CPU_SLEEP>;
186 };
187
188 CPU_PD2: power-domain-cpu2 {
189 #power-domain-cells = <0>;
190 power-domains = <&CLUSTER_PD>;
191 domain-idle-states = <&CPU_SLEEP>;
192 };
193
194 CPU_PD3: power-domain-cpu3 {
195 #power-domain-cells = <0>;
196 power-domains = <&CLUSTER_PD>;
197 domain-idle-states = <&CPU_SLEEP>;
198 };
199
200 CLUSTER_PD: power-domain-cpu-cluster {
201 #power-domain-cells = <0>;
202 power-domains = <&mpm>;
203 domain-idle-states = <&CLUSTER_SLEEP>;
204 };
205 };
206
207 rpm: remoteproc {
208 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc";
209
210 glink-edge {
211 compatible = "qcom,glink-rpm";
212 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
213 qcom,rpm-msg-ram = <&rpm_msg_ram>;
214 mboxes = <&apcs_glb 0>;
215
216 rpm_requests: rpm-requests {
217 compatible = "qcom,rpm-qcm2290";
218 qcom,glink-channels = "rpm_requests";
219
220 rpmcc: clock-controller {
221 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc";
222 clocks = <&xo_board>;
223 clock-names = "xo";
224 #clock-cells = <1>;
225 };
226
227 rpmpd: power-controller {
228 compatible = "qcom,qcm2290-rpmpd";
229 #power-domain-cells = <1>;
230 operating-points-v2 = <&rpmpd_opp_table>;
231
232 rpmpd_opp_table: opp-table {
233 compatible = "operating-points-v2";
234
235 rpmpd_opp_min_svs: opp1 {
236 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
237 };
238
239 rpmpd_opp_low_svs: opp2 {
240 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
241 };
242
243 rpmpd_opp_svs: opp3 {
244 opp-level = <RPM_SMD_LEVEL_SVS>;
245 };
246
247 rpmpd_opp_svs_plus: opp4 {
248 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
249 };
250
251 rpmpd_opp_nom: opp5 {
252 opp-level = <RPM_SMD_LEVEL_NOM>;
253 };
254
255 rpmpd_opp_nom_plus: opp6 {
256 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
257 };
258
259 rpmpd_opp_turbo: opp7 {
260 opp-level = <RPM_SMD_LEVEL_TURBO>;
261 };
262
263 rpmpd_opp_turbo_plus: opp8 {
264 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
265 };
266 };
267 };
268 };
269 };
270
271 mpm: interrupt-controller {
272 compatible = "qcom,mpm";
273 qcom,rpm-msg-ram = <&apss_mpm>;
274 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
275 mboxes = <&apcs_glb 1>;
276 interrupt-controller;
277 #interrupt-cells = <2>;
278 #power-domain-cells = <0>;
279 interrupt-parent = <&intc>;
280 qcom,mpm-pin-count = <96>;
281 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */
282 <5 296>, /* Soundwire master_irq */
283 <12 422>, /* DWC3 ss_phy_irq */
284 <24 79>, /* Soundwire wake_irq */
285 <86 183>, /* MPM wake, SPMI */
286 <90 260>; /* QUSB2_PHY DP+DM */
287 };
288 };
289
290 reserved_memory: reserved-memory {
291 #address-cells = <2>;
292 #size-cells = <2>;
293 ranges;
294
295 hyp_mem: hyp@45700000 {
296 reg = <0x0 0x45700000 0x0 0x600000>;
297 no-map;
298 };
299
300 xbl_aop_mem: xbl-aop@45e00000 {
301 reg = <0x0 0x45e00000 0x0 0x140000>;
302 no-map;
303 };
304
305 sec_apps_mem: sec-apps@45fff000 {
306 reg = <0x0 0x45fff000 0x0 0x1000>;
307 no-map;
308 };
309
310 smem_mem: smem@46000000 {
311 compatible = "qcom,smem";
312 reg = <0x0 0x46000000 0x0 0x200000>;
313 no-map;
314
315 hwlocks = <&tcsr_mutex 3>;
316 qcom,rpm-msg-ram = <&rpm_msg_ram>;
317 };
318
319 pil_modem_mem: modem@4ab00000 {
320 reg = <0x0 0x4ab00000 0x0 0x6900000>;
321 no-map;
322 };
323
324 pil_video_mem: video@51400000 {
325 reg = <0x0 0x51400000 0x0 0x500000>;
326 no-map;
327 };
328
329 wlan_msa_mem: wlan-msa@51900000 {
330 reg = <0x0 0x51900000 0x0 0x100000>;
331 no-map;
332 };
333
334 pil_adsp_mem: adsp@51a00000 {
335 reg = <0x0 0x51a00000 0x0 0x1c00000>;
336 no-map;
337 };
338
339 pil_ipa_fw_mem: ipa-fw@53600000 {
340 reg = <0x0 0x53600000 0x0 0x10000>;
341 no-map;
342 };
343
344 pil_ipa_gsi_mem: ipa-gsi@53610000 {
345 reg = <0x0 0x53610000 0x0 0x5000>;
346 no-map;
347 };
348
349 pil_gpu_mem: zap@53615000 {
350 compatible = "shared-dma-pool";
351 reg = <0x0 0x53615000 0x0 0x2000>;
352 no-map;
353 };
354
355 cont_splash_memory: framebuffer@5c000000 {
356 reg = <0x0 0x5c000000 0x0 0x00f00000>;
357 no-map;
358 };
359
360 dfps_data_memory: dpfs-data@5cf00000 {
361 reg = <0x0 0x5cf00000 0x0 0x0100000>;
362 no-map;
363 };
364
365 removed_mem: reserved@60000000 {
366 reg = <0x0 0x60000000 0x0 0x3900000>;
367 no-map;
368 };
369
370 rmtfs_mem: memory@89b01000 {
371 compatible = "qcom,rmtfs-mem";
372 reg = <0x0 0x89b01000 0x0 0x200000>;
373 no-map;
374
375 qcom,client-id = <1>;
376 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
377 };
378 };
379
380 smp2p-adsp {
381 compatible = "qcom,smp2p";
382 qcom,smem = <443>, <429>;
383
384 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
385
386 mboxes = <&apcs_glb 10>;
387
388 qcom,local-pid = <0>;
389 qcom,remote-pid = <2>;
390
391 adsp_smp2p_out: master-kernel {
392 qcom,entry-name = "master-kernel";
393 #qcom,smem-state-cells = <1>;
394 };
395
396 adsp_smp2p_in: slave-kernel {
397 qcom,entry-name = "slave-kernel";
398 interrupt-controller;
399 #interrupt-cells = <2>;
400 };
401 };
402
403 smp2p-mpss {
404 compatible = "qcom,smp2p";
405 qcom,smem = <435>, <428>;
406
407 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
408
409 mboxes = <&apcs_glb 14>;
410
411 qcom,local-pid = <0>;
412 qcom,remote-pid = <1>;
413
414 modem_smp2p_out: master-kernel {
415 qcom,entry-name = "master-kernel";
416 #qcom,smem-state-cells = <1>;
417 };
418
419 modem_smp2p_in: slave-kernel {
420 qcom,entry-name = "slave-kernel";
421 interrupt-controller;
422 #interrupt-cells = <2>;
423 };
424
425 wlan_smp2p_in: wlan-wpss-to-ap {
426 qcom,entry-name = "wlan";
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 };
430 };
431
432 soc: soc@0 {
433 compatible = "simple-bus";
434 #address-cells = <2>;
435 #size-cells = <2>;
436 ranges = <0 0 0 0 0x10 0>;
437 dma-ranges = <0 0 0 0 0x10 0>;
438
439 tcsr_mutex: hwlock@340000 {
440 compatible = "qcom,tcsr-mutex";
441 reg = <0x0 0x00340000 0x0 0x20000>;
442 #hwlock-cells = <1>;
443 };
444
445 tcsr_regs: syscon@3c0000 {
446 compatible = "qcom,qcm2290-tcsr", "syscon";
447 reg = <0x0 0x003c0000 0x0 0x40000>;
448 };
449
450 tlmm: pinctrl@500000 {
451 compatible = "qcom,qcm2290-tlmm";
452 reg = <0x0 0x00500000 0x0 0x300000>;
453 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
454 gpio-controller;
455 gpio-ranges = <&tlmm 0 0 127>;
456 wakeup-parent = <&mpm>;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460
461 qup_i2c0_default: qup-i2c0-default-state {
462 pins = "gpio0", "gpio1";
463 function = "qup0";
464 drive-strength = <2>;
465 bias-pull-up;
466 };
467
468 qup_i2c1_default: qup-i2c1-default-state {
469 pins = "gpio4", "gpio5";
470 function = "qup1";
471 drive-strength = <2>;
472 bias-pull-up;
473 };
474
475 qup_i2c2_default: qup-i2c2-default-state {
476 pins = "gpio6", "gpio7";
477 function = "qup2";
478 drive-strength = <2>;
479 bias-pull-up;
480 };
481
482 qup_i2c3_default: qup-i2c3-default-state {
483 pins = "gpio8", "gpio9";
484 function = "qup3";
485 drive-strength = <2>;
486 bias-pull-up;
487 };
488
489 qup_i2c4_default: qup-i2c4-default-state {
490 pins = "gpio12", "gpio13";
491 function = "qup4";
492 drive-strength = <2>;
493 bias-pull-up;
494 };
495
496 qup_i2c5_default: qup-i2c5-default-state {
497 pins = "gpio14", "gpio15";
498 function = "qup5";
499 drive-strength = <2>;
500 bias-pull-up;
501 };
502
503 qup_spi0_default: qup-spi0-default-state {
504 pins = "gpio0", "gpio1","gpio2", "gpio3";
505 function = "qup0";
506 drive-strength = <2>;
507 bias-pull-up;
508 };
509
510 qup_spi1_default: qup-spi1-default-state {
511 pins = "gpio4", "gpio5", "gpio69", "gpio70";
512 function = "qup1";
513 drive-strength = <2>;
514 bias-pull-up;
515 };
516
517 qup_spi2_default: qup-spi2-default-state {
518 pins = "gpio6", "gpio7", "gpio71", "gpio80";
519 function = "qup2";
520 drive-strength = <2>;
521 bias-pull-up;
522 };
523
524 qup_spi3_default: qup-spi3-default-state {
525 pins = "gpio8", "gpio9", "gpio10", "gpio11";
526 function = "qup3";
527 drive-strength = <2>;
528 bias-pull-up;
529 };
530
531 qup_spi4_default: qup-spi4-default-state {
532 pins = "gpio12", "gpio13", "gpio96", "gpio97";
533 function = "qup4";
534 drive-strength = <2>;
535 bias-pull-up;
536 };
537
538 qup_spi5_default: qup-spi5-default-state {
539 pins = "gpio14", "gpio15", "gpio16", "gpio17";
540 function = "qup5";
541 drive-strength = <2>;
542 bias-pull-up;
543 };
544
545 qup_uart0_default: qup-uart0-default-state {
546 pins = "gpio0", "gpio1", "gpio2", "gpio3";
547 function = "qup0";
548 drive-strength = <2>;
549 bias-disable;
550 };
551
552 qup_uart4_default: qup-uart4-default-state {
553 pins = "gpio12", "gpio13";
554 function = "qup4";
555 drive-strength = <2>;
556 bias-disable;
557 };
558
559 sdc1_state_on: sdc1-on-state {
560 clk-pins {
561 pins = "sdc1_clk";
562 drive-strength = <16>;
563 bias-disable;
564 };
565
566 cmd-pins {
567 pins = "sdc1_cmd";
568 drive-strength = <10>;
569 bias-pull-up;
570 };
571
572 data-pins {
573 pins = "sdc1_data";
574 drive-strength = <10>;
575 bias-pull-up;
576 };
577
578 rclk-pins {
579 pins = "sdc1_rclk";
580 bias-pull-down;
581 };
582 };
583
584 sdc1_state_off: sdc1-off-state {
585 clk-pins {
586 pins = "sdc1_clk";
587 drive-strength = <2>;
588 bias-disable;
589 };
590
591 cmd-pins {
592 pins = "sdc1_cmd";
593 drive-strength = <2>;
594 bias-pull-up;
595 };
596
597 data-pins {
598 pins = "sdc1_data";
599 drive-strength = <2>;
600 bias-pull-up;
601 };
602
603 rclk-pins {
604 pins = "sdc1_rclk";
605 bias-pull-down;
606 };
607 };
608
609 sdc2_state_on: sdc2-on-state {
610 clk-pins {
611 pins = "sdc2_clk";
612 drive-strength = <16>;
613 bias-disable;
614 };
615
616 cmd-pins {
617 pins = "sdc2_cmd";
618 drive-strength = <10>;
619 bias-pull-up;
620 };
621
622 data-pins {
623 pins = "sdc2_data";
624 drive-strength = <10>;
625 bias-pull-up;
626 };
627 };
628
629 sdc2_state_off: sdc2-off-state {
630 clk-pins {
631 pins = "sdc2_clk";
632 drive-strength = <2>;
633 bias-disable;
634 };
635
636 cmd-pins {
637 pins = "sdc2_cmd";
638 drive-strength = <2>;
639 bias-pull-up;
640 };
641
642 data-pins {
643 pins = "sdc2_data";
644 drive-strength = <2>;
645 bias-pull-up;
646 };
647 };
648 };
649
650 gcc: clock-controller@1400000 {
651 compatible = "qcom,gcc-qcm2290";
652 reg = <0x0 0x01400000 0x0 0x1f0000>;
653 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
654 clock-names = "bi_tcxo", "sleep_clk";
655 #clock-cells = <1>;
656 #reset-cells = <1>;
657 #power-domain-cells = <1>;
658 };
659
660 usb_hsphy: phy@1613000 {
661 compatible = "qcom,qcm2290-qusb2-phy";
662 reg = <0x0 0x01613000 0x0 0x180>;
663
664 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
665 <&rpmcc RPM_SMD_XO_CLK_SRC>;
666 clock-names = "cfg_ahb", "ref";
667
668 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
669 nvmem-cells = <&qusb2_hstx_trim>;
670 #phy-cells = <0>;
671
672 status = "disabled";
673 };
674
675 usb_qmpphy: phy@1615000 {
676 compatible = "qcom,qcm2290-qmp-usb3-phy";
677 reg = <0x0 0x01615000 0x0 0x1000>;
678
679 clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
680 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
681 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
682 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
683 clock-names = "cfg_ahb",
684 "ref",
685 "com_aux",
686 "pipe";
687
688 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
689 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
690 reset-names = "phy",
691 "phy_phy";
692
693 #clock-cells = <0>;
694 clock-output-names = "usb3_phy_pipe_clk_src";
695
696 #phy-cells = <0>;
697
698 qcom,tcsr-reg = <&tcsr_regs 0xb244>;
699
700 status = "disabled";
701 };
702
703 system_noc: interconnect@1880000 {
704 compatible = "qcom,qcm2290-snoc";
705 reg = <0x0 0x01880000 0x0 0x60200>;
706 #interconnect-cells = <2>;
707
708 qup_virt: interconnect-qup {
709 compatible = "qcom,qcm2290-qup-virt";
710 #interconnect-cells = <2>;
711 };
712
713 mmnrt_virt: interconnect-mmnrt {
714 compatible = "qcom,qcm2290-mmnrt-virt";
715 #interconnect-cells = <2>;
716 };
717
718 mmrt_virt: interconnect-mmrt {
719 compatible = "qcom,qcm2290-mmrt-virt";
720 #interconnect-cells = <2>;
721 };
722 };
723
724 config_noc: interconnect@1900000 {
725 compatible = "qcom,qcm2290-cnoc";
726 reg = <0x0 0x01900000 0x0 0x8200>;
727 #interconnect-cells = <2>;
728 };
729
730 qfprom@1b44000 {
731 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom";
732 reg = <0x0 0x01b44000 0x0 0x3000>;
733 #address-cells = <1>;
734 #size-cells = <1>;
735
736 qusb2_hstx_trim: hstx-trim@25b {
737 reg = <0x25b 0x1>;
738 bits = <1 4>;
739 };
740 };
741
742 pmu@1b8e300 {
743 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon";
744 reg = <0x0 0x01b8e300 0x0 0x600>;
745 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
746
747 operating-points-v2 = <&cpu_bwmon_opp_table>;
748 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG
749 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>;
750
751 cpu_bwmon_opp_table: opp-table {
752 compatible = "operating-points-v2";
753
754 opp-0 {
755 opp-peak-kBps = <(200 * 4 * 1000)>;
756 };
757
758 opp-1 {
759 opp-peak-kBps = <(300 * 4 * 1000)>;
760 };
761
762 opp-2 {
763 opp-peak-kBps = <(451 * 4 * 1000)>;
764 };
765
766 opp-3 {
767 opp-peak-kBps = <(547 * 4 * 1000)>;
768 };
769
770 opp-4 {
771 opp-peak-kBps = <(681 * 4 * 1000)>;
772 };
773
774 opp-5 {
775 opp-peak-kBps = <(768 * 4 * 1000)>;
776 };
777
778 opp-6 {
779 opp-peak-kBps = <(1017 * 4 * 1000)>;
780 };
781
782 opp-7 {
783 opp-peak-kBps = <(1353 * 4 * 1000)>;
784 };
785
786 opp-8 {
787 opp-peak-kBps = <(1555 * 4 * 1000)>;
788 };
789
790 opp-9 {
791 opp-peak-kBps = <(1804 * 4 * 1000)>;
792 };
793 };
794 };
795
796 spmi_bus: spmi@1c40000 {
797 compatible = "qcom,spmi-pmic-arb";
798 reg = <0x0 0x01c40000 0x0 0x1100>,
799 <0x0 0x01e00000 0x0 0x2000000>,
800 <0x0 0x03e00000 0x0 0x100000>,
801 <0x0 0x03f00000 0x0 0xa0000>,
802 <0x0 0x01c0a000 0x0 0x26000>;
803 reg-names = "core",
804 "chnls",
805 "obsrvr",
806 "intr",
807 "cnfg";
808 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>;
809 interrupt-names = "periph_irq";
810 qcom,ee = <0>;
811 qcom,channel = <0>;
812 #address-cells = <2>;
813 #size-cells = <0>;
814 interrupt-controller;
815 #interrupt-cells = <4>;
816 };
817
818 tsens0: thermal-sensor@4411000 {
819 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2";
820 reg = <0x0 0x04411000 0x0 0x1ff>,
821 <0x0 0x04410000 0x0 0x8>;
822 #qcom,sensors = <10>;
823 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>,
824 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
825 interrupt-names = "uplow", "critical";
826 #thermal-sensor-cells = <1>;
827 };
828
829 rng: rng@4453000 {
830 compatible = "qcom,prng-ee";
831 reg = <0x0 0x04453000 0x0 0x1000>;
832 clocks = <&rpmcc RPM_SMD_HWKM_CLK>;
833 clock-names = "core";
834 };
835
836 bimc: interconnect@4480000 {
837 compatible = "qcom,qcm2290-bimc";
838 reg = <0x0 0x04480000 0x0 0x80000>;
839 #interconnect-cells = <2>;
840 };
841
842 rpm_msg_ram: sram@45f0000 {
843 compatible = "qcom,rpm-msg-ram", "mmio-sram";
844 reg = <0x0 0x045f0000 0x0 0x7000>;
845 #address-cells = <1>;
846 #size-cells = <1>;
847 ranges = <0 0x0 0x045f0000 0x7000>;
848
849 apss_mpm: sram@1b8 {
850 reg = <0x1b8 0x48>;
851 };
852 };
853
854 sram@4690000 {
855 compatible = "qcom,rpm-stats";
856 reg = <0x0 0x04690000 0x0 0x10000>;
857 };
858
859 sdhc_1: mmc@4744000 {
860 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
861 reg = <0x0 0x04744000 0x0 0x1000>,
862 <0x0 0x04745000 0x0 0x1000>,
863 <0x0 0x04748000 0x0 0x8000>;
864 reg-names = "hc",
865 "cqhci",
866 "ice";
867
868 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
870 interrupt-names = "hc_irq", "pwr_irq";
871
872 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
873 <&gcc GCC_SDCC1_APPS_CLK>,
874 <&rpmcc RPM_SMD_XO_CLK_SRC>,
875 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
876 clock-names = "iface",
877 "core",
878 "xo",
879 "ice";
880
881 resets = <&gcc GCC_SDCC1_BCR>;
882
883 power-domains = <&rpmpd QCM2290_VDDCX>;
884 operating-points-v2 = <&sdhc1_opp_table>;
885 iommus = <&apps_smmu 0xc0 0x0>;
886 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
887 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
888 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
889 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
890 interconnect-names = "sdhc-ddr",
891 "cpu-sdhc";
892
893 qcom,dll-config = <0x000f642c>;
894 qcom,ddr-config = <0x80040868>;
895 bus-width = <8>;
896
897 status = "disabled";
898
899 sdhc1_opp_table: opp-table {
900 compatible = "operating-points-v2";
901
902 opp-100000000 {
903 opp-hz = /bits/ 64 <100000000>;
904 required-opps = <&rpmpd_opp_low_svs>;
905 opp-peak-kBps = <250000 133320>;
906 opp-avg-kBps = <102400 65000>;
907 };
908
909 opp-192000000 {
910 opp-hz = /bits/ 64 <192000000>;
911 required-opps = <&rpmpd_opp_low_svs>;
912 opp-peak-kBps = <800000 300000>;
913 opp-avg-kBps = <204800 200000>;
914 };
915
916 opp-384000000 {
917 opp-hz = /bits/ 64 <384000000>;
918 required-opps = <&rpmpd_opp_svs_plus>;
919 opp-peak-kBps = <800000 300000>;
920 opp-avg-kBps = <204800 200000>;
921 };
922 };
923 };
924
925 sdhc_2: mmc@4784000 {
926 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5";
927 reg = <0x0 0x04784000 0x0 0x1000>;
928 reg-names = "hc";
929
930 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
932 interrupt-names = "hc_irq", "pwr_irq";
933
934 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
935 <&gcc GCC_SDCC2_APPS_CLK>,
936 <&rpmcc RPM_SMD_XO_CLK_SRC>;
937 clock-names = "iface",
938 "core",
939 "xo";
940
941 resets = <&gcc GCC_SDCC2_BCR>;
942
943 power-domains = <&rpmpd QCM2290_VDDCX>;
944 operating-points-v2 = <&sdhc2_opp_table>;
945 iommus = <&apps_smmu 0xa0 0x0>;
946 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
947 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
948 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
949 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
950 interconnect-names = "sdhc-ddr",
951 "cpu-sdhc";
952
953 qcom,dll-config = <0x0007642c>;
954 qcom,ddr-config = <0x80040868>;
955 bus-width = <4>;
956
957 status = "disabled";
958
959 sdhc2_opp_table: opp-table {
960 compatible = "operating-points-v2";
961
962 opp-100000000 {
963 opp-hz = /bits/ 64 <100000000>;
964 required-opps = <&rpmpd_opp_low_svs>;
965 opp-peak-kBps = <250000 133320>;
966 opp-avg-kBps = <261438 150000>;
967 };
968
969 opp-202000000 {
970 opp-hz = /bits/ 64 <202000000>;
971 required-opps = <&rpmpd_opp_svs_plus>;
972 opp-peak-kBps = <800000 300000>;
973 opp-avg-kBps = <261438 300000>;
974 };
975 };
976 };
977
978 gpi_dma0: dma-controller@4a00000 {
979 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma";
980 reg = <0x0 0x04a00000 0x0 0x60000>;
981 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
991 dma-channels = <10>;
992 dma-channel-mask = <0x1f>;
993 iommus = <&apps_smmu 0xf6 0x0>;
994 #dma-cells = <3>;
995 status = "disabled";
996 };
997
998 qupv3_id_0: geniqup@4ac0000 {
999 compatible = "qcom,geni-se-qup";
1000 reg = <0x0 0x04ac0000 0x0 0x2000>;
1001 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1002 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1003 clock-names = "m-ahb", "s-ahb";
1004 iommus = <&apps_smmu 0xe3 0x0>;
1005 #address-cells = <2>;
1006 #size-cells = <2>;
1007 ranges;
1008 status = "disabled";
1009
1010 i2c0: i2c@4a80000 {
1011 compatible = "qcom,geni-i2c";
1012 reg = <0x0 0x04a80000 0x0 0x4000>;
1013 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1015 clock-names = "se";
1016 pinctrl-0 = <&qup_i2c0_default>;
1017 pinctrl-names = "default";
1018 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1019 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1020 dma-names = "tx", "rx";
1021 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1022 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1023 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1024 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1025 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1026 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1027 interconnect-names = "qup-core",
1028 "qup-config",
1029 "qup-memory";
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032 status = "disabled";
1033 };
1034
1035 spi0: spi@4a80000 {
1036 compatible = "qcom,geni-spi";
1037 reg = <0x0 0x04a80000 0x0 0x4000>;
1038 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1039 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1040 clock-names = "se";
1041 pinctrl-0 = <&qup_spi0_default>;
1042 pinctrl-names = "default";
1043 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1044 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1045 dma-names = "tx", "rx";
1046 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1047 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1048 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1049 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1050 interconnect-names = "qup-core",
1051 "qup-config";
1052 #address-cells = <1>;
1053 #size-cells = <0>;
1054 status = "disabled";
1055 };
1056
1057 uart0: serial@4a80000 {
1058 compatible = "qcom,geni-uart";
1059 reg = <0x0 0x04a80000 0x0 0x4000>;
1060 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1061 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1062 clock-names = "se";
1063 pinctrl-0 = <&qup_uart0_default>;
1064 pinctrl-names = "default";
1065 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1066 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1067 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1068 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1069 interconnect-names = "qup-core",
1070 "qup-config";
1071 status = "disabled";
1072 };
1073
1074 i2c1: i2c@4a84000 {
1075 compatible = "qcom,geni-i2c";
1076 reg = <0x0 0x04a84000 0x0 0x4000>;
1077 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1078 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1079 clock-names = "se";
1080 pinctrl-0 = <&qup_i2c1_default>;
1081 pinctrl-names = "default";
1082 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1083 <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1084 dma-names = "tx", "rx";
1085 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1086 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1087 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1088 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1089 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1090 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1091 interconnect-names = "qup-core",
1092 "qup-config",
1093 "qup-memory";
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1096 status = "disabled";
1097 };
1098
1099 spi1: spi@4a84000 {
1100 compatible = "qcom,geni-spi";
1101 reg = <0x0 0x04a84000 0x0 0x4000>;
1102 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1103 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1104 clock-names = "se";
1105 pinctrl-0 = <&qup_spi1_default>;
1106 pinctrl-names = "default";
1107 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1108 <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1109 dma-names = "tx", "rx";
1110 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1111 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1112 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1113 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1114 interconnect-names = "qup-core",
1115 "qup-config";
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 status = "disabled";
1119 };
1120
1121 i2c2: i2c@4a88000 {
1122 compatible = "qcom,geni-i2c";
1123 reg = <0x0 0x04a88000 0x0 0x4000>;
1124 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1126 clock-names = "se";
1127 pinctrl-0 = <&qup_i2c2_default>;
1128 pinctrl-names = "default";
1129 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1130 <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1131 dma-names = "tx", "rx";
1132 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1133 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1134 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1135 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1136 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1137 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1138 interconnect-names = "qup-core",
1139 "qup-config",
1140 "qup-memory";
1141 #address-cells = <1>;
1142 #size-cells = <0>;
1143 status = "disabled";
1144 };
1145
1146 spi2: spi@4a88000 {
1147 compatible = "qcom,geni-spi";
1148 reg = <0x0 0x04a88000 0x0 0x4000>;
1149 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1151 clock-names = "se";
1152 pinctrl-0 = <&qup_spi2_default>;
1153 pinctrl-names = "default";
1154 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1155 <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1156 dma-names = "tx", "rx";
1157 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1158 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1159 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1160 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1161 interconnect-names = "qup-core",
1162 "qup-config";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1165 status = "disabled";
1166 };
1167
1168 i2c3: i2c@4a8c000 {
1169 compatible = "qcom,geni-i2c";
1170 reg = <0x0 0x04a8c000 0x0 0x4000>;
1171 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1172 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1173 clock-names = "se";
1174 pinctrl-0 = <&qup_i2c3_default>;
1175 pinctrl-names = "default";
1176 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1177 <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1178 dma-names = "tx", "rx";
1179 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1180 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1181 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1182 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1183 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1184 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1185 interconnect-names = "qup-core",
1186 "qup-config",
1187 "qup-memory";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1190 status = "disabled";
1191 };
1192
1193 spi3: spi@4a8c000 {
1194 compatible = "qcom,geni-spi";
1195 reg = <0x0 0x04a8c000 0x0 0x4000>;
1196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1198 clock-names = "se";
1199 pinctrl-0 = <&qup_spi3_default>;
1200 pinctrl-names = "default";
1201 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1202 <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1203 dma-names = "tx", "rx";
1204 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1205 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1206 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1207 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1208 interconnect-names = "qup-core",
1209 "qup-config";
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 status = "disabled";
1213 };
1214
1215 i2c4: i2c@4a90000 {
1216 compatible = "qcom,geni-i2c";
1217 reg = <0x0 0x04a90000 0x0 0x4000>;
1218 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1220 clock-names = "se";
1221 pinctrl-0 = <&qup_i2c4_default>;
1222 pinctrl-names = "default";
1223 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1224 <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1225 dma-names = "tx", "rx";
1226 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1227 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1228 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1229 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1230 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1231 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1232 interconnect-names = "qup-core",
1233 "qup-config",
1234 "qup-memory";
1235 #address-cells = <1>;
1236 #size-cells = <0>;
1237 status = "disabled";
1238 };
1239
1240 spi4: spi@4a90000 {
1241 compatible = "qcom,geni-spi";
1242 reg = <0x0 0x04a90000 0x0 0x4000>;
1243 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1244 clock-names = "se";
1245 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1246 pinctrl-names = "default";
1247 pinctrl-0 = <&qup_spi4_default>;
1248 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1249 <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1250 dma-names = "tx", "rx";
1251 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1252 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1253 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1254 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1255 interconnect-names = "qup-core",
1256 "qup-config";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1259 status = "disabled";
1260 };
1261
1262 uart4: serial@4a90000 {
1263 compatible = "qcom,geni-uart";
1264 reg = <0x0 0x04a90000 0x0 0x4000>;
1265 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1267 clock-names = "se";
1268 pinctrl-0 = <&qup_uart4_default>;
1269 pinctrl-names = "default";
1270 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1271 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1272 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1273 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1274 interconnect-names = "qup-core",
1275 "qup-config";
1276 status = "disabled";
1277 };
1278
1279 i2c5: i2c@4a94000 {
1280 compatible = "qcom,geni-i2c";
1281 reg = <0x0 0x04a94000 0x0 0x4000>;
1282 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1283 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1284 clock-names = "se";
1285 pinctrl-0 = <&qup_i2c5_default>;
1286 pinctrl-names = "default";
1287 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1288 <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1289 dma-names = "tx", "rx";
1290 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1291 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1292 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1293 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1294 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1295 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>;
1296 interconnect-names = "qup-core",
1297 "qup-config",
1298 "qup-memory";
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 status = "disabled";
1302 };
1303
1304 spi5: spi@4a94000 {
1305 compatible = "qcom,geni-spi";
1306 reg = <0x0 0x04a94000 0x0 0x4000>;
1307 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1308 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1309 clock-names = "se";
1310 pinctrl-0 = <&qup_spi5_default>;
1311 pinctrl-names = "default";
1312 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1313 <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1314 dma-names = "tx", "rx";
1315 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1316 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1317 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1318 &config_noc MASTER_APPSS_PROC RPM_ALWAYS_TAG>;
1319 interconnect-names = "qup-core",
1320 "qup-config";
1321 #address-cells = <1>;
1322 #size-cells = <0>;
1323 status = "disabled";
1324 };
1325 };
1326
1327 usb: usb@4ef8800 {
1328 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3";
1329 reg = <0x0 0x04ef8800 0x0 0x400>;
1330 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1331 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "hs_phy_irq",
1333 "ss_phy_irq";
1334
1335 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1336 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1337 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1338 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1339 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1340 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1341 clock-names = "cfg_noc",
1342 "core",
1343 "iface",
1344 "sleep",
1345 "mock_utmi",
1346 "xo";
1347
1348 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1349 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1350 assigned-clock-rates = <19200000>, <133333333>;
1351
1352 resets = <&gcc GCC_USB30_PRIM_BCR>;
1353 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1354 /* TODO: USB<->IPA path */
1355 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG
1356 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1357 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1358 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1359 interconnect-names = "usb-ddr",
1360 "apps-usb";
1361 wakeup-source;
1362
1363 #address-cells = <2>;
1364 #size-cells = <2>;
1365 ranges;
1366
1367 status = "disabled";
1368
1369 usb_dwc3: usb@4e00000 {
1370 compatible = "snps,dwc3";
1371 reg = <0x0 0x04e00000 0x0 0xcd00>;
1372 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1373 phys = <&usb_hsphy>, <&usb_qmpphy>;
1374 phy-names = "usb2-phy", "usb3-phy";
1375 iommus = <&apps_smmu 0x120 0x0>;
1376 snps,dis_u2_susphy_quirk;
1377 snps,dis_enblslpm_quirk;
1378 snps,has-lpm-erratum;
1379 snps,hird-threshold = /bits/ 8 <0x10>;
1380 snps,usb3_lpm_capable;
1381 maximum-speed = "super-speed";
1382 dr_mode = "otg";
1383 };
1384 };
1385
1386 mdss: display-subsystem@5e00000 {
1387 compatible = "qcom,qcm2290-mdss";
1388 reg = <0x0 0x05e00000 0x0 0x1000>;
1389 reg-names = "mdss";
1390 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1391 interrupt-controller;
1392 #interrupt-cells = <1>;
1393
1394 clocks = <&gcc GCC_DISP_AHB_CLK>,
1395 <&gcc GCC_DISP_HF_AXI_CLK>,
1396 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1397 clock-names = "iface",
1398 "bus",
1399 "core";
1400
1401 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
1402
1403 power-domains = <&dispcc MDSS_GDSC>;
1404
1405 iommus = <&apps_smmu 0x420 0x2>,
1406 <&apps_smmu 0x421 0x0>;
1407 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG
1408 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>,
1409 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG
1410 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1411 interconnect-names = "mdp0-mem",
1412 "cpu-cfg";
1413
1414 #address-cells = <2>;
1415 #size-cells = <2>;
1416 ranges;
1417
1418 status = "disabled";
1419
1420 mdp: display-controller@5e01000 {
1421 compatible = "qcom,qcm2290-dpu";
1422 reg = <0x0 0x05e01000 0x0 0x8f000>,
1423 <0x0 0x05eb0000 0x0 0x2008>;
1424 reg-names = "mdp",
1425 "vbif";
1426
1427 interrupt-parent = <&mdss>;
1428 interrupts = <0>;
1429
1430 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1431 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1432 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1433 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1434 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1435 clock-names = "bus",
1436 "iface",
1437 "core",
1438 "lut",
1439 "vsync";
1440
1441 operating-points-v2 = <&mdp_opp_table>;
1442 power-domains = <&rpmpd QCM2290_VDDCX>;
1443
1444 ports {
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447
1448 port@0 {
1449 reg = <0>;
1450 dpu_intf1_out: endpoint {
1451 remote-endpoint = <&mdss_dsi0_in>;
1452 };
1453 };
1454 };
1455
1456 mdp_opp_table: opp-table {
1457 compatible = "operating-points-v2";
1458
1459 opp-19200000 {
1460 opp-hz = /bits/ 64 <19200000>;
1461 required-opps = <&rpmpd_opp_min_svs>;
1462 };
1463
1464 opp-192000000 {
1465 opp-hz = /bits/ 64 <192000000>;
1466 required-opps = <&rpmpd_opp_low_svs>;
1467 };
1468
1469 opp-256000000 {
1470 opp-hz = /bits/ 64 <256000000>;
1471 required-opps = <&rpmpd_opp_svs>;
1472 };
1473
1474 opp-307200000 {
1475 opp-hz = /bits/ 64 <307200000>;
1476 required-opps = <&rpmpd_opp_svs_plus>;
1477 };
1478
1479 opp-384000000 {
1480 opp-hz = /bits/ 64 <384000000>;
1481 required-opps = <&rpmpd_opp_nom>;
1482 };
1483 };
1484 };
1485
1486 mdss_dsi0: dsi@5e94000 {
1487 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1488 reg = <0x0 0x05e94000 0x0 0x400>;
1489 reg-names = "dsi_ctrl";
1490
1491 interrupt-parent = <&mdss>;
1492 interrupts = <4>;
1493
1494 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1495 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1496 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1497 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1498 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1499 <&gcc GCC_DISP_HF_AXI_CLK>;
1500 clock-names = "byte",
1501 "byte_intf",
1502 "pixel",
1503 "core",
1504 "iface",
1505 "bus";
1506
1507 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1508 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1509 assigned-clock-parents = <&mdss_dsi0_phy 0>,
1510 <&mdss_dsi0_phy 1>;
1511
1512 operating-points-v2 = <&dsi_opp_table>;
1513 power-domains = <&rpmpd QCM2290_VDDCX>;
1514 phys = <&mdss_dsi0_phy>;
1515
1516 #address-cells = <1>;
1517 #size-cells = <0>;
1518
1519 status = "disabled";
1520
1521 dsi_opp_table: opp-table {
1522 compatible = "operating-points-v2";
1523
1524 opp-19200000 {
1525 opp-hz = /bits/ 64 <19200000>;
1526 required-opps = <&rpmpd_opp_min_svs>;
1527 };
1528
1529 opp-164000000 {
1530 opp-hz = /bits/ 64 <164000000>;
1531 required-opps = <&rpmpd_opp_low_svs>;
1532 };
1533
1534 opp-187500000 {
1535 opp-hz = /bits/ 64 <187500000>;
1536 required-opps = <&rpmpd_opp_svs>;
1537 };
1538 };
1539
1540 ports {
1541 #address-cells = <1>;
1542 #size-cells = <0>;
1543
1544 port@0 {
1545 reg = <0>;
1546
1547 mdss_dsi0_in: endpoint {
1548 remote-endpoint = <&dpu_intf1_out>;
1549 };
1550 };
1551
1552 port@1 {
1553 reg = <1>;
1554
1555 mdss_dsi0_out: endpoint {
1556 };
1557 };
1558 };
1559 };
1560
1561 mdss_dsi0_phy: phy@5e94400 {
1562 compatible = "qcom,dsi-phy-14nm-2290";
1563 reg = <0x0 0x05e94400 0x0 0x100>,
1564 <0x0 0x05e94500 0x0 0x300>,
1565 <0x0 0x05e94800 0x0 0x188>;
1566 reg-names = "dsi_phy",
1567 "dsi_phy_lane",
1568 "dsi_pll";
1569
1570 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
1571 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1572 clock-names = "iface",
1573 "ref";
1574
1575 power-domains = <&rpmpd QCM2290_VDDMX>;
1576 required-opps = <&rpmpd_opp_nom>;
1577
1578 #clock-cells = <1>;
1579 #phy-cells = <0>;
1580
1581 status = "disabled";
1582 };
1583 };
1584
1585 dispcc: clock-controller@5f00000 {
1586 compatible = "qcom,qcm2290-dispcc";
1587 reg = <0x0 0x05f00000 0x0 0x20000>;
1588 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1589 <&rpmcc RPM_SMD_XO_A_CLK_SRC>,
1590 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
1591 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
1592 <&mdss_dsi0_phy 0>,
1593 <&mdss_dsi0_phy 1>;
1594 clock-names = "bi_tcxo",
1595 "bi_tcxo_ao",
1596 "gcc_disp_gpll0_clk_src",
1597 "gcc_disp_gpll0_div_clk_src",
1598 "dsi0_phy_pll_out_byteclk",
1599 "dsi0_phy_pll_out_dsiclk";
1600 #power-domain-cells = <1>;
1601 #clock-cells = <1>;
1602 #reset-cells = <1>;
1603 };
1604
1605 remoteproc_mpss: remoteproc@6080000 {
1606 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas";
1607 reg = <0x0 0x06080000 0x0 0x100>;
1608
1609 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
1610 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1611 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1612 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1613 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1614 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1615 interrupt-names = "wdog",
1616 "fatal",
1617 "ready",
1618 "handover",
1619 "stop-ack",
1620 "shutdown-ack";
1621
1622 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1623 clock-names = "xo";
1624
1625 power-domains = <&rpmpd QCM2290_VDDCX>;
1626
1627 memory-region = <&pil_modem_mem>;
1628
1629 qcom,smem-states = <&modem_smp2p_out 0>;
1630 qcom,smem-state-names = "stop";
1631
1632 status = "disabled";
1633
1634 glink-edge {
1635 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
1636 label = "mpss";
1637 qcom,remote-pid = <1>;
1638 mboxes = <&apcs_glb 12>;
1639 };
1640 };
1641
1642 remoteproc_adsp: remoteproc@ab00000 {
1643 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas";
1644 reg = <0x0 0x0ab00000 0x0 0x100>;
1645
1646 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
1647 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1648 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1649 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1650 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1651 interrupt-names = "wdog",
1652 "fatal",
1653 "ready",
1654 "handover",
1655 "stop-ack";
1656
1657 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
1658 clock-names = "xo";
1659
1660 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>,
1661 <&rpmpd QCM2290_VDD_LPI_MX>;
1662
1663 memory-region = <&pil_adsp_mem>;
1664
1665 qcom,smem-states = <&adsp_smp2p_out 0>;
1666 qcom,smem-state-names = "stop";
1667
1668 status = "disabled";
1669
1670 glink-edge {
1671 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
1672 label = "lpass";
1673 qcom,remote-pid = <2>;
1674 mboxes = <&apcs_glb 8>;
1675 };
1676 };
1677
1678 apps_smmu: iommu@c600000 {
1679 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1680 reg = <0x0 0x0c600000 0x0 0x80000>;
1681 #iommu-cells = <2>;
1682 #global-interrupts = <1>;
1683
1684 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1686 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1687 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1691 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1693 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1694 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1695 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1696 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1716 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1718 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1719 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1722 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1746 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1747 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1748 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
1749 };
1750
1751 wifi: wifi@c800000 {
1752 compatible = "qcom,wcn3990-wifi";
1753 reg = <0x0 0x0c800000 0x0 0x800000>;
1754 reg-names = "membase";
1755 memory-region = <&wlan_msa_mem>;
1756 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
1757 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
1768 iommus = <&apps_smmu 0x1a0 0x1>;
1769 qcom,msa-fixed-perm;
1770 status = "disabled";
1771 };
1772
1773 watchdog@f017000 {
1774 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt";
1775 reg = <0x0 0x0f017000 0x0 0x1000>;
1776 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>,
1777 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1778 clocks = <&sleep_clk>;
1779 };
1780
1781 apcs_glb: mailbox@f111000 {
1782 compatible = "qcom,qcm2290-apcs-hmss-global";
1783 reg = <0x0 0x0f111000 0x0 0x1000>;
1784 #mbox-cells = <1>;
1785 };
1786
1787 timer@f120000 {
1788 compatible = "arm,armv7-timer-mem";
1789 reg = <0x0 0x0f120000 0x0 0x1000>;
1790 #address-cells = <1>;
1791 #size-cells = <1>;
1792 ranges = <0 0x0 0x0f121000 0x8000>;
1793
1794 frame@0 {
1795 reg = <0x0 0x1000>,
1796 <0x1000 0x1000>;
1797 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1799 frame-number = <0>;
1800 };
1801
1802 frame@2000 {
1803 reg = <0x2000 0x1000>;
1804 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1805 frame-number = <1>;
1806 status = "disabled";
1807 };
1808
1809 frame@3000 {
1810 reg = <0x3000 0x1000>;
1811 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1812 frame-number = <2>;
1813 status = "disabled";
1814 };
1815
1816 frame@4000 {
1817 reg = <0x4000 0x1000>;
1818 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1819 frame-number = <3>;
1820 status = "disabled";
1821 };
1822
1823 frame@5000 {
1824 reg = <0x5000 0x1000>;
1825 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1826 frame-number = <4>;
1827 status = "disabled";
1828 };
1829
1830 frame@6000 {
1831 reg = <0x6000 0x1000>;
1832 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1833 frame-number = <5>;
1834 status = "disabled";
1835 };
1836
1837 frame@7000 {
1838 reg = <0x7000 0x1000>;
1839 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1840 frame-number = <6>;
1841 status = "disabled";
1842 };
1843 };
1844
1845 intc: interrupt-controller@f200000 {
1846 compatible = "arm,gic-v3";
1847 reg = <0x0 0x0f200000 0x0 0x10000>,
1848 <0x0 0x0f300000 0x0 0x100000>;
1849 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1850 #interrupt-cells = <3>;
1851 interrupt-controller;
1852 interrupt-parent = <&intc>;
1853 #redistributor-regions = <1>;
1854 redistributor-stride = <0x0 0x20000>;
1855 };
1856
1857 cpufreq_hw: cpufreq@f521000 {
1858 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw";
1859 reg = <0x0 0x0f521000 0x0 0x1000>;
1860 reg-names = "freq-domain0";
1861 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1862 interrupt-names = "dcvsh-irq-0";
1863 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
1864 clock-names = "xo", "alternate";
1865
1866 #freq-domain-cells = <1>;
1867 #clock-cells = <1>;
1868 };
1869 };
1870
1871 thermal-zones {
1872 mapss-thermal {
1873 polling-delay-passive = <0>;
1874 polling-delay = <0>;
1875
1876 thermal-sensors = <&tsens0 0>;
1877
1878 trips {
1879 mapss_alert0: trip-point0 {
1880 temperature = <90000>;
1881 hysteresis = <2000>;
1882 type = "passive";
1883 };
1884
1885 mapss_alert1: trip-point1 {
1886 temperature = <95000>;
1887 hysteresis = <2000>;
1888 type = "passive";
1889 };
1890
1891 mapss_crit: mapss-crit {
1892 temperature = <110000>;
1893 hysteresis = <1000>;
1894 type = "critical";
1895 };
1896 };
1897 };
1898
1899 video-thermal {
1900 polling-delay-passive = <0>;
1901 polling-delay = <0>;
1902
1903 thermal-sensors = <&tsens0 1>;
1904
1905 trips {
1906 video_alert0: trip-point0 {
1907 temperature = <90000>;
1908 hysteresis = <2000>;
1909 type = "passive";
1910 };
1911
1912 video_alert1: trip-point1 {
1913 temperature = <95000>;
1914 hysteresis = <2000>;
1915 type = "passive";
1916 };
1917
1918 video_crit: video-crit {
1919 temperature = <110000>;
1920 hysteresis = <1000>;
1921 type = "critical";
1922 };
1923 };
1924 };
1925
1926 wlan-thermal {
1927 polling-delay-passive = <0>;
1928 polling-delay = <0>;
1929
1930 thermal-sensors = <&tsens0 2>;
1931
1932 trips {
1933 wlan_alert0: trip-point0 {
1934 temperature = <90000>;
1935 hysteresis = <2000>;
1936 type = "passive";
1937 };
1938
1939 wlan_alert1: trip-point1 {
1940 temperature = <95000>;
1941 hysteresis = <2000>;
1942 type = "passive";
1943 };
1944
1945 wlan_crit: wlan-crit {
1946 temperature = <110000>;
1947 hysteresis = <1000>;
1948 type = "critical";
1949 };
1950 };
1951 };
1952
1953 cpuss0-thermal {
1954 polling-delay-passive = <0>;
1955 polling-delay = <0>;
1956
1957 thermal-sensors = <&tsens0 3>;
1958
1959 trips {
1960 cpuss0_alert0: trip-point0 {
1961 temperature = <90000>;
1962 hysteresis = <2000>;
1963 type = "passive";
1964 };
1965
1966 cpuss0_alert1: trip-point1 {
1967 temperature = <95000>;
1968 hysteresis = <2000>;
1969 type = "passive";
1970 };
1971
1972 cpuss0_crit: cpuss0-crit {
1973 temperature = <110000>;
1974 hysteresis = <1000>;
1975 type = "critical";
1976 };
1977 };
1978 };
1979
1980 cpuss1-thermal {
1981 polling-delay-passive = <0>;
1982 polling-delay = <0>;
1983
1984 thermal-sensors = <&tsens0 4>;
1985
1986 trips {
1987 cpuss1_alert0: trip-point0 {
1988 temperature = <90000>;
1989 hysteresis = <2000>;
1990 type = "passive";
1991 };
1992
1993 cpuss1_alert1: trip-point1 {
1994 temperature = <95000>;
1995 hysteresis = <2000>;
1996 type = "passive";
1997 };
1998
1999 cpuss1_crit: cpuss1-crit {
2000 temperature = <110000>;
2001 hysteresis = <1000>;
2002 type = "critical";
2003 };
2004 };
2005 };
2006
2007 mdm0-thermal {
2008 polling-delay-passive = <0>;
2009 polling-delay = <0>;
2010
2011 thermal-sensors = <&tsens0 5>;
2012
2013 trips {
2014 mdm0_alert0: trip-point0 {
2015 temperature = <90000>;
2016 hysteresis = <2000>;
2017 type = "passive";
2018 };
2019
2020 mdm0_alert1: trip-point1 {
2021 temperature = <95000>;
2022 hysteresis = <2000>;
2023 type = "passive";
2024 };
2025
2026 mdm0_crit: mdm0-crit {
2027 temperature = <110000>;
2028 hysteresis = <1000>;
2029 type = "critical";
2030 };
2031 };
2032 };
2033
2034 mdm1-thermal {
2035 polling-delay-passive = <0>;
2036 polling-delay = <0>;
2037
2038 thermal-sensors = <&tsens0 6>;
2039
2040 trips {
2041 mdm1_alert0: trip-point0 {
2042 temperature = <90000>;
2043 hysteresis = <2000>;
2044 type = "passive";
2045 };
2046
2047 mdm1_alert1: trip-point1 {
2048 temperature = <95000>;
2049 hysteresis = <2000>;
2050 type = "passive";
2051 };
2052
2053 mdm1_crit: mdm1-crit {
2054 temperature = <110000>;
2055 hysteresis = <1000>;
2056 type = "critical";
2057 };
2058 };
2059 };
2060
2061 gpu-thermal {
2062 polling-delay-passive = <0>;
2063 polling-delay = <0>;
2064
2065 thermal-sensors = <&tsens0 7>;
2066
2067 trips {
2068 gpu_alert0: trip-point0 {
2069 temperature = <90000>;
2070 hysteresis = <2000>;
2071 type = "passive";
2072 };
2073
2074 gpu_alert1: trip-point1 {
2075 temperature = <95000>;
2076 hysteresis = <2000>;
2077 type = "passive";
2078 };
2079
2080 gpu_crit: gpu-crit {
2081 temperature = <110000>;
2082 hysteresis = <1000>;
2083 type = "critical";
2084 };
2085 };
2086 };
2087
2088 hm-center-thermal {
2089 polling-delay-passive = <0>;
2090 polling-delay = <0>;
2091
2092 thermal-sensors = <&tsens0 8>;
2093
2094 trips {
2095 hm_center_alert0: trip-point0 {
2096 temperature = <90000>;
2097 hysteresis = <2000>;
2098 type = "passive";
2099 };
2100
2101 hm_center_alert1: trip-point1 {
2102 temperature = <95000>;
2103 hysteresis = <2000>;
2104 type = "passive";
2105 };
2106
2107 hm_center_crit: hm-center-crit {
2108 temperature = <110000>;
2109 hysteresis = <1000>;
2110 type = "critical";
2111 };
2112 };
2113 };
2114
2115 camera-thermal {
2116 polling-delay-passive = <0>;
2117 polling-delay = <0>;
2118
2119 thermal-sensors = <&tsens0 9>;
2120
2121 trips {
2122 camera_alert0: trip-point0 {
2123 temperature = <90000>;
2124 hysteresis = <2000>;
2125 type = "passive";
2126 };
2127
2128 camera_alert1: trip-point1 {
2129 temperature = <95000>;
2130 hysteresis = <2000>;
2131 type = "passive";
2132 };
2133
2134 camera_crit: camera-crit {
2135 temperature = <110000>;
2136 hysteresis = <1000>;
2137 type = "critical";
2138 };
2139 };
2140 };
2141 };
2142
2143 timer {
2144 compatible = "arm,armv8-timer";
2145 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2146 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2147 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2148 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2149 };
2150};