Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * OMAP2/3/4 powerdomain control
4 *
5 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
6 * Copyright (C) 2007-2011 Nokia Corporation
7 *
8 * Paul Walmsley
9 *
10 * XXX This should be moved to the mach-omap2/ directory at the earliest
11 * opportunity.
12 */
13
14#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
15#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
16
17#include <linux/types.h>
18#include <linux/list.h>
19#include <linux/spinlock.h>
20
21/* Powerdomain basic power states */
22#define PWRDM_POWER_OFF 0x0
23#define PWRDM_POWER_RET 0x1
24#define PWRDM_POWER_INACTIVE 0x2
25#define PWRDM_POWER_ON 0x3
26
27#define PWRDM_MAX_PWRSTS 4
28
29/* Powerdomain allowable state bitfields */
30#define PWRSTS_ON (1 << PWRDM_POWER_ON)
31#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
32#define PWRSTS_RET (1 << PWRDM_POWER_RET)
33#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
34
35#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
36#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
37#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
39#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
40
41
42/*
43 * Powerdomain flags (struct powerdomain.flags)
44 *
45 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
46 *
47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
49 *
50 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
51 * to a lower sleep state without waking up the powerdomain
52 */
53#define PWRDM_HAS_HDWR_SAR BIT(0)
54#define PWRDM_HAS_MPU_QUIRK BIT(1)
55#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
56
57/*
58 * Number of memory banks that are power-controllable. On OMAP4430, the
59 * maximum is 5.
60 */
61#define PWRDM_MAX_MEM_BANKS 5
62
63/*
64 * Maximum number of clockdomains that can be associated with a powerdomain.
65 * PER powerdomain on AM33XX is the worst case
66 */
67#define PWRDM_MAX_CLKDMS 11
68
69/* XXX A completely arbitrary number. What is reasonable here? */
70#define PWRDM_TRANSITION_BAILOUT 100000
71
72struct clockdomain;
73struct powerdomain;
74struct voltagedomain;
75
76/**
77 * struct powerdomain - OMAP powerdomain
78 * @name: Powerdomain name
79 * @voltdm: voltagedomain containing this powerdomain
80 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
81 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
82 * @pwrsts: Possible powerdomain power states
83 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
84 * @flags: Powerdomain flags
85 * @banks: Number of software-controllable memory banks in this powerdomain
86 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
87 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
88 * @pwrdm_clkdms: Clockdomains in this powerdomain
89 * @node: list_head linking all powerdomains
90 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
91 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
92 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
93 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
94 * in @pwrstctrl_offs
95 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
96 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
97 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
98 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
99 * in @pwrstctrl_offs
100 * @state:
101 * @state_counter:
102 * @timer:
103 * @state_timer:
104 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
105 * @_lock_flags: stored flags when @_lock is taken
106 *
107 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
108 */
109struct powerdomain {
110 const char *name;
111 union {
112 const char *name;
113 struct voltagedomain *ptr;
114 } voltdm;
115 const s16 prcm_offs;
116 const u8 pwrsts;
117 const u8 pwrsts_logic_ret;
118 const u8 flags;
119 const u8 banks;
120 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
121 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
122 const u8 prcm_partition;
123 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
124 struct list_head node;
125 struct list_head voltdm_node;
126 int state;
127 unsigned state_counter[PWRDM_MAX_PWRSTS];
128 unsigned ret_logic_off_counter;
129 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
130 spinlock_t _lock;
131 unsigned long _lock_flags;
132 const u8 pwrstctrl_offs;
133 const u8 pwrstst_offs;
134 const u32 logicretstate_mask;
135 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
136 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
138 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
139
140#ifdef CONFIG_PM_DEBUG
141 s64 timer;
142 s64 state_timer[PWRDM_MAX_PWRSTS];
143#endif
144 u32 context;
145};
146
147/**
148 * struct pwrdm_ops - Arch specific function implementations
149 * @pwrdm_set_next_pwrst: Set the target power state for a pd
150 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
151 * @pwrdm_read_pwrst: Read the current power state of a pd
152 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
153 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
154 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
155 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
156 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
157 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
158 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
159 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
160 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
161 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
162 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
163 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
164 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
165 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
166 * @pwrdm_wait_transition: Wait for a pd state transition to complete
167 * @pwrdm_has_voltdm: Check if a voltdm association is needed
168 *
169 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
170 * chips, a powerdomain's power state is not allowed to directly
171 * transition from one low-power state (e.g., CSWR) to another
172 * low-power state (e.g., OFF) without first waking up the
173 * powerdomain. This wastes energy. So OMAP4 chips support the
174 * ability to transition a powerdomain power state directly from one
175 * low-power state to another. The function pointed to by
176 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
177 * hardware powerdomain state machine to enable this feature.
178 */
179struct pwrdm_ops {
180 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
181 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
182 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
183 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
184 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
185 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
186 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
187 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
188 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
189 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
190 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
191 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
193 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
194 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
195 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
196 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
197 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
198 int (*pwrdm_has_voltdm)(void);
199 void (*pwrdm_save_context)(struct powerdomain *pwrdm);
200 void (*pwrdm_restore_context)(struct powerdomain *pwrdm);
201};
202
203int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
204int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
205int pwrdm_complete_init(void);
206
207struct powerdomain *pwrdm_lookup(const char *name);
208
209int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
210 void *user);
211
212int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
213
214int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
215
216u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
217 bool is_logic_state, u8 req_state);
218
219int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
220int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
221int pwrdm_read_pwrst(struct powerdomain *pwrdm);
222int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
223int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
224
225int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
226int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
227int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
228
229int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
230int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
231int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
232int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
233int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
234int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
235
236int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
237int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
238bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
239
240int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
241int pwrdm_state_switch(struct powerdomain *pwrdm);
242int pwrdm_pre_transition(struct powerdomain *pwrdm);
243int pwrdm_post_transition(struct powerdomain *pwrdm);
244
245extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
246
247extern void omap242x_powerdomains_init(void);
248extern void omap243x_powerdomains_init(void);
249extern void omap3xxx_powerdomains_init(void);
250extern void am33xx_powerdomains_init(void);
251extern void omap44xx_powerdomains_init(void);
252extern void omap54xx_powerdomains_init(void);
253extern void dra7xx_powerdomains_init(void);
254void am43xx_powerdomains_init(void);
255
256extern struct pwrdm_ops omap2_pwrdm_operations;
257extern struct pwrdm_ops omap3_pwrdm_operations;
258extern struct pwrdm_ops am33xx_pwrdm_operations;
259extern struct pwrdm_ops omap4_pwrdm_operations;
260
261/* Common Internal functions used across OMAP rev's */
262extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
263extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
264extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
265
266extern struct powerdomain wkup_omap2_pwrdm;
267extern struct powerdomain gfx_omap2_pwrdm;
268
269extern void pwrdm_lock(struct powerdomain *pwrdm);
270extern void pwrdm_unlock(struct powerdomain *pwrdm);
271
272#endif