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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for DRA7xx clock data
4 *
5 * Copyright (C) 2013 Texas Instruments, Inc.
6 */
7&cm_core_aon_clocks {
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
12 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
13 };
14
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
19 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
20 };
21
22 atl_clkin2_ck: clock-atl-clkin2 {
23 #clock-cells = <0>;
24 compatible = "ti,dra7-atl-clock";
25 clock-output-names = "atl_clkin2_ck";
26 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
27 };
28
29 atl_clkin3_ck: clock-atl-clkin3 {
30 #clock-cells = <0>;
31 compatible = "ti,dra7-atl-clock";
32 clock-output-names = "atl_clkin3_ck";
33 clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
34 };
35
36 hdmi_clkin_ck: clock-hdmi-clkin {
37 #clock-cells = <0>;
38 compatible = "fixed-clock";
39 clock-output-names = "hdmi_clkin_ck";
40 clock-frequency = <0>;
41 };
42
43 mlb_clkin_ck: clock-mlb-clkin {
44 #clock-cells = <0>;
45 compatible = "fixed-clock";
46 clock-output-names = "mlb_clkin_ck";
47 clock-frequency = <0>;
48 };
49
50 mlbp_clkin_ck: clock-mlbp-clkin {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-output-names = "mlbp_clkin_ck";
54 clock-frequency = <0>;
55 };
56
57 pciesref_acs_clk_ck: clock-pciesref-acs {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-output-names = "pciesref_acs_clk_ck";
61 clock-frequency = <100000000>;
62 };
63
64 ref_clkin0_ck: clock-ref-clkin0 {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-output-names = "ref_clkin0_ck";
68 clock-frequency = <0>;
69 };
70
71 ref_clkin1_ck: clock-ref-clkin1 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-output-names = "ref_clkin1_ck";
75 clock-frequency = <0>;
76 };
77
78 ref_clkin2_ck: clock-ref-clkin2 {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-output-names = "ref_clkin2_ck";
82 clock-frequency = <0>;
83 };
84
85 ref_clkin3_ck: clock-ref-clkin3 {
86 #clock-cells = <0>;
87 compatible = "fixed-clock";
88 clock-output-names = "ref_clkin3_ck";
89 clock-frequency = <0>;
90 };
91
92 rmii_clk_ck: clock-rmii {
93 #clock-cells = <0>;
94 compatible = "fixed-clock";
95 clock-output-names = "rmii_clk_ck";
96 clock-frequency = <0>;
97 };
98
99 sdvenc_clkin_ck: clock-sdvenc-clkin {
100 #clock-cells = <0>;
101 compatible = "fixed-clock";
102 clock-output-names = "sdvenc_clkin_ck";
103 clock-frequency = <0>;
104 };
105
106 secure_32k_clk_src_ck: clock-secure-32k-clk-src {
107 #clock-cells = <0>;
108 compatible = "fixed-clock";
109 clock-output-names = "secure_32k_clk_src_ck";
110 clock-frequency = <32768>;
111 };
112
113 sys_clk32_crystal_ck: clock-sys-clk32-crystal {
114 #clock-cells = <0>;
115 compatible = "fixed-clock";
116 clock-output-names = "sys_clk32_crystal_ck";
117 clock-frequency = <32768>;
118 };
119
120 sys_clk32_pseudo_ck: clock-sys-clk32-pseudo {
121 #clock-cells = <0>;
122 compatible = "fixed-factor-clock";
123 clock-output-names = "sys_clk32_pseudo_ck";
124 clocks = <&sys_clkin1>;
125 clock-mult = <1>;
126 clock-div = <610>;
127 };
128
129 virt_12000000_ck: clock-virt-12000000 {
130 #clock-cells = <0>;
131 compatible = "fixed-clock";
132 clock-output-names = "virt_12000000_ck";
133 clock-frequency = <12000000>;
134 };
135
136 virt_13000000_ck: clock-virt-13000000 {
137 #clock-cells = <0>;
138 compatible = "fixed-clock";
139 clock-output-names = "virt_13000000_ck";
140 clock-frequency = <13000000>;
141 };
142
143 virt_16800000_ck: clock-virt-16800000 {
144 #clock-cells = <0>;
145 compatible = "fixed-clock";
146 clock-output-names = "virt_16800000_ck";
147 clock-frequency = <16800000>;
148 };
149
150 virt_19200000_ck: clock-virt-19200000 {
151 #clock-cells = <0>;
152 compatible = "fixed-clock";
153 clock-output-names = "virt_19200000_ck";
154 clock-frequency = <19200000>;
155 };
156
157 virt_20000000_ck: clock-virt-20000000 {
158 #clock-cells = <0>;
159 compatible = "fixed-clock";
160 clock-output-names = "virt_20000000_ck";
161 clock-frequency = <20000000>;
162 };
163
164 virt_26000000_ck: clock-virt-26000000 {
165 #clock-cells = <0>;
166 compatible = "fixed-clock";
167 clock-output-names = "virt_26000000_ck";
168 clock-frequency = <26000000>;
169 };
170
171 virt_27000000_ck: clock-virt-27000000 {
172 #clock-cells = <0>;
173 compatible = "fixed-clock";
174 clock-output-names = "virt_27000000_ck";
175 clock-frequency = <27000000>;
176 };
177
178 virt_38400000_ck: clock-virt-38400000 {
179 #clock-cells = <0>;
180 compatible = "fixed-clock";
181 clock-output-names = "virt_38400000_ck";
182 clock-frequency = <38400000>;
183 };
184
185 sys_clkin2: clock-sys-clkin2 {
186 #clock-cells = <0>;
187 compatible = "fixed-clock";
188 clock-output-names = "sys_clkin2";
189 clock-frequency = <22579200>;
190 };
191
192 usb_otg_clkin_ck: clock-usb-otg-clkin {
193 #clock-cells = <0>;
194 compatible = "fixed-clock";
195 clock-output-names = "usb_otg_clkin_ck";
196 clock-frequency = <0>;
197 };
198
199 video1_clkin_ck: clock-video1-clkin {
200 #clock-cells = <0>;
201 compatible = "fixed-clock";
202 clock-output-names = "video1_clkin_ck";
203 clock-frequency = <0>;
204 };
205
206 video1_m2_clkin_ck: clock-video1-m2-clkin {
207 #clock-cells = <0>;
208 compatible = "fixed-clock";
209 clock-output-names = "video1_m2_clkin_ck";
210 clock-frequency = <0>;
211 };
212
213 video2_clkin_ck: clock-video2-clkin {
214 #clock-cells = <0>;
215 compatible = "fixed-clock";
216 clock-output-names = "video2_clkin_ck";
217 clock-frequency = <0>;
218 };
219
220 video2_m2_clkin_ck: clock-video2-m2-clkin {
221 #clock-cells = <0>;
222 compatible = "fixed-clock";
223 clock-output-names = "video2_m2_clkin_ck";
224 clock-frequency = <0>;
225 };
226
227 dpll_abe_ck: clock@1e0 {
228 #clock-cells = <0>;
229 compatible = "ti,omap4-dpll-m4xen-clock";
230 clock-output-names = "dpll_abe_ck";
231 clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
232 reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
233 };
234
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
236 #clock-cells = <0>;
237 compatible = "ti,omap4-dpll-x2-clock";
238 clock-output-names = "dpll_abe_x2_ck";
239 clocks = <&dpll_abe_ck>;
240 };
241
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
243 #clock-cells = <0>;
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_abe_m2x2_ck";
246 clocks = <&dpll_abe_x2_ck>;
247 ti,max-div = <31>;
248 ti,autoidle-shift = <8>;
249 reg = <0x01f0>;
250 ti,index-starts-at-one;
251 ti,invert-autoidle-bit;
252 };
253
254 abe_clk: clock-abe@108 {
255 #clock-cells = <0>;
256 compatible = "ti,divider-clock";
257 clock-output-names = "abe_clk";
258 clocks = <&dpll_abe_m2x2_ck>;
259 ti,max-div = <4>;
260 reg = <0x0108>;
261 ti,index-power-of-two;
262 };
263
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
265 #clock-cells = <0>;
266 compatible = "ti,divider-clock";
267 clock-output-names = "dpll_abe_m2_ck";
268 clocks = <&dpll_abe_ck>;
269 ti,max-div = <31>;
270 ti,autoidle-shift = <8>;
271 reg = <0x01f0>;
272 ti,index-starts-at-one;
273 ti,invert-autoidle-bit;
274 };
275
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
277 #clock-cells = <0>;
278 compatible = "ti,divider-clock";
279 clock-output-names = "dpll_abe_m3x2_ck";
280 clocks = <&dpll_abe_x2_ck>;
281 ti,max-div = <31>;
282 ti,autoidle-shift = <8>;
283 reg = <0x01f4>;
284 ti,index-starts-at-one;
285 ti,invert-autoidle-bit;
286 };
287
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
289 #clock-cells = <0>;
290 compatible = "ti,mux-clock";
291 clock-output-names = "dpll_core_byp_mux";
292 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
293 ti,bit-shift = <23>;
294 reg = <0x012c>;
295 };
296
297 dpll_core_ck: clock@120 {
298 #clock-cells = <0>;
299 compatible = "ti,omap4-dpll-core-clock";
300 clock-output-names = "dpll_core_ck";
301 clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
302 reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
303 };
304
305 dpll_core_x2_ck: clock-dpll-core-x2 {
306 #clock-cells = <0>;
307 compatible = "ti,omap4-dpll-x2-clock";
308 clock-output-names = "dpll_core_x2_ck";
309 clocks = <&dpll_core_ck>;
310 };
311
312 dpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {
313 #clock-cells = <0>;
314 compatible = "ti,divider-clock";
315 clock-output-names = "dpll_core_h12x2_ck";
316 clocks = <&dpll_core_x2_ck>;
317 ti,max-div = <63>;
318 ti,autoidle-shift = <8>;
319 reg = <0x013c>;
320 ti,index-starts-at-one;
321 ti,invert-autoidle-bit;
322 };
323
324 mpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {
325 #clock-cells = <0>;
326 compatible = "fixed-factor-clock";
327 clock-output-names = "mpu_dpll_hs_clk_div";
328 clocks = <&dpll_core_h12x2_ck>;
329 clock-mult = <1>;
330 clock-div = <1>;
331 };
332
333 dpll_mpu_ck: clock@160 {
334 #clock-cells = <0>;
335 compatible = "ti,omap5-mpu-dpll-clock";
336 clock-output-names = "dpll_mpu_ck";
337 clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
338 reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
339 };
340
341 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {
342 #clock-cells = <0>;
343 compatible = "ti,divider-clock";
344 clock-output-names = "dpll_mpu_m2_ck";
345 clocks = <&dpll_mpu_ck>;
346 ti,max-div = <31>;
347 ti,autoidle-shift = <8>;
348 reg = <0x0170>;
349 ti,index-starts-at-one;
350 ti,invert-autoidle-bit;
351 };
352
353 mpu_dclk_div: clock-mpu-dclk-div {
354 #clock-cells = <0>;
355 compatible = "fixed-factor-clock";
356 clock-output-names = "mpu_dclk_div";
357 clocks = <&dpll_mpu_m2_ck>;
358 clock-mult = <1>;
359 clock-div = <1>;
360 };
361
362 dsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {
363 #clock-cells = <0>;
364 compatible = "fixed-factor-clock";
365 clock-output-names = "dsp_dpll_hs_clk_div";
366 clocks = <&dpll_core_h12x2_ck>;
367 clock-mult = <1>;
368 clock-div = <1>;
369 };
370
371 dpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {
372 #clock-cells = <0>;
373 compatible = "ti,mux-clock";
374 clock-output-names = "dpll_dsp_byp_mux";
375 clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
376 ti,bit-shift = <23>;
377 reg = <0x0240>;
378 };
379
380 dpll_dsp_ck: clock@234 {
381 #clock-cells = <0>;
382 compatible = "ti,omap4-dpll-clock";
383 clock-output-names = "dpll_dsp_ck";
384 clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
385 reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
386 assigned-clocks = <&dpll_dsp_ck>;
387 assigned-clock-rates = <600000000>;
388 };
389
390 dpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {
391 #clock-cells = <0>;
392 compatible = "ti,divider-clock";
393 clock-output-names = "dpll_dsp_m2_ck";
394 clocks = <&dpll_dsp_ck>;
395 ti,max-div = <31>;
396 ti,autoidle-shift = <8>;
397 reg = <0x0244>;
398 ti,index-starts-at-one;
399 ti,invert-autoidle-bit;
400 assigned-clocks = <&dpll_dsp_m2_ck>;
401 assigned-clock-rates = <600000000>;
402 };
403
404 iva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {
405 #clock-cells = <0>;
406 compatible = "fixed-factor-clock";
407 clock-output-names = "iva_dpll_hs_clk_div";
408 clocks = <&dpll_core_h12x2_ck>;
409 clock-mult = <1>;
410 clock-div = <1>;
411 };
412
413 dpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {
414 #clock-cells = <0>;
415 compatible = "ti,mux-clock";
416 clock-output-names = "dpll_iva_byp_mux";
417 clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
418 ti,bit-shift = <23>;
419 reg = <0x01ac>;
420 };
421
422 dpll_iva_ck: clock@1a0 {
423 #clock-cells = <0>;
424 compatible = "ti,omap4-dpll-clock";
425 clock-output-names = "dpll_iva_ck";
426 clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
427 reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
428 assigned-clocks = <&dpll_iva_ck>;
429 assigned-clock-rates = <1165000000>;
430 };
431
432 dpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {
433 #clock-cells = <0>;
434 compatible = "ti,divider-clock";
435 clock-output-names = "dpll_iva_m2_ck";
436 clocks = <&dpll_iva_ck>;
437 ti,max-div = <31>;
438 ti,autoidle-shift = <8>;
439 reg = <0x01b0>;
440 ti,index-starts-at-one;
441 ti,invert-autoidle-bit;
442 assigned-clocks = <&dpll_iva_m2_ck>;
443 assigned-clock-rates = <388333334>;
444 };
445
446 iva_dclk: clock-iva-dclk {
447 #clock-cells = <0>;
448 compatible = "fixed-factor-clock";
449 clock-output-names = "iva_dclk";
450 clocks = <&dpll_iva_m2_ck>;
451 clock-mult = <1>;
452 clock-div = <1>;
453 };
454
455 dpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {
456 #clock-cells = <0>;
457 compatible = "ti,mux-clock";
458 clock-output-names = "dpll_gpu_byp_mux";
459 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
460 ti,bit-shift = <23>;
461 reg = <0x02e4>;
462 };
463
464 dpll_gpu_ck: clock@2d8 {
465 #clock-cells = <0>;
466 compatible = "ti,omap4-dpll-clock";
467 clock-output-names = "dpll_gpu_ck";
468 clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
469 reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
470 assigned-clocks = <&dpll_gpu_ck>;
471 assigned-clock-rates = <1277000000>;
472 };
473
474 dpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {
475 #clock-cells = <0>;
476 compatible = "ti,divider-clock";
477 clock-output-names = "dpll_gpu_m2_ck";
478 clocks = <&dpll_gpu_ck>;
479 ti,max-div = <31>;
480 ti,autoidle-shift = <8>;
481 reg = <0x02e8>;
482 ti,index-starts-at-one;
483 ti,invert-autoidle-bit;
484 assigned-clocks = <&dpll_gpu_m2_ck>;
485 assigned-clock-rates = <425666667>;
486 };
487
488 dpll_core_m2_ck: clock-dpll-core-m2-8@130 {
489 #clock-cells = <0>;
490 compatible = "ti,divider-clock";
491 clock-output-names = "dpll_core_m2_ck";
492 clocks = <&dpll_core_ck>;
493 ti,max-div = <31>;
494 ti,autoidle-shift = <8>;
495 reg = <0x0130>;
496 ti,index-starts-at-one;
497 ti,invert-autoidle-bit;
498 };
499
500 core_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {
501 #clock-cells = <0>;
502 compatible = "fixed-factor-clock";
503 clock-output-names = "core_dpll_out_dclk_div";
504 clocks = <&dpll_core_m2_ck>;
505 clock-mult = <1>;
506 clock-div = <1>;
507 };
508
509 dpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {
510 #clock-cells = <0>;
511 compatible = "ti,mux-clock";
512 clock-output-names = "dpll_ddr_byp_mux";
513 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
514 ti,bit-shift = <23>;
515 reg = <0x021c>;
516 };
517
518 dpll_ddr_ck: clock@210 {
519 #clock-cells = <0>;
520 compatible = "ti,omap4-dpll-clock";
521 clock-output-names = "dpll_ddr_ck";
522 clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
523 reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
524 };
525
526 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {
527 #clock-cells = <0>;
528 compatible = "ti,divider-clock";
529 clock-output-names = "dpll_ddr_m2_ck";
530 clocks = <&dpll_ddr_ck>;
531 ti,max-div = <31>;
532 ti,autoidle-shift = <8>;
533 reg = <0x0220>;
534 ti,index-starts-at-one;
535 ti,invert-autoidle-bit;
536 };
537
538 dpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {
539 #clock-cells = <0>;
540 compatible = "ti,mux-clock";
541 clock-output-names = "dpll_gmac_byp_mux";
542 clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
543 ti,bit-shift = <23>;
544 reg = <0x02b4>;
545 };
546
547 dpll_gmac_ck: clock@2a8 {
548 #clock-cells = <0>;
549 compatible = "ti,omap4-dpll-clock";
550 clock-output-names = "dpll_gmac_ck";
551 clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
552 reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
553 };
554
555 dpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {
556 #clock-cells = <0>;
557 compatible = "ti,divider-clock";
558 clock-output-names = "dpll_gmac_m2_ck";
559 clocks = <&dpll_gmac_ck>;
560 ti,max-div = <31>;
561 ti,autoidle-shift = <8>;
562 reg = <0x02b8>;
563 ti,index-starts-at-one;
564 ti,invert-autoidle-bit;
565 };
566
567 video2_dclk_div: clock-video2-dclk-div {
568 #clock-cells = <0>;
569 compatible = "fixed-factor-clock";
570 clock-output-names = "video2_dclk_div";
571 clocks = <&video2_m2_clkin_ck>;
572 clock-mult = <1>;
573 clock-div = <1>;
574 };
575
576 video1_dclk_div: clock-video1-dclk-div {
577 #clock-cells = <0>;
578 compatible = "fixed-factor-clock";
579 clock-output-names = "video1_dclk_div";
580 clocks = <&video1_m2_clkin_ck>;
581 clock-mult = <1>;
582 clock-div = <1>;
583 };
584
585 hdmi_dclk_div: clock-hdmi-dclk-div {
586 #clock-cells = <0>;
587 compatible = "fixed-factor-clock";
588 clock-output-names = "hdmi_dclk_div";
589 clocks = <&hdmi_clkin_ck>;
590 clock-mult = <1>;
591 clock-div = <1>;
592 };
593
594 per_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {
595 #clock-cells = <0>;
596 compatible = "fixed-factor-clock";
597 clock-output-names = "per_dpll_hs_clk_div";
598 clocks = <&dpll_abe_m3x2_ck>;
599 clock-mult = <1>;
600 clock-div = <2>;
601 };
602
603 usb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {
604 #clock-cells = <0>;
605 compatible = "fixed-factor-clock";
606 clock-output-names = "usb_dpll_hs_clk_div";
607 clocks = <&dpll_abe_m3x2_ck>;
608 clock-mult = <1>;
609 clock-div = <3>;
610 };
611
612 eve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {
613 #clock-cells = <0>;
614 compatible = "fixed-factor-clock";
615 clock-output-names = "eve_dpll_hs_clk_div";
616 clocks = <&dpll_core_h12x2_ck>;
617 clock-mult = <1>;
618 clock-div = <1>;
619 };
620
621 dpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {
622 #clock-cells = <0>;
623 compatible = "ti,mux-clock";
624 clock-output-names = "dpll_eve_byp_mux";
625 clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
626 ti,bit-shift = <23>;
627 reg = <0x0290>;
628 };
629
630 dpll_eve_ck: clock@284 {
631 #clock-cells = <0>;
632 compatible = "ti,omap4-dpll-clock";
633 clock-output-names = "dpll_eve_ck";
634 clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
635 reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
636 };
637
638 dpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {
639 #clock-cells = <0>;
640 compatible = "ti,divider-clock";
641 clock-output-names = "dpll_eve_m2_ck";
642 clocks = <&dpll_eve_ck>;
643 ti,max-div = <31>;
644 ti,autoidle-shift = <8>;
645 reg = <0x0294>;
646 ti,index-starts-at-one;
647 ti,invert-autoidle-bit;
648 };
649
650 eve_dclk_div: clock-eve-dclk-div {
651 #clock-cells = <0>;
652 compatible = "fixed-factor-clock";
653 clock-output-names = "eve_dclk_div";
654 clocks = <&dpll_eve_m2_ck>;
655 clock-mult = <1>;
656 clock-div = <1>;
657 };
658
659 dpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {
660 #clock-cells = <0>;
661 compatible = "ti,divider-clock";
662 clock-output-names = "dpll_core_h13x2_ck";
663 clocks = <&dpll_core_x2_ck>;
664 ti,max-div = <63>;
665 ti,autoidle-shift = <8>;
666 reg = <0x0140>;
667 ti,index-starts-at-one;
668 ti,invert-autoidle-bit;
669 };
670
671 dpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {
672 #clock-cells = <0>;
673 compatible = "ti,divider-clock";
674 clock-output-names = "dpll_core_h14x2_ck";
675 clocks = <&dpll_core_x2_ck>;
676 ti,max-div = <63>;
677 ti,autoidle-shift = <8>;
678 reg = <0x0144>;
679 ti,index-starts-at-one;
680 ti,invert-autoidle-bit;
681 };
682
683 dpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {
684 #clock-cells = <0>;
685 compatible = "ti,divider-clock";
686 clock-output-names = "dpll_core_h22x2_ck";
687 clocks = <&dpll_core_x2_ck>;
688 ti,max-div = <63>;
689 ti,autoidle-shift = <8>;
690 reg = <0x0154>;
691 ti,index-starts-at-one;
692 ti,invert-autoidle-bit;
693 };
694
695 dpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {
696 #clock-cells = <0>;
697 compatible = "ti,divider-clock";
698 clock-output-names = "dpll_core_h23x2_ck";
699 clocks = <&dpll_core_x2_ck>;
700 ti,max-div = <63>;
701 ti,autoidle-shift = <8>;
702 reg = <0x0158>;
703 ti,index-starts-at-one;
704 ti,invert-autoidle-bit;
705 };
706
707 dpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {
708 #clock-cells = <0>;
709 compatible = "ti,divider-clock";
710 clock-output-names = "dpll_core_h24x2_ck";
711 clocks = <&dpll_core_x2_ck>;
712 ti,max-div = <63>;
713 ti,autoidle-shift = <8>;
714 reg = <0x015c>;
715 ti,index-starts-at-one;
716 ti,invert-autoidle-bit;
717 };
718
719 dpll_ddr_x2_ck: clock-dpll-ddr-x2 {
720 #clock-cells = <0>;
721 compatible = "ti,omap4-dpll-x2-clock";
722 clock-output-names = "dpll_ddr_x2_ck";
723 clocks = <&dpll_ddr_ck>;
724 };
725
726 dpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {
727 #clock-cells = <0>;
728 compatible = "ti,divider-clock";
729 clock-output-names = "dpll_ddr_h11x2_ck";
730 clocks = <&dpll_ddr_x2_ck>;
731 ti,max-div = <63>;
732 ti,autoidle-shift = <8>;
733 reg = <0x0228>;
734 ti,index-starts-at-one;
735 ti,invert-autoidle-bit;
736 };
737
738 dpll_dsp_x2_ck: clock-dpll-dsp-x2 {
739 #clock-cells = <0>;
740 compatible = "ti,omap4-dpll-x2-clock";
741 clock-output-names = "dpll_dsp_x2_ck";
742 clocks = <&dpll_dsp_ck>;
743 };
744
745 dpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {
746 #clock-cells = <0>;
747 compatible = "ti,divider-clock";
748 clock-output-names = "dpll_dsp_m3x2_ck";
749 clocks = <&dpll_dsp_x2_ck>;
750 ti,max-div = <31>;
751 ti,autoidle-shift = <8>;
752 reg = <0x0248>;
753 ti,index-starts-at-one;
754 ti,invert-autoidle-bit;
755 assigned-clocks = <&dpll_dsp_m3x2_ck>;
756 assigned-clock-rates = <400000000>;
757 };
758
759 dpll_gmac_x2_ck: clock-dpll-gmac-x2 {
760 #clock-cells = <0>;
761 compatible = "ti,omap4-dpll-x2-clock";
762 clock-output-names = "dpll_gmac_x2_ck";
763 clocks = <&dpll_gmac_ck>;
764 };
765
766 dpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {
767 #clock-cells = <0>;
768 compatible = "ti,divider-clock";
769 clock-output-names = "dpll_gmac_h11x2_ck";
770 clocks = <&dpll_gmac_x2_ck>;
771 ti,max-div = <63>;
772 ti,autoidle-shift = <8>;
773 reg = <0x02c0>;
774 ti,index-starts-at-one;
775 ti,invert-autoidle-bit;
776 };
777
778 dpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {
779 #clock-cells = <0>;
780 compatible = "ti,divider-clock";
781 clock-output-names = "dpll_gmac_h12x2_ck";
782 clocks = <&dpll_gmac_x2_ck>;
783 ti,max-div = <63>;
784 ti,autoidle-shift = <8>;
785 reg = <0x02c4>;
786 ti,index-starts-at-one;
787 ti,invert-autoidle-bit;
788 };
789
790 dpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {
791 #clock-cells = <0>;
792 compatible = "ti,divider-clock";
793 clock-output-names = "dpll_gmac_h13x2_ck";
794 clocks = <&dpll_gmac_x2_ck>;
795 ti,max-div = <63>;
796 ti,autoidle-shift = <8>;
797 reg = <0x02c8>;
798 ti,index-starts-at-one;
799 ti,invert-autoidle-bit;
800 };
801
802 dpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {
803 #clock-cells = <0>;
804 compatible = "ti,divider-clock";
805 clock-output-names = "dpll_gmac_m3x2_ck";
806 clocks = <&dpll_gmac_x2_ck>;
807 ti,max-div = <31>;
808 ti,autoidle-shift = <8>;
809 reg = <0x02bc>;
810 ti,index-starts-at-one;
811 ti,invert-autoidle-bit;
812 };
813
814 gmii_m_clk_div: clock-gmii-m-clk-div {
815 #clock-cells = <0>;
816 compatible = "fixed-factor-clock";
817 clock-output-names = "gmii_m_clk_div";
818 clocks = <&dpll_gmac_h11x2_ck>;
819 clock-mult = <1>;
820 clock-div = <2>;
821 };
822
823 hdmi_clk2_div: clock-hdmi-clk2-div {
824 #clock-cells = <0>;
825 compatible = "fixed-factor-clock";
826 clock-output-names = "hdmi_clk2_div";
827 clocks = <&hdmi_clkin_ck>;
828 clock-mult = <1>;
829 clock-div = <1>;
830 };
831
832 hdmi_div_clk: clock-hdmi-div {
833 #clock-cells = <0>;
834 compatible = "fixed-factor-clock";
835 clock-output-names = "hdmi_div_clk";
836 clocks = <&hdmi_clkin_ck>;
837 clock-mult = <1>;
838 clock-div = <1>;
839 };
840
841 l3_iclk_div: clock-l3-iclk-div-4@100 {
842 #clock-cells = <0>;
843 compatible = "ti,divider-clock";
844 clock-output-names = "l3_iclk_div";
845 ti,max-div = <2>;
846 ti,bit-shift = <4>;
847 reg = <0x0100>;
848 clocks = <&dpll_core_h12x2_ck>;
849 ti,index-power-of-two;
850 };
851
852 l4_root_clk_div: clock-l4-root-clk-div {
853 #clock-cells = <0>;
854 compatible = "fixed-factor-clock";
855 clock-output-names = "l4_root_clk_div";
856 clocks = <&l3_iclk_div>;
857 clock-mult = <1>;
858 clock-div = <2>;
859 };
860
861 video1_clk2_div: clock-video1-clk2-div {
862 #clock-cells = <0>;
863 compatible = "fixed-factor-clock";
864 clock-output-names = "video1_clk2_div";
865 clocks = <&video1_clkin_ck>;
866 clock-mult = <1>;
867 clock-div = <1>;
868 };
869
870 video1_div_clk: clock-video1-div {
871 #clock-cells = <0>;
872 compatible = "fixed-factor-clock";
873 clock-output-names = "video1_div_clk";
874 clocks = <&video1_clkin_ck>;
875 clock-mult = <1>;
876 clock-div = <1>;
877 };
878
879 video2_clk2_div: clock-video2-clk2-div {
880 #clock-cells = <0>;
881 compatible = "fixed-factor-clock";
882 clock-output-names = "video2_clk2_div";
883 clocks = <&video2_clkin_ck>;
884 clock-mult = <1>;
885 clock-div = <1>;
886 };
887
888 video2_div_clk: clock-video2-div {
889 #clock-cells = <0>;
890 compatible = "fixed-factor-clock";
891 clock-output-names = "video2_div_clk";
892 clocks = <&video2_clkin_ck>;
893 clock-mult = <1>;
894 clock-div = <1>;
895 };
896
897 dummy_ck: clock-dummy {
898 #clock-cells = <0>;
899 compatible = "fixed-clock";
900 clock-output-names = "dummy_ck";
901 clock-frequency = <0>;
902 };
903};
904&prm_clocks {
905 sys_clkin1: clock-sys-clkin1@110 {
906 #clock-cells = <0>;
907 compatible = "ti,mux-clock";
908 clock-output-names = "sys_clkin1";
909 clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
910 reg = <0x0110>;
911 ti,index-starts-at-one;
912 };
913
914 abe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {
915 #clock-cells = <0>;
916 compatible = "ti,mux-clock";
917 clock-output-names = "abe_dpll_sys_clk_mux";
918 clocks = <&sys_clkin1>, <&sys_clkin2>;
919 reg = <0x0118>;
920 };
921
922 abe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {
923 #clock-cells = <0>;
924 compatible = "ti,mux-clock";
925 clock-output-names = "abe_dpll_bypass_clk_mux";
926 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
927 reg = <0x0114>;
928 };
929
930 abe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {
931 #clock-cells = <0>;
932 compatible = "ti,mux-clock";
933 clock-output-names = "abe_dpll_clk_mux";
934 clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
935 reg = <0x010c>;
936 };
937
938 abe_24m_fclk: clock-abe-24m@11c {
939 #clock-cells = <0>;
940 compatible = "ti,divider-clock";
941 clock-output-names = "abe_24m_fclk";
942 clocks = <&dpll_abe_m2x2_ck>;
943 reg = <0x011c>;
944 ti,dividers = <8>, <16>;
945 };
946
947 aess_fclk: clock-aess@178 {
948 #clock-cells = <0>;
949 compatible = "ti,divider-clock";
950 clock-output-names = "aess_fclk";
951 clocks = <&abe_clk>;
952 reg = <0x0178>;
953 ti,max-div = <2>;
954 };
955
956 abe_giclk_div: clock-abe-giclk-div@174 {
957 #clock-cells = <0>;
958 compatible = "ti,divider-clock";
959 clock-output-names = "abe_giclk_div";
960 clocks = <&aess_fclk>;
961 reg = <0x0174>;
962 ti,max-div = <2>;
963 };
964
965 abe_lp_clk_div: clock-abe-lp-clk-div@1d8 {
966 #clock-cells = <0>;
967 compatible = "ti,divider-clock";
968 clock-output-names = "abe_lp_clk_div";
969 clocks = <&dpll_abe_m2x2_ck>;
970 reg = <0x01d8>;
971 ti,dividers = <16>, <32>;
972 };
973
974 abe_sys_clk_div: clock-abe-sys-clk-div@120 {
975 #clock-cells = <0>;
976 compatible = "ti,divider-clock";
977 clock-output-names = "abe_sys_clk_div";
978 clocks = <&sys_clkin1>;
979 reg = <0x0120>;
980 ti,max-div = <2>;
981 };
982
983 adc_gfclk_mux: clock-adc-gfclk-mux@1dc {
984 #clock-cells = <0>;
985 compatible = "ti,mux-clock";
986 clock-output-names = "adc_gfclk_mux";
987 clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
988 reg = <0x01dc>;
989 };
990
991 sys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {
992 #clock-cells = <0>;
993 compatible = "ti,divider-clock";
994 clock-output-names = "sys_clk1_dclk_div";
995 clocks = <&sys_clkin1>;
996 ti,max-div = <64>;
997 reg = <0x01c8>;
998 ti,index-power-of-two;
999 };
1000
1001 sys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {
1002 #clock-cells = <0>;
1003 compatible = "ti,divider-clock";
1004 clock-output-names = "sys_clk2_dclk_div";
1005 clocks = <&sys_clkin2>;
1006 ti,max-div = <64>;
1007 reg = <0x01cc>;
1008 ti,index-power-of-two;
1009 };
1010
1011 per_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {
1012 #clock-cells = <0>;
1013 compatible = "ti,divider-clock";
1014 clock-output-names = "per_abe_x1_dclk_div";
1015 clocks = <&dpll_abe_m2_ck>;
1016 ti,max-div = <64>;
1017 reg = <0x01bc>;
1018 ti,index-power-of-two;
1019 };
1020
1021 dsp_gclk_div: clock-dsp-gclk-div@18c {
1022 #clock-cells = <0>;
1023 compatible = "ti,divider-clock";
1024 clock-output-names = "dsp_gclk_div";
1025 clocks = <&dpll_dsp_m2_ck>;
1026 ti,max-div = <64>;
1027 reg = <0x018c>;
1028 ti,index-power-of-two;
1029 };
1030
1031 gpu_dclk: clock-gpu-dclk@1a0 {
1032 #clock-cells = <0>;
1033 compatible = "ti,divider-clock";
1034 clock-output-names = "gpu_dclk";
1035 clocks = <&dpll_gpu_m2_ck>;
1036 ti,max-div = <64>;
1037 reg = <0x01a0>;
1038 ti,index-power-of-two;
1039 };
1040
1041 emif_phy_dclk_div: clock-emif-phy-dclk-div@190 {
1042 #clock-cells = <0>;
1043 compatible = "ti,divider-clock";
1044 clock-output-names = "emif_phy_dclk_div";
1045 clocks = <&dpll_ddr_m2_ck>;
1046 ti,max-div = <64>;
1047 reg = <0x0190>;
1048 ti,index-power-of-two;
1049 };
1050
1051 gmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {
1052 #clock-cells = <0>;
1053 compatible = "ti,divider-clock";
1054 clock-output-names = "gmac_250m_dclk_div";
1055 clocks = <&dpll_gmac_m2_ck>;
1056 ti,max-div = <64>;
1057 reg = <0x019c>;
1058 ti,index-power-of-two;
1059 };
1060
1061 gmac_main_clk: clock-gmac-main {
1062 #clock-cells = <0>;
1063 compatible = "fixed-factor-clock";
1064 clock-output-names = "gmac_main_clk";
1065 clocks = <&gmac_250m_dclk_div>;
1066 clock-mult = <1>;
1067 clock-div = <2>;
1068 };
1069
1070 l3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {
1071 #clock-cells = <0>;
1072 compatible = "ti,divider-clock";
1073 clock-output-names = "l3init_480m_dclk_div";
1074 clocks = <&dpll_usb_m2_ck>;
1075 ti,max-div = <64>;
1076 reg = <0x01ac>;
1077 ti,index-power-of-two;
1078 };
1079
1080 usb_otg_dclk_div: clock-usb-otg-dclk-div@184 {
1081 #clock-cells = <0>;
1082 compatible = "ti,divider-clock";
1083 clock-output-names = "usb_otg_dclk_div";
1084 clocks = <&usb_otg_clkin_ck>;
1085 ti,max-div = <64>;
1086 reg = <0x0184>;
1087 ti,index-power-of-two;
1088 };
1089
1090 sata_dclk_div: clock-sata-dclk-div@1c0 {
1091 #clock-cells = <0>;
1092 compatible = "ti,divider-clock";
1093 clock-output-names = "sata_dclk_div";
1094 clocks = <&sys_clkin1>;
1095 ti,max-div = <64>;
1096 reg = <0x01c0>;
1097 ti,index-power-of-two;
1098 };
1099
1100 pcie2_dclk_div: clock-pcie2-dclk-div@1b8 {
1101 #clock-cells = <0>;
1102 compatible = "ti,divider-clock";
1103 clock-output-names = "pcie2_dclk_div";
1104 clocks = <&dpll_pcie_ref_m2_ck>;
1105 ti,max-div = <64>;
1106 reg = <0x01b8>;
1107 ti,index-power-of-two;
1108 };
1109
1110 pcie_dclk_div: clock-pcie-dclk-div@1b4 {
1111 #clock-cells = <0>;
1112 compatible = "ti,divider-clock";
1113 clock-output-names = "pcie_dclk_div";
1114 clocks = <&apll_pcie_m2_ck>;
1115 ti,max-div = <64>;
1116 reg = <0x01b4>;
1117 ti,index-power-of-two;
1118 };
1119
1120 emu_dclk_div: clock-emu-dclk-div@194 {
1121 #clock-cells = <0>;
1122 compatible = "ti,divider-clock";
1123 clock-output-names = "emu_dclk_div";
1124 clocks = <&sys_clkin1>;
1125 ti,max-div = <64>;
1126 reg = <0x0194>;
1127 ti,index-power-of-two;
1128 };
1129
1130 secure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {
1131 #clock-cells = <0>;
1132 compatible = "ti,divider-clock";
1133 clock-output-names = "secure_32k_dclk_div";
1134 clocks = <&secure_32k_clk_src_ck>;
1135 ti,max-div = <64>;
1136 reg = <0x01c4>;
1137 ti,index-power-of-two;
1138 };
1139
1140 clkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {
1141 #clock-cells = <0>;
1142 compatible = "ti,mux-clock";
1143 clock-output-names = "clkoutmux0_clk_mux";
1144 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1145 reg = <0x0158>;
1146 };
1147
1148 clkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {
1149 #clock-cells = <0>;
1150 compatible = "ti,mux-clock";
1151 clock-output-names = "clkoutmux1_clk_mux";
1152 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1153 reg = <0x015c>;
1154 };
1155
1156 clkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {
1157 #clock-cells = <0>;
1158 compatible = "ti,mux-clock";
1159 clock-output-names = "clkoutmux2_clk_mux";
1160 clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1161 reg = <0x0160>;
1162 };
1163
1164 custefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {
1165 #clock-cells = <0>;
1166 compatible = "fixed-factor-clock";
1167 clock-output-names = "custefuse_sys_gfclk_div";
1168 clocks = <&sys_clkin1>;
1169 clock-mult = <1>;
1170 clock-div = <2>;
1171 };
1172
1173 eve_clk: clock-eve@180 {
1174 #clock-cells = <0>;
1175 compatible = "ti,mux-clock";
1176 clock-output-names = "eve_clk";
1177 clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1178 reg = <0x0180>;
1179 };
1180
1181 hdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {
1182 #clock-cells = <0>;
1183 compatible = "ti,mux-clock";
1184 clock-output-names = "hdmi_dpll_clk_mux";
1185 clocks = <&sys_clkin1>, <&sys_clkin2>;
1186 reg = <0x0164>;
1187 };
1188
1189 mlb_clk: clock-mlb@134 {
1190 #clock-cells = <0>;
1191 compatible = "ti,divider-clock";
1192 clock-output-names = "mlb_clk";
1193 clocks = <&mlb_clkin_ck>;
1194 ti,max-div = <64>;
1195 reg = <0x0134>;
1196 ti,index-power-of-two;
1197 };
1198
1199 mlbp_clk: clock-mlbp@130 {
1200 #clock-cells = <0>;
1201 compatible = "ti,divider-clock";
1202 clock-output-names = "mlbp_clk";
1203 clocks = <&mlbp_clkin_ck>;
1204 ti,max-div = <64>;
1205 reg = <0x0130>;
1206 ti,index-power-of-two;
1207 };
1208
1209 per_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {
1210 #clock-cells = <0>;
1211 compatible = "ti,divider-clock";
1212 clock-output-names = "per_abe_x1_gfclk2_div";
1213 clocks = <&dpll_abe_m2_ck>;
1214 ti,max-div = <64>;
1215 reg = <0x0138>;
1216 ti,index-power-of-two;
1217 };
1218
1219 timer_sys_clk_div: clock-timer-sys-clk-div@144 {
1220 #clock-cells = <0>;
1221 compatible = "ti,divider-clock";
1222 clock-output-names = "timer_sys_clk_div";
1223 clocks = <&sys_clkin1>;
1224 reg = <0x0144>;
1225 ti,max-div = <2>;
1226 };
1227
1228 video1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {
1229 #clock-cells = <0>;
1230 compatible = "ti,mux-clock";
1231 clock-output-names = "video1_dpll_clk_mux";
1232 clocks = <&sys_clkin1>, <&sys_clkin2>;
1233 reg = <0x0168>;
1234 };
1235
1236 video2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {
1237 #clock-cells = <0>;
1238 compatible = "ti,mux-clock";
1239 clock-output-names = "video2_dpll_clk_mux";
1240 clocks = <&sys_clkin1>, <&sys_clkin2>;
1241 reg = <0x016c>;
1242 };
1243
1244 wkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {
1245 #clock-cells = <0>;
1246 compatible = "ti,mux-clock";
1247 clock-output-names = "wkupaon_iclk_mux";
1248 clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1249 reg = <0x0108>;
1250 };
1251};
1252
1253&cm_core_clocks {
1254 dpll_pcie_ref_ck: clock@200 {
1255 #clock-cells = <0>;
1256 compatible = "ti,omap4-dpll-clock";
1257 clock-output-names = "dpll_pcie_ref_ck";
1258 clocks = <&sys_clkin1>, <&sys_clkin1>;
1259 reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1260 };
1261
1262 dpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {
1263 #clock-cells = <0>;
1264 compatible = "ti,divider-clock";
1265 clock-output-names = "dpll_pcie_ref_m2ldo_ck";
1266 clocks = <&dpll_pcie_ref_ck>;
1267 ti,max-div = <31>;
1268 ti,autoidle-shift = <8>;
1269 reg = <0x0210>;
1270 ti,index-starts-at-one;
1271 ti,invert-autoidle-bit;
1272 };
1273
1274 apll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {
1275 compatible = "ti,mux-clock";
1276 clock-output-names = "apll_pcie_in_clk_mux";
1277 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1278 #clock-cells = <0>;
1279 reg = <0x021c 0x4>;
1280 ti,bit-shift = <7>;
1281 };
1282
1283 apll_pcie_ck: clock@21c {
1284 #clock-cells = <0>;
1285 compatible = "ti,dra7-apll-clock";
1286 clock-output-names = "apll_pcie_ck";
1287 clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1288 reg = <0x021c>, <0x0220>;
1289 };
1290
1291 optfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {
1292 compatible = "ti,divider-clock";
1293 clock-output-names = "optfclk_pciephy_div";
1294 clocks = <&apll_pcie_ck>;
1295 #clock-cells = <0>;
1296 reg = <0x021c>;
1297 ti,dividers = <2>, <1>;
1298 ti,bit-shift = <8>;
1299 ti,max-div = <2>;
1300 };
1301
1302 apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
1303 #clock-cells = <0>;
1304 compatible = "fixed-factor-clock";
1305 clock-output-names = "apll_pcie_clkvcoldo";
1306 clocks = <&apll_pcie_ck>;
1307 clock-mult = <1>;
1308 clock-div = <1>;
1309 };
1310
1311 apll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {
1312 #clock-cells = <0>;
1313 compatible = "fixed-factor-clock";
1314 clock-output-names = "apll_pcie_clkvcoldo_div";
1315 clocks = <&apll_pcie_ck>;
1316 clock-mult = <1>;
1317 clock-div = <1>;
1318 };
1319
1320 apll_pcie_m2_ck: clock-apll-pcie-m2 {
1321 #clock-cells = <0>;
1322 compatible = "fixed-factor-clock";
1323 clock-output-names = "apll_pcie_m2_ck";
1324 clocks = <&apll_pcie_ck>;
1325 clock-mult = <1>;
1326 clock-div = <1>;
1327 };
1328
1329 dpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {
1330 #clock-cells = <0>;
1331 compatible = "ti,mux-clock";
1332 clock-output-names = "dpll_per_byp_mux";
1333 clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1334 ti,bit-shift = <23>;
1335 reg = <0x014c>;
1336 };
1337
1338 dpll_per_ck: clock@140 {
1339 #clock-cells = <0>;
1340 compatible = "ti,omap4-dpll-clock";
1341 clock-output-names = "dpll_per_ck";
1342 clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1343 reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1344 };
1345
1346 dpll_per_m2_ck: clock-dpll-per-m2-8@150 {
1347 #clock-cells = <0>;
1348 compatible = "ti,divider-clock";
1349 clock-output-names = "dpll_per_m2_ck";
1350 clocks = <&dpll_per_ck>;
1351 ti,max-div = <31>;
1352 ti,autoidle-shift = <8>;
1353 reg = <0x0150>;
1354 ti,index-starts-at-one;
1355 ti,invert-autoidle-bit;
1356 };
1357
1358 func_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {
1359 #clock-cells = <0>;
1360 compatible = "fixed-factor-clock";
1361 clock-output-names = "func_96m_aon_dclk_div";
1362 clocks = <&dpll_per_m2_ck>;
1363 clock-mult = <1>;
1364 clock-div = <1>;
1365 };
1366
1367 dpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {
1368 #clock-cells = <0>;
1369 compatible = "ti,mux-clock";
1370 clock-output-names = "dpll_usb_byp_mux";
1371 clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1372 ti,bit-shift = <23>;
1373 reg = <0x018c>;
1374 };
1375
1376 dpll_usb_ck: clock@180 {
1377 #clock-cells = <0>;
1378 compatible = "ti,omap4-dpll-j-type-clock";
1379 clock-output-names = "dpll_usb_ck";
1380 clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1381 reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1382 };
1383
1384 dpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {
1385 #clock-cells = <0>;
1386 compatible = "ti,divider-clock";
1387 clock-output-names = "dpll_usb_m2_ck";
1388 clocks = <&dpll_usb_ck>;
1389 ti,max-div = <127>;
1390 ti,autoidle-shift = <8>;
1391 reg = <0x0190>;
1392 ti,index-starts-at-one;
1393 ti,invert-autoidle-bit;
1394 };
1395
1396 dpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {
1397 #clock-cells = <0>;
1398 compatible = "ti,divider-clock";
1399 clock-output-names = "dpll_pcie_ref_m2_ck";
1400 clocks = <&dpll_pcie_ref_ck>;
1401 ti,max-div = <127>;
1402 ti,autoidle-shift = <8>;
1403 reg = <0x0210>;
1404 ti,index-starts-at-one;
1405 ti,invert-autoidle-bit;
1406 };
1407
1408 dpll_per_x2_ck: clock-dpll-per-x2 {
1409 #clock-cells = <0>;
1410 compatible = "ti,omap4-dpll-x2-clock";
1411 clock-output-names = "dpll_per_x2_ck";
1412 clocks = <&dpll_per_ck>;
1413 };
1414
1415 dpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {
1416 #clock-cells = <0>;
1417 compatible = "ti,divider-clock";
1418 clock-output-names = "dpll_per_h11x2_ck";
1419 clocks = <&dpll_per_x2_ck>;
1420 ti,max-div = <63>;
1421 ti,autoidle-shift = <8>;
1422 reg = <0x0158>;
1423 ti,index-starts-at-one;
1424 ti,invert-autoidle-bit;
1425 };
1426
1427 dpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {
1428 #clock-cells = <0>;
1429 compatible = "ti,divider-clock";
1430 clock-output-names = "dpll_per_h12x2_ck";
1431 clocks = <&dpll_per_x2_ck>;
1432 ti,max-div = <63>;
1433 ti,autoidle-shift = <8>;
1434 reg = <0x015c>;
1435 ti,index-starts-at-one;
1436 ti,invert-autoidle-bit;
1437 };
1438
1439 dpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {
1440 #clock-cells = <0>;
1441 compatible = "ti,divider-clock";
1442 clock-output-names = "dpll_per_h13x2_ck";
1443 clocks = <&dpll_per_x2_ck>;
1444 ti,max-div = <63>;
1445 ti,autoidle-shift = <8>;
1446 reg = <0x0160>;
1447 ti,index-starts-at-one;
1448 ti,invert-autoidle-bit;
1449 };
1450
1451 dpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {
1452 #clock-cells = <0>;
1453 compatible = "ti,divider-clock";
1454 clock-output-names = "dpll_per_h14x2_ck";
1455 clocks = <&dpll_per_x2_ck>;
1456 ti,max-div = <63>;
1457 ti,autoidle-shift = <8>;
1458 reg = <0x0164>;
1459 ti,index-starts-at-one;
1460 ti,invert-autoidle-bit;
1461 };
1462
1463 dpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {
1464 #clock-cells = <0>;
1465 compatible = "ti,divider-clock";
1466 clock-output-names = "dpll_per_m2x2_ck";
1467 clocks = <&dpll_per_x2_ck>;
1468 ti,max-div = <31>;
1469 ti,autoidle-shift = <8>;
1470 reg = <0x0150>;
1471 ti,index-starts-at-one;
1472 ti,invert-autoidle-bit;
1473 };
1474
1475 dpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {
1476 #clock-cells = <0>;
1477 compatible = "fixed-factor-clock";
1478 clock-output-names = "dpll_usb_clkdcoldo";
1479 clocks = <&dpll_usb_ck>;
1480 clock-mult = <1>;
1481 clock-div = <1>;
1482 };
1483
1484 func_128m_clk: clock-func-128m {
1485 #clock-cells = <0>;
1486 compatible = "fixed-factor-clock";
1487 clock-output-names = "func_128m_clk";
1488 clocks = <&dpll_per_h11x2_ck>;
1489 clock-mult = <1>;
1490 clock-div = <2>;
1491 };
1492
1493 func_12m_fclk: clock-func-12m-fclk {
1494 #clock-cells = <0>;
1495 compatible = "fixed-factor-clock";
1496 clock-output-names = "func_12m_fclk";
1497 clocks = <&dpll_per_m2x2_ck>;
1498 clock-mult = <1>;
1499 clock-div = <16>;
1500 };
1501
1502 func_24m_clk: clock-func-24m {
1503 #clock-cells = <0>;
1504 compatible = "fixed-factor-clock";
1505 clock-output-names = "func_24m_clk";
1506 clocks = <&dpll_per_m2_ck>;
1507 clock-mult = <1>;
1508 clock-div = <4>;
1509 };
1510
1511 func_48m_fclk: clock-func-48m-fclk {
1512 #clock-cells = <0>;
1513 compatible = "fixed-factor-clock";
1514 clock-output-names = "func_48m_fclk";
1515 clocks = <&dpll_per_m2x2_ck>;
1516 clock-mult = <1>;
1517 clock-div = <4>;
1518 };
1519
1520 func_96m_fclk: clock-func-96m-fclk {
1521 #clock-cells = <0>;
1522 compatible = "fixed-factor-clock";
1523 clock-output-names = "func_96m_fclk";
1524 clocks = <&dpll_per_m2x2_ck>;
1525 clock-mult = <1>;
1526 clock-div = <2>;
1527 };
1528
1529 l3init_60m_fclk: clock-l3init-60m@104 {
1530 #clock-cells = <0>;
1531 compatible = "ti,divider-clock";
1532 clock-output-names = "l3init_60m_fclk";
1533 clocks = <&dpll_usb_m2_ck>;
1534 reg = <0x0104>;
1535 ti,dividers = <1>, <8>;
1536 };
1537
1538 clkout2_clk: clock-clkout2-8@6b0 {
1539 #clock-cells = <0>;
1540 compatible = "ti,gate-clock";
1541 clock-output-names = "clkout2_clk";
1542 clocks = <&clkoutmux2_clk_mux>;
1543 ti,bit-shift = <8>;
1544 reg = <0x06b0>;
1545 };
1546
1547 l3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {
1548 #clock-cells = <0>;
1549 compatible = "ti,gate-clock";
1550 clock-output-names = "l3init_960m_gfclk";
1551 clocks = <&dpll_usb_clkdcoldo>;
1552 ti,bit-shift = <8>;
1553 reg = <0x06c0>;
1554 };
1555
1556 usb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {
1557 #clock-cells = <0>;
1558 compatible = "ti,gate-clock";
1559 clock-output-names = "usb_phy1_always_on_clk32k";
1560 clocks = <&sys_32k_ck>;
1561 ti,bit-shift = <8>;
1562 reg = <0x0640>;
1563 };
1564
1565 usb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {
1566 #clock-cells = <0>;
1567 compatible = "ti,gate-clock";
1568 clock-output-names = "usb_phy2_always_on_clk32k";
1569 clocks = <&sys_32k_ck>;
1570 ti,bit-shift = <8>;
1571 reg = <0x0688>;
1572 };
1573
1574 usb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {
1575 #clock-cells = <0>;
1576 compatible = "ti,gate-clock";
1577 clock-output-names = "usb_phy3_always_on_clk32k";
1578 clocks = <&sys_32k_ck>;
1579 ti,bit-shift = <8>;
1580 reg = <0x0698>;
1581 };
1582
1583 gpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {
1584 #clock-cells = <0>;
1585 compatible = "ti,mux-clock";
1586 clock-output-names = "gpu_core_gclk_mux";
1587 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1588 ti,bit-shift = <24>;
1589 reg = <0x1220>;
1590 assigned-clocks = <&gpu_core_gclk_mux>;
1591 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1592 };
1593
1594 gpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {
1595 #clock-cells = <0>;
1596 compatible = "ti,mux-clock";
1597 clock-output-names = "gpu_hyd_gclk_mux";
1598 clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1599 ti,bit-shift = <26>;
1600 reg = <0x1220>;
1601 assigned-clocks = <&gpu_hyd_gclk_mux>;
1602 assigned-clock-parents = <&dpll_gpu_m2_ck>;
1603 };
1604
1605 l3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {
1606 #clock-cells = <0>;
1607 compatible = "ti,divider-clock";
1608 clock-output-names = "l3instr_ts_gclk_div";
1609 clocks = <&wkupaon_iclk_mux>;
1610 ti,bit-shift = <24>;
1611 reg = <0x0e50>;
1612 ti,dividers = <8>, <16>, <32>;
1613 };
1614
1615 vip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {
1616 #clock-cells = <0>;
1617 compatible = "ti,mux-clock";
1618 clock-output-names = "vip1_gclk_mux";
1619 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1620 ti,bit-shift = <24>;
1621 reg = <0x1020>;
1622 };
1623
1624 vip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {
1625 #clock-cells = <0>;
1626 compatible = "ti,mux-clock";
1627 clock-output-names = "vip2_gclk_mux";
1628 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1629 ti,bit-shift = <24>;
1630 reg = <0x1028>;
1631 };
1632
1633 vip3_gclk_mux: clock-vip3-gclk-mux-24@1030 {
1634 #clock-cells = <0>;
1635 compatible = "ti,mux-clock";
1636 clock-output-names = "vip3_gclk_mux";
1637 clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1638 ti,bit-shift = <24>;
1639 reg = <0x1030>;
1640 };
1641};
1642
1643&cm_core_clockdomains {
1644 coreaon_clkdm: clock-coreaon-clkdm {
1645 compatible = "ti,clockdomain";
1646 clock-output-names = "coreaon_clkdm";
1647 clocks = <&dpll_usb_ck>;
1648 };
1649};
1650
1651&scm_conf_clocks {
1652 dss_deshdcp_clk: clock-dss-deshdcp-0@558 {
1653 #clock-cells = <0>;
1654 compatible = "ti,gate-clock";
1655 clock-output-names = "dss_deshdcp_clk";
1656 clocks = <&l3_iclk_div>;
1657 ti,bit-shift = <0>;
1658 reg = <0x558>;
1659 };
1660
1661 ehrpwm0_tbclk: clock-ehrpwm0-tbclk-20@558 {
1662 #clock-cells = <0>;
1663 compatible = "ti,gate-clock";
1664 clock-output-names = "ehrpwm0_tbclk";
1665 clocks = <&l4_root_clk_div>;
1666 ti,bit-shift = <20>;
1667 reg = <0x0558>;
1668 };
1669
1670 ehrpwm1_tbclk: clock-ehrpwm1-tbclk-21@558 {
1671 #clock-cells = <0>;
1672 compatible = "ti,gate-clock";
1673 clock-output-names = "ehrpwm1_tbclk";
1674 clocks = <&l4_root_clk_div>;
1675 ti,bit-shift = <21>;
1676 reg = <0x0558>;
1677 };
1678
1679 ehrpwm2_tbclk: clock-ehrpwm2-tbclk-22@558 {
1680 #clock-cells = <0>;
1681 compatible = "ti,gate-clock";
1682 clock-output-names = "ehrpwm2_tbclk";
1683 clocks = <&l4_root_clk_div>;
1684 ti,bit-shift = <22>;
1685 reg = <0x0558>;
1686 };
1687
1688 sys_32k_ck: clock-sys-32k@6c4 {
1689 #clock-cells = <0>;
1690 compatible = "ti,mux-clock";
1691 clock-output-names = "sys_32k_ck";
1692 clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1693 ti,bit-shift = <8>;
1694 reg = <0x6c4>;
1695 };
1696};
1697
1698&cm_core_aon {
1699 mpu_cm: clock@300 {
1700 compatible = "ti,omap4-cm";
1701 clock-output-names = "mpu_cm";
1702 reg = <0x300 0x100>;
1703 #address-cells = <1>;
1704 #size-cells = <1>;
1705 ranges = <0 0x300 0x100>;
1706
1707 mpu_clkctrl: clock@20 {
1708 compatible = "ti,clkctrl";
1709 clock-output-names = "mpu_clkctrl";
1710 reg = <0x20 0x4>;
1711 #clock-cells = <2>;
1712 };
1713
1714 };
1715
1716 dsp1_cm: clock@400 {
1717 compatible = "ti,omap4-cm";
1718 clock-output-names = "dsp1_cm";
1719 reg = <0x400 0x100>;
1720 #address-cells = <1>;
1721 #size-cells = <1>;
1722 ranges = <0 0x400 0x100>;
1723
1724 dsp1_clkctrl: clock@20 {
1725 compatible = "ti,clkctrl";
1726 clock-output-names = "dsp1_clkctrl";
1727 reg = <0x20 0x4>;
1728 #clock-cells = <2>;
1729 };
1730
1731 };
1732
1733 ipu_cm: clock@500 {
1734 compatible = "ti,omap4-cm";
1735 clock-output-names = "ipu_cm";
1736 reg = <0x500 0x100>;
1737 #address-cells = <1>;
1738 #size-cells = <1>;
1739 ranges = <0 0x500 0x100>;
1740
1741 ipu1_clkctrl: clock@20 {
1742 compatible = "ti,clkctrl";
1743 clock-output-names = "ipu1_clkctrl";
1744 reg = <0x20 0x4>;
1745 #clock-cells = <2>;
1746 assigned-clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 24>;
1747 assigned-clock-parents = <&dpll_core_h22x2_ck>;
1748 };
1749
1750 ipu_clkctrl: clock@50 {
1751 compatible = "ti,clkctrl";
1752 clock-output-names = "ipu_clkctrl";
1753 reg = <0x50 0x34>;
1754 #clock-cells = <2>;
1755 };
1756
1757 };
1758
1759 dsp2_cm: clock@600 {
1760 compatible = "ti,omap4-cm";
1761 clock-output-names = "dsp2_cm";
1762 reg = <0x600 0x100>;
1763 #address-cells = <1>;
1764 #size-cells = <1>;
1765 ranges = <0 0x600 0x100>;
1766
1767 dsp2_clkctrl: clock@20 {
1768 compatible = "ti,clkctrl";
1769 clock-output-names = "dsp2_clkctrl";
1770 reg = <0x20 0x4>;
1771 #clock-cells = <2>;
1772 };
1773
1774 };
1775
1776 rtc_cm: clock@700 {
1777 compatible = "ti,omap4-cm";
1778 clock-output-names = "rtc_cm";
1779 reg = <0x700 0x60>;
1780 #address-cells = <1>;
1781 #size-cells = <1>;
1782 ranges = <0 0x700 0x60>;
1783
1784 rtc_clkctrl: clock@20 {
1785 compatible = "ti,clkctrl";
1786 clock-output-names = "rtc_clkctrl";
1787 reg = <0x20 0x28>;
1788 #clock-cells = <2>;
1789 };
1790 };
1791
1792 vpe_cm: clock@760 {
1793 compatible = "ti,omap4-cm";
1794 clock-output-names = "vpe_cm";
1795 reg = <0x760 0xc>;
1796 #address-cells = <1>;
1797 #size-cells = <1>;
1798 ranges = <0 0x760 0xc>;
1799
1800 vpe_clkctrl: clock@0 {
1801 compatible = "ti,clkctrl";
1802 clock-output-names = "vpe_clkctrl";
1803 reg = <0x0 0xc>;
1804 #clock-cells = <2>;
1805 };
1806 };
1807
1808};
1809
1810&cm_core {
1811 coreaon_cm: clock@600 {
1812 compatible = "ti,omap4-cm";
1813 clock-output-names = "coreaon_cm";
1814 reg = <0x600 0x100>;
1815 #address-cells = <1>;
1816 #size-cells = <1>;
1817 ranges = <0 0x600 0x100>;
1818
1819 coreaon_clkctrl: clock@20 {
1820 compatible = "ti,clkctrl";
1821 clock-output-names = "coreaon_clkctrl";
1822 reg = <0x20 0x1c>;
1823 #clock-cells = <2>;
1824 };
1825 };
1826
1827 l3main1_cm: clock@700 {
1828 compatible = "ti,omap4-cm";
1829 clock-output-names = "l3main1_cm";
1830 reg = <0x700 0x100>;
1831 #address-cells = <1>;
1832 #size-cells = <1>;
1833 ranges = <0 0x700 0x100>;
1834
1835 l3main1_clkctrl: clock@20 {
1836 compatible = "ti,clkctrl";
1837 clock-output-names = "l3main1_clkctrl";
1838 reg = <0x20 0x74>;
1839 #clock-cells = <2>;
1840 };
1841
1842 };
1843
1844 ipu2_cm: clock@900 {
1845 compatible = "ti,omap4-cm";
1846 clock-output-names = "ipu2_cm";
1847 reg = <0x900 0x100>;
1848 #address-cells = <1>;
1849 #size-cells = <1>;
1850 ranges = <0 0x900 0x100>;
1851
1852 ipu2_clkctrl: clock@20 {
1853 compatible = "ti,clkctrl";
1854 clock-output-names = "ipu2_clkctrl";
1855 reg = <0x20 0x4>;
1856 #clock-cells = <2>;
1857 };
1858
1859 };
1860
1861 dma_cm: clock@a00 {
1862 compatible = "ti,omap4-cm";
1863 clock-output-names = "dma_cm";
1864 reg = <0xa00 0x100>;
1865 #address-cells = <1>;
1866 #size-cells = <1>;
1867 ranges = <0 0xa00 0x100>;
1868
1869 dma_clkctrl: clock@20 {
1870 compatible = "ti,clkctrl";
1871 clock-output-names = "dma_clkctrl";
1872 reg = <0x20 0x4>;
1873 #clock-cells = <2>;
1874 };
1875 };
1876
1877 emif_cm: clock@b00 {
1878 compatible = "ti,omap4-cm";
1879 clock-output-names = "emif_cm";
1880 reg = <0xb00 0x100>;
1881 #address-cells = <1>;
1882 #size-cells = <1>;
1883 ranges = <0 0xb00 0x100>;
1884
1885 emif_clkctrl: clock@20 {
1886 compatible = "ti,clkctrl";
1887 clock-output-names = "emif_clkctrl";
1888 reg = <0x20 0x4>;
1889 #clock-cells = <2>;
1890 };
1891 };
1892
1893 atl_cm: clock@c00 {
1894 compatible = "ti,omap4-cm";
1895 clock-output-names = "atl_cm";
1896 reg = <0xc00 0x100>;
1897 #address-cells = <1>;
1898 #size-cells = <1>;
1899 ranges = <0 0xc00 0x100>;
1900
1901 atl_clkctrl: clock@0 {
1902 compatible = "ti,clkctrl";
1903 clock-output-names = "atl_clkctrl";
1904 reg = <0x0 0x4>;
1905 #clock-cells = <2>;
1906 };
1907 };
1908
1909 l4cfg_cm: clock@d00 {
1910 compatible = "ti,omap4-cm";
1911 clock-output-names = "l4cfg_cm";
1912 reg = <0xd00 0x100>;
1913 #address-cells = <1>;
1914 #size-cells = <1>;
1915 ranges = <0 0xd00 0x100>;
1916
1917 l4cfg_clkctrl: clock@20 {
1918 compatible = "ti,clkctrl";
1919 clock-output-names = "l4cfg_clkctrl";
1920 reg = <0x20 0x84>;
1921 #clock-cells = <2>;
1922 };
1923 };
1924
1925 l3instr_cm: clock@e00 {
1926 compatible = "ti,omap4-cm";
1927 clock-output-names = "l3instr_cm";
1928 reg = <0xe00 0x100>;
1929 #address-cells = <1>;
1930 #size-cells = <1>;
1931 ranges = <0 0xe00 0x100>;
1932
1933 l3instr_clkctrl: clock@20 {
1934 compatible = "ti,clkctrl";
1935 clock-output-names = "l3instr_clkctrl";
1936 reg = <0x20 0xc>;
1937 #clock-cells = <2>;
1938 };
1939 };
1940
1941 iva_cm: clock@f00 {
1942 compatible = "ti,omap4-cm";
1943 clock-output-names = "iva_cm";
1944 reg = <0xf00 0x100>;
1945 #address-cells = <1>;
1946 #size-cells = <1>;
1947 ranges = <0 0xf00 0x100>;
1948
1949 iva_clkctrl: clock@20 {
1950 compatible = "ti,clkctrl";
1951 clock-output-names = "iva_clkctrl";
1952 reg = <0x20 0xc>;
1953 #clock-cells = <2>;
1954 };
1955 };
1956
1957 cam_cm: clock@1000 {
1958 compatible = "ti,omap4-cm";
1959 clock-output-names = "cam_cm";
1960 reg = <0x1000 0x100>;
1961 #address-cells = <1>;
1962 #size-cells = <1>;
1963 ranges = <0 0x1000 0x100>;
1964
1965 cam_clkctrl: clock@20 {
1966 compatible = "ti,clkctrl";
1967 clock-output-names = "cam_clkctrl";
1968 reg = <0x20 0x2c>;
1969 #clock-cells = <2>;
1970 };
1971 };
1972
1973 dss_cm: clock@1100 {
1974 compatible = "ti,omap4-cm";
1975 clock-output-names = "dss_cm";
1976 reg = <0x1100 0x100>;
1977 #address-cells = <1>;
1978 #size-cells = <1>;
1979 ranges = <0 0x1100 0x100>;
1980
1981 dss_clkctrl: clock@20 {
1982 compatible = "ti,clkctrl";
1983 clock-output-names = "dss_clkctrl";
1984 reg = <0x20 0x14>;
1985 #clock-cells = <2>;
1986 };
1987 };
1988
1989 gpu_cm: clock@1200 {
1990 compatible = "ti,omap4-cm";
1991 clock-output-names = "gpu_cm";
1992 reg = <0x1200 0x100>;
1993 #address-cells = <1>;
1994 #size-cells = <1>;
1995 ranges = <0 0x1200 0x100>;
1996
1997 gpu_clkctrl: clock@20 {
1998 compatible = "ti,clkctrl";
1999 clock-output-names = "gpu_clkctrl";
2000 reg = <0x20 0x4>;
2001 #clock-cells = <2>;
2002 };
2003 };
2004
2005 l3init_cm: clock@1300 {
2006 compatible = "ti,omap4-cm";
2007 clock-output-names = "l3init_cm";
2008 reg = <0x1300 0x100>;
2009 #address-cells = <1>;
2010 #size-cells = <1>;
2011 ranges = <0 0x1300 0x100>;
2012
2013 l3init_clkctrl: clock@20 {
2014 compatible = "ti,clkctrl";
2015 clock-output-names = "l3init_clkctrl";
2016 reg = <0x20 0x6c>, <0xe0 0x14>;
2017 #clock-cells = <2>;
2018 };
2019
2020 pcie_clkctrl: clock@b0 {
2021 compatible = "ti,clkctrl";
2022 clock-output-names = "pcie_clkctrl";
2023 reg = <0xb0 0xc>;
2024 #clock-cells = <2>;
2025 };
2026
2027 gmac_clkctrl: clock@d0 {
2028 compatible = "ti,clkctrl";
2029 clock-output-names = "gmac_clkctrl";
2030 reg = <0xd0 0x4>;
2031 #clock-cells = <2>;
2032 };
2033
2034 };
2035
2036 l4per_cm: clock@1700 {
2037 compatible = "ti,omap4-cm";
2038 clock-output-names = "l4per_cm";
2039 reg = <0x1700 0x300>;
2040 #address-cells = <1>;
2041 #size-cells = <1>;
2042 ranges = <0 0x1700 0x300>;
2043
2044 l4per_clkctrl: clock@28 {
2045 compatible = "ti,clkctrl";
2046 clock-output-names = "l4per_clkctrl";
2047 reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
2048 #clock-cells = <2>;
2049
2050 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
2051 assigned-clock-parents = <&abe_24m_fclk>;
2052 };
2053
2054 l4sec_clkctrl: clock@1a0 {
2055 compatible = "ti,clkctrl";
2056 clock-output-names = "l4sec_clkctrl";
2057 reg = <0x1a0 0x2c>;
2058 #clock-cells = <2>;
2059 };
2060
2061 l4per2_clkctrl: clock@c {
2062 compatible = "ti,clkctrl";
2063 clock-output-names = "l4per2_clkctrl";
2064 reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
2065 #clock-cells = <2>;
2066 };
2067
2068 l4per3_clkctrl: clock@14 {
2069 compatible = "ti,clkctrl";
2070 clock-output-names = "l4per3_clkctrl";
2071 reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
2072 #clock-cells = <2>;
2073 };
2074 };
2075
2076};
2077
2078&prm {
2079 wkupaon_cm: clock@1800 {
2080 compatible = "ti,omap4-cm";
2081 clock-output-names = "wkupaon_cm";
2082 reg = <0x1800 0x100>;
2083 #address-cells = <1>;
2084 #size-cells = <1>;
2085 ranges = <0 0x1800 0x100>;
2086
2087 wkupaon_clkctrl: clock@20 {
2088 compatible = "ti,clkctrl";
2089 clock-output-names = "wkupaon_clkctrl";
2090 reg = <0x20 0x6c>;
2091 #clock-cells = <2>;
2092 };
2093 };
2094};