1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * Device Tree Source for OMAP3 clock data
  4 *
  5 * Copyright (C) 2013 Texas Instruments, Inc.
  6 */
  7&scm_clocks {
  8	emac_ick: emac_ick@32c {
  9		#clock-cells = <0>;
 10		compatible = "ti,am35xx-gate-clock";
 11		clocks = <&ipss_ick>;
 12		reg = <0x032c>;
 13		ti,bit-shift = <1>;
 14	};
 15
 16	emac_fck: emac_fck@32c {
 17		#clock-cells = <0>;
 18		compatible = "ti,gate-clock";
 19		clocks = <&rmii_ck>;
 20		reg = <0x032c>;
 21		ti,bit-shift = <9>;
 22	};
 23
 24	vpfe_ick: vpfe_ick@32c {
 25		#clock-cells = <0>;
 26		compatible = "ti,am35xx-gate-clock";
 27		clocks = <&ipss_ick>;
 28		reg = <0x032c>;
 29		ti,bit-shift = <2>;
 30	};
 31
 32	vpfe_fck: vpfe_fck@32c {
 33		#clock-cells = <0>;
 34		compatible = "ti,gate-clock";
 35		clocks = <&pclk_ck>;
 36		reg = <0x032c>;
 37		ti,bit-shift = <10>;
 38	};
 39
 40	hsotgusb_ick_am35xx: hsotgusb_ick_am35xx@32c {
 41		#clock-cells = <0>;
 42		compatible = "ti,am35xx-gate-clock";
 43		clocks = <&ipss_ick>;
 44		reg = <0x032c>;
 45		ti,bit-shift = <0>;
 46	};
 47
 48	hsotgusb_fck_am35xx: hsotgusb_fck_am35xx@32c {
 49		#clock-cells = <0>;
 50		compatible = "ti,gate-clock";
 51		clocks = <&sys_ck>;
 52		reg = <0x032c>;
 53		ti,bit-shift = <8>;
 54	};
 55
 56	hecc_ck: hecc_ck@32c {
 57		#clock-cells = <0>;
 58		compatible = "ti,am35xx-gate-clock";
 59		clocks = <&sys_ck>;
 60		reg = <0x032c>;
 61		ti,bit-shift = <3>;
 62	};
 63};
 64&cm_clocks {
 65	clock@a10 {
 66		compatible = "ti,clksel";
 67		reg = <0xa10>;
 68		#clock-cells = <2>;
 69		#address-cells = <1>;
 70		#size-cells = <0>;
 71
 72		ipss_ick: clock-ipss-ick@4 {
 73			reg = <4>;
 74			#clock-cells = <0>;
 75			compatible = "ti,am35xx-interface-clock";
 76			clock-output-names = "ipss_ick";
 77			clocks = <&core_l3_ick>;
 78		};
 79
 80		uart4_ick_am35xx: clock-uart4-ick-am35xx@23 {
 81			reg = <23>;
 82			#clock-cells = <0>;
 83			compatible = "ti,omap3-interface-clock";
 84			clock-output-names = "uart4_ick_am35xx";
 85			clocks = <&core_l4_ick>;
 86		};
 87	};
 88
 89	rmii_ck: rmii_ck {
 90		#clock-cells = <0>;
 91		compatible = "fixed-clock";
 92		clock-frequency = <50000000>;
 93	};
 94
 95	pclk_ck: pclk_ck {
 96		#clock-cells = <0>;
 97		compatible = "fixed-clock";
 98		clock-frequency = <27000000>;
 99	};
100
101	clock@a00 {
102		compatible = "ti,clksel";
103		reg = <0xa00>;
104		#clock-cells = <2>;
105		#address-cells = <1>;
106		#size-cells = <0>;
107
108		uart4_fck_am35xx: clock-uart4-fck-am35xx@23 {
109			reg = <23>;
110			#clock-cells = <0>;
111			compatible = "ti,wait-gate-clock";
112			clock-output-names = "uart4_fck_am35xx";
113			clocks = <&core_48m_fck>;
114		};
115	};
116};
117
118&cm_clockdomains {
119	core_l3_clkdm: core_l3_clkdm {
120		compatible = "ti,clockdomain";
121		clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
122			 <&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
123			 <&hecc_ck>;
124	};
125
126	core_l4_clkdm: core_l4_clkdm {
127		compatible = "ti,clockdomain";
128		clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
129			 <&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
130			 <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
131			 <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
132			 <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
133			 <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
134			 <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
135			 <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
136			 <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
137			 <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
138			 <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
139			 <&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
140	};
141};