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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Newflow Ltd - https://www.newflow.co.uk/
4 */
5/dts-v1/;
6
7#include "am33xx.dtsi"
8
9/ {
10 model = "Newflow AM335x NanoBone";
11 compatible = "ti,am33xx";
12
13 cpus {
14 cpu@0 {
15 cpu0-supply = <&dcdc2_reg>;
16 };
17 };
18
19 memory@80000000 {
20 device_type = "memory";
21 reg = <0x80000000 0x10000000>; /* 256 MB */
22 };
23
24 leds {
25 compatible = "gpio-leds";
26
27 led0 {
28 label = "nanobone:green:usr1";
29 gpios = <&gpio1 5 0>;
30 default-state = "off";
31 };
32 };
33};
34
35&am33xx_pinmux {
36 pinctrl-names = "default";
37 pinctrl-0 = <&misc_pins>;
38
39 misc_pins: misc-pins {
40 pinctrl-single,pins = <
41 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */
42 >;
43 };
44
45 gpmc_pins: gpmc-pins {
46 pinctrl-single,pins = <
47 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
48 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
49 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
50 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
51 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
52 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
53 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
54 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
55 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0)
56 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0)
57 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0)
58 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0)
59 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0)
60 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0)
61 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0)
62 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0)
63
64 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
65 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
66 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0)
67 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0)
68 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0)
69
70 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
71 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
72 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
73 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
74
75 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */
76 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */
77 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */
78 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */
79 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */
80 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */
81 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */
82
83 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */
84 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */
85 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */
86 >;
87 };
88
89 i2c0_pins: i2c0-pins {
90 pinctrl-single,pins = <
91 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0)
92 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0)
93 >;
94 };
95
96 uart0_pins: uart0-pins {
97 pinctrl-single,pins = <
98 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
99 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)
100 >;
101 };
102
103 uart1_pins: uart1-pins {
104 pinctrl-single,pins = <
105 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7)
106 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7)
107 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
108 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)
109 >;
110 };
111
112 uart2_pins: uart2-pins {
113 pinctrl-single,pins = <
114 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */
115 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */
116 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */
117 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */
118 >;
119 };
120
121 uart3_pins: uart3-pins {
122 pinctrl-single,pins = <
123 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */
124 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */
125 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */
126 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
127 >;
128 };
129
130 uart4_pins: uart4-pins {
131 pinctrl-single,pins = <
132 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */
133 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */
134 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */
135 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */
136 >;
137 };
138
139 uart5_pins: uart5-pins {
140 pinctrl-single,pins = <
141 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */
142 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */
143 >;
144 };
145
146 mmc1_pins: mmc1-pins {
147 pinctrl-single,pins = <
148 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
149 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
150 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
151 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
152 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */
153 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
154 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */
155 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
156 >;
157 };
158};
159
160&uart0 {
161 pinctrl-names = "default";
162 pinctrl-0 = <&uart0_pins>;
163 status = "okay";
164};
165
166&uart1 {
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart1_pins>;
169 status = "okay";
170 rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
171 rs485-rts-active-high;
172 rs485-rx-during-tx;
173 rs485-rts-delay = <1 1>;
174 linux,rs485-enabled-at-boot-time;
175};
176
177&uart2 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&uart2_pins>;
180 status = "okay";
181 rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
182 rs485-rts-active-high;
183 rs485-rts-delay = <1 1>;
184 linux,rs485-enabled-at-boot-time;
185};
186
187&uart3 {
188 pinctrl-names = "default";
189 pinctrl-0 = <&uart3_pins>;
190 rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>;
191 rs485-rts-active-high;
192 rs485-rx-during-tx;
193 rs485-rts-delay = <1 1>;
194 linux,rs485-enabled-at-boot-time;
195 status = "okay";
196};
197
198&uart4 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&uart4_pins>;
201 rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>;
202 rs485-rts-active-high;
203 rs485-rx-during-tx;
204 rs485-rts-delay = <1 1>;
205 linux,rs485-enabled-at-boot-time;
206 status = "okay";
207};
208
209&uart5 {
210 pinctrl-names = "default";
211 pinctrl-0 = <&uart5_pins>;
212 status = "okay";
213};
214
215&i2c0 {
216 status = "okay";
217 pinctrl-names = "default";
218 clock-frequency = <400000>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c0_pins>;
221
222 gpio@20 {
223 compatible = "microchip,mcp23017";
224 gpio-controller;
225 #gpio-cells = <2>;
226 reg = <0x20>;
227 };
228
229 tps: tps@24 {
230 reg = <0x24>;
231 };
232
233 temperature-sensor@48 {
234 compatible = "lm75";
235 reg = <0x48>;
236 };
237
238 eeprom@53 {
239 compatible = "microchip,24c02", "atmel,24c02";
240 reg = <0x53>;
241 pagesize = <8>;
242 };
243
244 rtc@68 {
245 compatible = "dallas,ds1307";
246 reg = <0x68>;
247 };
248};
249
250&elm {
251 status = "okay";
252};
253
254&gpmc {
255 compatible = "ti,am3352-gpmc";
256 status = "okay";
257 gpmc,num-waitpins = <2>;
258 pinctrl-names = "default";
259 pinctrl-0 = <&gpmc_pins>;
260
261 #address-cells = <2>;
262 #size-cells = <1>;
263 ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */
264 <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */
265
266 nor@0,0 {
267 reg = <0 0x00000000 0x08000000>;
268 compatible = "cfi-flash";
269 linux,mtd-name = "spansion,s29gl010p11t";
270 bank-width = <2>;
271
272 gpmc,mux-add-data = <2>;
273
274 gpmc,sync-clk-ps = <0>;
275 gpmc,cs-on-ns = <0>;
276 gpmc,cs-rd-off-ns = <160>;
277 gpmc,cs-wr-off-ns = <160>;
278 gpmc,adv-on-ns = <10>;
279 gpmc,adv-rd-off-ns = <30>;
280 gpmc,adv-wr-off-ns = <30>;
281 gpmc,oe-on-ns = <40>;
282 gpmc,oe-off-ns = <160>;
283 gpmc,we-on-ns = <40>;
284 gpmc,we-off-ns = <160>;
285 gpmc,rd-cycle-ns = <160>;
286 gpmc,wr-cycle-ns = <160>;
287 gpmc,access-ns = <150>;
288 gpmc,page-burst-access-ns = <10>;
289 gpmc,cycle2cycle-samecsen;
290 gpmc,cycle2cycle-delay-ns = <20>;
291 gpmc,wr-data-mux-bus-ns = <70>;
292 gpmc,wr-access-ns = <80>;
293
294 #address-cells = <1>;
295 #size-cells = <1>;
296
297 /*
298 MTD partition table
299 ===================
300 +------------+-->0x00000000-> U-Boot start
301 | |
302 | |-->0x000BFFFF-> U-Boot end
303 | |-->0x000C0000-> ENV1 start
304 | |
305 | |-->0x000DFFFF-> ENV1 end
306 | |-->0x000E0000-> ENV2 start
307 | |
308 | |-->0x000FFFFF-> ENV2 end
309 | |-->0x00100000-> Kernel start
310 | |
311 | |-->0x004FFFFF-> Kernel end
312 | |-->0x00500000-> File system start
313 | |
314 | |-->0x01FFFFFF-> File system end
315 | |-->0x02000000-> User data start
316 | |
317 | |-->0x03FFFFFF-> User data end
318 | |-->0x04000000-> Data storage start
319 | |
320 +------------+-->0x08000000-> NOR end (Free end)
321 */
322 partition@0 {
323 label = "boot";
324 reg = <0x00000000 0x000c0000>; /* 768KB */
325 };
326
327 partition@1 {
328 label = "env1";
329 reg = <0x000c0000 0x00020000>; /* 128KB */
330 };
331
332 partition@2 {
333 label = "env2";
334 reg = <0x000e0000 0x00020000>; /* 128KB */
335 };
336
337 partition@3 {
338 label = "kernel";
339 reg = <0x00100000 0x00400000>; /* 4MB */
340 };
341
342 partition@4 {
343 label = "rootfs";
344 reg = <0x00500000 0x01b00000>; /* 27MB */
345 };
346
347 partition@5 {
348 label = "user";
349 reg = <0x02000000 0x02000000>; /* 32MB */
350 };
351
352 partition@6 {
353 label = "data";
354 reg = <0x04000000 0x04000000>; /* 64MB */
355 };
356 };
357
358 fram@1,0 {
359 reg = <1 0x00000000 0x01000000>;
360 bank-width = <2>;
361
362 gpmc,mux-add-data = <2>;
363
364 gpmc,sync-clk-ps = <0>;
365 gpmc,cs-on-ns = <0>;
366 gpmc,cs-rd-off-ns = <160>;
367 gpmc,cs-wr-off-ns = <160>;
368 gpmc,adv-on-ns = <10>;
369 gpmc,adv-rd-off-ns = <20>;
370 gpmc,adv-wr-off-ns = <20>;
371 gpmc,oe-on-ns = <30>;
372 gpmc,oe-off-ns = <150>;
373 gpmc,we-on-ns = <30>;
374 gpmc,we-off-ns = <150>;
375 gpmc,rd-cycle-ns = <160>;
376 gpmc,wr-cycle-ns = <160>;
377 gpmc,access-ns = <130>;
378 gpmc,page-burst-access-ns = <10>;
379 gpmc,cycle2cycle-samecsen;
380 gpmc,cycle2cycle-diffcsen;
381 gpmc,cycle2cycle-delay-ns = <10>;
382 gpmc,wr-data-mux-bus-ns = <30>;
383 gpmc,wr-access-ns = <0>;
384 };
385};
386
387&mac_sw {
388 status = "okay";
389};
390
391&davinci_mdio_sw {
392 status = "okay";
393
394 ethphy0: ethernet-phy@0 {
395 reg = <0>;
396 };
397
398 ethphy1: ethernet-phy@1 {
399 reg = <1>;
400 };
401};
402
403&cpsw_port1 {
404 phy-handle = <ðphy0>;
405 phy-mode = "mii";
406 ti,dual-emac-pvid = <1>;
407};
408
409&cpsw_port2 {
410 phy-handle = <ðphy1>;
411 phy-mode = "mii";
412 ti,dual-emac-pvid = <2>;
413};
414
415&mmc1 {
416 status = "okay";
417 vmmc-supply = <&ldo4_reg>;
418 pinctrl-names = "default";
419 pinctrl-0 = <&mmc1_pins>;
420 bus-width = <4>;
421 cd-debounce-delay-ms = <5>;
422 cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
423 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
424};
425
426&usb0 {
427 dr_mode = "host";
428};
429
430#include "../../tps65217.dtsi"
431
432&tps {
433 regulators {
434 dcdc1_reg: regulator@0 {
435 /* +1.5V voltage with ±4% tolerance */
436 regulator-min-microvolt = <1450000>;
437 regulator-max-microvolt = <1550000>;
438 regulator-boot-on;
439 regulator-always-on;
440 };
441
442 dcdc2_reg: regulator@1 {
443 /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
444 regulator-name = "vdd_mpu";
445 regulator-min-microvolt = <915000>;
446 regulator-max-microvolt = <1140000>;
447 regulator-boot-on;
448 regulator-always-on;
449 };
450
451 dcdc3_reg: regulator@2 {
452 /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
453 regulator-name = "vdd_core";
454 regulator-min-microvolt = <915000>;
455 regulator-max-microvolt = <1140000>;
456 regulator-boot-on;
457 regulator-always-on;
458 };
459
460 ldo1_reg: regulator@3 {
461 /* +1.8V voltage with ±4% tolerance */
462 regulator-min-microvolt = <1750000>;
463 regulator-max-microvolt = <1870000>;
464 regulator-boot-on;
465 regulator-always-on;
466 };
467
468 ldo2_reg: regulator@4 {
469 /* +3.3V voltage with ±4% tolerance */
470 regulator-min-microvolt = <3175000>;
471 regulator-max-microvolt = <3430000>;
472 regulator-boot-on;
473 regulator-always-on;
474 };
475
476 ldo3_reg: regulator@5 {
477 /* +1.8V voltage with ±4% tolerance */
478 regulator-min-microvolt = <1750000>;
479 regulator-max-microvolt = <1870000>;
480 regulator-boot-on;
481 regulator-always-on;
482 };
483
484 ldo4_reg: regulator@6 {
485 /* +3.3V voltage with ±4% tolerance */
486 regulator-min-microvolt = <3175000>;
487 regulator-max-microvolt = <3430000>;
488 regulator-boot-on;
489 regulator-always-on;
490 };
491 };
492};