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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 | /* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) */ #ifndef __ASM_IRQFLAGS_ARCOMPACT_H #define __ASM_IRQFLAGS_ARCOMPACT_H /* vineetg: March 2010 : local_irq_save( ) optimisation * -Remove explicit mov of current status32 into reg, that is not needed * -Use BIC insn instead of INVERTED + AND * -Conditionally disable interrupts (if they are not enabled, don't disable) */ #include <asm/arcregs.h> /* status32 Reg bits related to Interrupt Handling */ #define STATUS_E1_BIT 1 /* Int 1 enable */ #define STATUS_E2_BIT 2 /* Int 2 enable */ #define STATUS_A1_BIT 3 /* Int 1 active */ #define STATUS_A2_BIT 4 /* Int 2 active */ #define STATUS_AE_BIT 5 /* Exception active */ #define STATUS_E1_MASK (1<<STATUS_E1_BIT) #define STATUS_E2_MASK (1<<STATUS_E2_BIT) #define STATUS_A1_MASK (1<<STATUS_A1_BIT) #define STATUS_A2_MASK (1<<STATUS_A2_BIT) #define STATUS_AE_MASK (1<<STATUS_AE_BIT) #define STATUS_IE_MASK (STATUS_E1_MASK | STATUS_E2_MASK) /* Other Interrupt Handling related Aux regs */ #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ #define AUX_IRQ_LV12 0x43 /* interrupt level register */ #define AUX_IENABLE 0x40c #define AUX_ITRIGGER 0x40d #define AUX_IPULSE 0x415 #define ISA_INIT_STATUS_BITS STATUS_IE_MASK #ifndef __ASSEMBLY__ /****************************************************************** * IRQ Control Macros * * All of them have "memory" clobber (compiler barrier) which is needed to * ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available) * are redone after IRQs are re-enabled (and gcc doesn't reuse stale register) * * Noted at the time of Abilis Timer List corruption * * Orig Bug + Rejected solution: * https://lore.kernel.org/lkml/1364553218-31255-1-git-send-email-vgupta@synopsys.com * * Reasoning: * https://lore.kernel.org/lkml/CA+55aFyFWjpSVQM6M266tKrG_ZXJzZ-nYejpmXYQXbrr42mGPQ@mail.gmail.com * ******************************************************************/ /* * Save IRQ state and disable IRQs */ static inline long arch_local_irq_save(void) { unsigned long temp, flags; __asm__ __volatile__( " lr %1, [status32] \n" " bic %0, %1, %2 \n" " and.f 0, %1, %2 \n" " flag.nz %0 \n" : "=r"(temp), "=r"(flags) : "n"((STATUS_E1_MASK | STATUS_E2_MASK)) : "memory", "cc"); return flags; } /* * restore saved IRQ state */ static inline void arch_local_irq_restore(unsigned long flags) { __asm__ __volatile__( " flag %0 \n" : : "r"(flags) : "memory"); } /* * Unconditionally Enable IRQs */ #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS extern void arch_local_irq_enable(void); #else static inline void arch_local_irq_enable(void) { unsigned long temp; __asm__ __volatile__( " lr %0, [status32] \n" " or %0, %0, %1 \n" " flag %0 \n" : "=&r"(temp) : "n"((STATUS_E1_MASK | STATUS_E2_MASK)) : "cc", "memory"); } #endif /* * Unconditionally Disable IRQs */ static inline void arch_local_irq_disable(void) { unsigned long temp; __asm__ __volatile__( " lr %0, [status32] \n" " and %0, %0, %1 \n" " flag %0 \n" : "=&r"(temp) : "n"(~(STATUS_E1_MASK | STATUS_E2_MASK)) : "memory"); } /* * save IRQ state */ static inline long arch_local_save_flags(void) { unsigned long temp; __asm__ __volatile__( " lr %0, [status32] \n" : "=&r"(temp) : : "memory"); return temp; } /* * Query IRQ state */ static inline int arch_irqs_disabled_flags(unsigned long flags) { return !(flags & (STATUS_E1_MASK #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS | STATUS_E2_MASK #endif )); } static inline int arch_irqs_disabled(void) { return arch_irqs_disabled_flags(arch_local_save_flags()); } #else #ifdef CONFIG_TRACE_IRQFLAGS .macro TRACE_ASM_IRQ_DISABLE bl trace_hardirqs_off .endm .macro TRACE_ASM_IRQ_ENABLE bl trace_hardirqs_on .endm #else .macro TRACE_ASM_IRQ_DISABLE .endm .macro TRACE_ASM_IRQ_ENABLE .endm #endif .macro IRQ_DISABLE scratch lr \scratch, [status32] bic \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK) flag \scratch TRACE_ASM_IRQ_DISABLE .endm .macro IRQ_ENABLE scratch TRACE_ASM_IRQ_ENABLE lr \scratch, [status32] or \scratch, \scratch, (STATUS_E1_MASK | STATUS_E2_MASK) flag \scratch .endm #endif /* __ASSEMBLY__ */ #endif |