1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Qualcomm Quad Serial Peripheral Interface (QSPI)
  8
  9maintainers:
 10  - Bjorn Andersson <bjorn.andersson@linaro.org>
 11
 12description: The QSPI controller allows SPI protocol communication in single,
 13  dual, or quad wire transmission modes for read/write access to slaves such
 14  as NOR flash.
 15
 16allOf:
 17  - $ref: /schemas/spi/spi-controller.yaml#
 18
 19properties:
 20  compatible:
 21    items:
 22      - enum:
 23          - qcom,sc7180-qspi
 24          - qcom,sc7280-qspi
 25          - qcom,sdm845-qspi
 26
 27      - const: qcom,qspi-v1
 28
 29  reg:
 30    maxItems: 1
 31
 32  iommus:
 33    maxItems: 1
 34
 35  interrupts:
 36    maxItems: 1
 37
 38  clock-names:
 39    items:
 40      - const: iface
 41      - const: core
 42
 43  clocks:
 44    items:
 45      - description: AHB clock
 46      - description: QSPI core clock
 47
 48  interconnects:
 49    minItems: 1
 50    maxItems: 2
 51
 52  interconnect-names:
 53    minItems: 1
 54    items:
 55      - const: qspi-config
 56      - const: qspi-memory
 57
 58  operating-points-v2: true
 59
 60  power-domains:
 61    maxItems: 1
 62
 63required:
 64  - compatible
 65  - reg
 66  - interrupts
 67  - clock-names
 68  - clocks
 69
 70unevaluatedProperties: false
 71
 72examples:
 73  - |
 74    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 75    #include <dt-bindings/interrupt-controller/arm-gic.h>
 76
 77    soc: soc {
 78        #address-cells = <2>;
 79        #size-cells = <2>;
 80
 81        qspi: spi@88df000 {
 82            compatible = "qcom,sdm845-qspi", "qcom,qspi-v1";
 83            reg = <0 0x88df000 0 0x600>;
 84            #address-cells = <1>;
 85            #size-cells = <0>;
 86            interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 87            clock-names = "iface", "core";
 88            clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
 89                         <&gcc GCC_QSPI_CORE_CLK>;
 90
 91            flash@0 {
 92                compatible = "jedec,spi-nor";
 93                reg = <0>;
 94                spi-max-frequency = <25000000>;
 95                spi-tx-bus-width = <2>;
 96                spi-rx-bus-width = <2>;
 97            };
 98        };
 99    };
100...