1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/spi/nvidia,tegra114-spi.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: NVIDIA Tegra114 SPI controller
  8
  9maintainers:
 10  - Thierry Reding <thierry.reding@gmail.com>
 11  - Jon Hunter <jonathanh@nvidia.com>
 12
 13properties:
 14  compatible:
 15    oneOf:
 16      - const: nvidia,tegra114-spi
 17      - items:
 18          - enum:
 19              - nvidia,tegra210-spi
 20              - nvidia,tegra124-spi
 21          - const: nvidia,tegra114-spi
 22
 23  reg:
 24    maxItems: 1
 25
 26  interrupts:
 27    maxItems: 1
 28
 29  clocks:
 30    items:
 31      - description: SPI module clock
 32
 33  clock-names:
 34    items:
 35      - const: spi
 36
 37  resets:
 38    items:
 39      - description: SPI module reset
 40
 41  reset-names:
 42    items:
 43      - const: spi
 44
 45  dmas:
 46    items:
 47      - description: DMA channel for the reception FIFO
 48      - description: DMA channel for the transmission FIFO
 49
 50  dma-names:
 51    items:
 52      - const: rx
 53      - const: tx
 54
 55  spi-max-frequency:
 56    description: Maximum SPI clocking speed of the controller in Hz.
 57    $ref: /schemas/types.yaml#/definitions/uint32
 58
 59allOf:
 60  - $ref: spi-controller.yaml
 61
 62unevaluatedProperties: false
 63
 64required:
 65  - compatible
 66  - reg
 67  - interrupts
 68  - clocks
 69  - clock-names
 70  - resets
 71  - reset-names
 72  - dmas
 73  - dma-names
 74
 75examples:
 76  - |
 77    spi@7000d600 {
 78        compatible = "nvidia,tegra114-spi";
 79        reg = <0x7000d600 0x200>;
 80        interrupts = <0 82 0x04>;
 81        clocks = <&tegra_car 44>;
 82        clock-names = "spi";
 83        resets = <&tegra_car 44>;
 84        reset-names = "spi";
 85        dmas = <&apbdma 16>, <&apbdma 16>;
 86        dma-names = "rx", "tx";
 87
 88        spi-max-frequency = <25000000>;
 89
 90        #address-cells = <1>;
 91        #size-cells = <0>;
 92
 93        flash@0 {
 94            compatible = "jedec,spi-nor";
 95            reg = <0>;
 96            spi-max-frequency = <20000000>;
 97            nvidia,rx-clk-tap-delay = <0>;
 98            nvidia,tx-clk-tap-delay = <16>;
 99        };
100    };