1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2%YAML 1.2
  3---
  4$id: http://devicetree.org/schemas/pci/xlnx,xdma-host.yaml#
  5$schema: http://devicetree.org/meta-schemas/core.yaml#
  6
  7title: Xilinx XDMA PL PCIe Root Port Bridge
  8
  9maintainers:
 10  - Thippeswamy Havalige <thippeswamy.havalige@amd.com>
 11
 12allOf:
 13  - $ref: /schemas/pci/pci-bus.yaml#
 14
 15properties:
 16  compatible:
 17    const: xlnx,xdma-host-3.00
 18
 19  reg:
 20    maxItems: 1
 21
 22  ranges:
 23    maxItems: 2
 24
 25  interrupts:
 26    items:
 27      - description: interrupt asserted when miscellaneous interrupt is received.
 28      - description: msi0 interrupt asserted when an MSI is received.
 29      - description: msi1 interrupt asserted when an MSI is received.
 30
 31  interrupt-names:
 32    items:
 33      - const: misc
 34      - const: msi0
 35      - const: msi1
 36
 37  interrupt-map-mask:
 38    items:
 39      - const: 0
 40      - const: 0
 41      - const: 0
 42      - const: 7
 43
 44  interrupt-map:
 45    maxItems: 4
 46
 47  "#interrupt-cells":
 48    const: 1
 49
 50  interrupt-controller:
 51    description: identifies the node as an interrupt controller
 52    type: object
 53    properties:
 54      interrupt-controller: true
 55
 56      "#address-cells":
 57        const: 0
 58
 59      "#interrupt-cells":
 60        const: 1
 61
 62    required:
 63      - interrupt-controller
 64      - "#address-cells"
 65      - "#interrupt-cells"
 66
 67    additionalProperties: false
 68
 69required:
 70  - compatible
 71  - reg
 72  - ranges
 73  - interrupts
 74  - interrupt-map
 75  - interrupt-map-mask
 76  - "#interrupt-cells"
 77  - interrupt-controller
 78
 79unevaluatedProperties: false
 80
 81examples:
 82
 83  - |
 84    #include <dt-bindings/interrupt-controller/arm-gic.h>
 85    #include <dt-bindings/interrupt-controller/irq.h>
 86
 87    soc {
 88        #address-cells = <2>;
 89        #size-cells = <2>;
 90        pcie@a0000000 {
 91            compatible = "xlnx,xdma-host-3.00";
 92            reg = <0x0 0xa0000000 0x0 0x10000000>;
 93            ranges = <0x2000000 0x0 0xb0000000 0x0 0xb0000000 0x0 0x1000000>,
 94                     <0x43000000 0x5 0x0 0x5 0x0 0x0 0x1000000>;
 95            #address-cells = <3>;
 96            #size-cells = <2>;
 97            #interrupt-cells = <1>;
 98            device_type = "pci";
 99            interrupt-parent = <&gic>;
100            interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
101                         <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
102            interrupt-names = "misc", "msi0", "msi1";
103            interrupt-map-mask = <0x0 0x0 0x0 0x7>;
104            interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
105                            <0 0 0 2 &pcie_intc_0 1>,
106                            <0 0 0 3 &pcie_intc_0 2>,
107                            <0 0 0 4 &pcie_intc_0 3>;
108            pcie_intc_0: interrupt-controller {
109                #address-cells = <0>;
110                #interrupt-cells = <1>;
111                interrupt-controller;
112            };
113        };
114    };