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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/iopoll.h>
7#include <linux/sched.h>
8
9#include "ixgbe.h"
10#include "ixgbe_phy.h"
11
12static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25static int ixgbe_get_phy_id(struct ixgbe_hw *hw);
26static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28/**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
35static int ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36{
37 int status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43}
44
45/**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
52static int ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53{
54 int status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61}
62
63/**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71{
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76}
77
78/**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
88int ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90{
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return -EBUSY;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return -EIO;
154}
155
156/**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
166int ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168{
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return -EBUSY;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return -EIO;
219}
220
221/**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229{
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255}
256
257/**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
263int ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264{
265 u32 status = -EFAULT;
266 u32 phy_addr;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
280 hw->phy.nw_mng_if_sel);
281 if (ixgbe_probe_phy(hw, phy_addr))
282 return 0;
283 else
284 return -EFAULT;
285 }
286
287 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
288 if (ixgbe_probe_phy(hw, phy_addr)) {
289 status = 0;
290 break;
291 }
292 }
293
294 /* Certain media types do not have a phy so an address will not
295 * be found and the code will take this path. Caller has to
296 * decide if it is an error or not.
297 */
298 if (status)
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
300
301 return status;
302}
303
304/**
305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
306 * @hw: pointer to the hardware structure
307 *
308 * This function checks the MMNGC.MNG_VETO bit to see if there are
309 * any constraints on link from manageability. For MAC's that don't
310 * have this bit just return false since the link can not be blocked
311 * via this method.
312 **/
313bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
314{
315 u32 mmngc;
316
317 /* If we don't have this bit, it can't be blocking */
318 if (hw->mac.type == ixgbe_mac_82598EB)
319 return false;
320
321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
322 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
323 hw_dbg(hw, "MNG_VETO bit detected.\n");
324 return true;
325 }
326
327 return false;
328}
329
330/**
331 * ixgbe_get_phy_id - Get the phy type
332 * @hw: pointer to hardware structure
333 *
334 **/
335static int ixgbe_get_phy_id(struct ixgbe_hw *hw)
336{
337 u16 phy_id_high = 0;
338 u16 phy_id_low = 0;
339 int status;
340
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
342 &phy_id_high);
343
344 if (!status) {
345 hw->phy.id = (u32)(phy_id_high << 16);
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
347 &phy_id_low);
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
350 }
351 return status;
352}
353
354/**
355 * ixgbe_get_phy_type_from_id - Get the phy type
356 * @phy_id: hardware phy id
357 *
358 **/
359static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
360{
361 enum ixgbe_phy_type phy_type;
362
363 switch (phy_id) {
364 case TN1010_PHY_ID:
365 phy_type = ixgbe_phy_tn;
366 break;
367 case X550_PHY_ID2:
368 case X550_PHY_ID3:
369 case X540_PHY_ID:
370 phy_type = ixgbe_phy_aq;
371 break;
372 case QT2022_PHY_ID:
373 phy_type = ixgbe_phy_qt;
374 break;
375 case ATH_PHY_ID:
376 phy_type = ixgbe_phy_nl;
377 break;
378 case X557_PHY_ID:
379 case X557_PHY_ID2:
380 phy_type = ixgbe_phy_x550em_ext_t;
381 break;
382 case BCM54616S_E_PHY_ID:
383 phy_type = ixgbe_phy_ext_1g_t;
384 break;
385 default:
386 phy_type = ixgbe_phy_unknown;
387 break;
388 }
389
390 return phy_type;
391}
392
393/**
394 * ixgbe_reset_phy_generic - Performs a PHY reset
395 * @hw: pointer to hardware structure
396 **/
397int ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
398{
399 u32 i;
400 u16 ctrl = 0;
401 int status = 0;
402
403 if (hw->phy.type == ixgbe_phy_unknown)
404 status = ixgbe_identify_phy_generic(hw);
405
406 if (status != 0 || hw->phy.type == ixgbe_phy_none)
407 return status;
408
409 /* Don't reset PHY if it's shut down due to overtemp. */
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
411 return 0;
412
413 /* Blocked by MNG FW so bail */
414 if (ixgbe_check_reset_blocked(hw))
415 return 0;
416
417 /*
418 * Perform soft PHY reset to the PHY_XS.
419 * This will cause a soft reset to the PHY
420 */
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
422 MDIO_MMD_PHYXS,
423 MDIO_CTRL1_RESET);
424
425 /*
426 * Poll for reset bit to self-clear indicating reset is complete.
427 * Some PHYs could take up to 3 seconds to complete and need about
428 * 1.7 usec delay after the reset is complete.
429 */
430 for (i = 0; i < 30; i++) {
431 msleep(100);
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
433 status = hw->phy.ops.read_reg(hw,
434 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
435 MDIO_MMD_PMAPMD, &ctrl);
436 if (status)
437 return status;
438
439 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
440 udelay(2);
441 break;
442 }
443 } else {
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
445 MDIO_MMD_PHYXS, &ctrl);
446 if (status)
447 return status;
448
449 if (!(ctrl & MDIO_CTRL1_RESET)) {
450 udelay(2);
451 break;
452 }
453 }
454 }
455
456 if (ctrl & MDIO_CTRL1_RESET) {
457 hw_dbg(hw, "PHY reset polling failed to complete.\n");
458 return -EIO;
459 }
460
461 return 0;
462}
463
464/**
465 * ixgbe_read_phy_reg_mdi - read PHY register
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
469 * @phy_data: Pointer to read data from PHY register
470 *
471 * Reads a value from a specified PHY register without the SWFW lock
472 **/
473int ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
474 u16 *phy_data)
475{
476 u32 i, data, command;
477
478 /* Setup and write the address cycle command */
479 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
480 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
482 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
483
484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
485
486 /* Check every 10 usec to see if the address cycle completed.
487 * The MDI Command bit will clear when the operation is
488 * complete
489 */
490 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
491 udelay(10);
492
493 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
494 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
495 break;
496 }
497
498
499 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
500 hw_dbg(hw, "PHY address command did not complete.\n");
501 return -EIO;
502 }
503
504 /* Address cycle complete, setup and write the read
505 * command
506 */
507 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
508 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
510 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
511
512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
513
514 /* Check every 10 usec to see if the address cycle
515 * completed. The MDI Command bit will clear when the
516 * operation is complete
517 */
518 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
519 udelay(10);
520
521 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
522 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
523 break;
524 }
525
526 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
527 hw_dbg(hw, "PHY read command didn't complete\n");
528 return -EIO;
529 }
530
531 /* Read operation is complete. Get the data
532 * from MSRWD
533 */
534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
535 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
536 *phy_data = (u16)(data);
537
538 return 0;
539}
540
541/**
542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
543 * using the SWFW lock - this function is needed in most cases
544 * @hw: pointer to hardware structure
545 * @reg_addr: 32 bit address of PHY register to read
546 * @device_type: 5 bit device type
547 * @phy_data: Pointer to read data from PHY register
548 **/
549int ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
550 u32 device_type, u16 *phy_data)
551{
552 u32 gssr = hw->phy.phy_semaphore_mask;
553 int status;
554
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
557 phy_data);
558 hw->mac.ops.release_swfw_sync(hw, gssr);
559 } else {
560 return -EBUSY;
561 }
562
563 return status;
564}
565
566/**
567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
568 * without SWFW lock
569 * @hw: pointer to hardware structure
570 * @reg_addr: 32 bit PHY register to write
571 * @device_type: 5 bit device type
572 * @phy_data: Data to write to the PHY register
573 **/
574int ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
575 u16 phy_data)
576{
577 u32 i, command;
578
579 /* Put the data in the MDI single read and write data register*/
580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
581
582 /* Setup and write the address cycle command */
583 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
584 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
586 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
587
588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
589
590 /*
591 * Check every 10 usec to see if the address cycle completed.
592 * The MDI Command bit will clear when the operation is
593 * complete
594 */
595 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
596 udelay(10);
597
598 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
599 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
600 break;
601 }
602
603 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
604 hw_dbg(hw, "PHY address cmd didn't complete\n");
605 return -EIO;
606 }
607
608 /*
609 * Address cycle complete, setup and write the write
610 * command
611 */
612 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
613 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
615 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
616
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618
619 /* Check every 10 usec to see if the address cycle
620 * completed. The MDI Command bit will clear when the
621 * operation is complete
622 */
623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
624 udelay(10);
625
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
628 break;
629 }
630
631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
632 hw_dbg(hw, "PHY write cmd didn't complete\n");
633 return -EIO;
634 }
635
636 return 0;
637}
638
639/**
640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
641 * using SWFW lock- this function is needed in most cases
642 * @hw: pointer to hardware structure
643 * @reg_addr: 32 bit PHY register to write
644 * @device_type: 5 bit device type
645 * @phy_data: Data to write to the PHY register
646 **/
647int ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
648 u32 device_type, u16 phy_data)
649{
650 u32 gssr = hw->phy.phy_semaphore_mask;
651 int status;
652
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
655 phy_data);
656 hw->mac.ops.release_swfw_sync(hw, gssr);
657 } else {
658 return -EBUSY;
659 }
660
661 return status;
662}
663
664#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
665
666/**
667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
668 * @hw: pointer to hardware structure
669 * @cmd: command register value to write
670 **/
671static int ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
672{
673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
674
675 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
676 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
677 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
678}
679
680/**
681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
682 * @hw: pointer to hardware structure
683 * @addr: address
684 * @regnum: register number
685 * @gssr: semaphore flags to acquire
686 **/
687static int ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
688 int regnum, u32 gssr)
689{
690 u32 hwaddr, cmd;
691 int data;
692
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
694 return -EBUSY;
695
696 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
697 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
698 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
699 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
700
701 data = ixgbe_msca_cmd(hw, cmd);
702 if (data < 0)
703 goto mii_bus_read_done;
704
705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
706 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
707
708mii_bus_read_done:
709 hw->mac.ops.release_swfw_sync(hw, gssr);
710 return data;
711}
712
713/**
714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
715 * @hw: pointer to hardware structure
716 * @addr: address
717 * @devad: device address to read
718 * @regnum: register number
719 * @gssr: semaphore flags to acquire
720 **/
721static int ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
722 int devad, int regnum, u32 gssr)
723{
724 u32 hwaddr, cmd;
725 int data;
726
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
728 return -EBUSY;
729
730 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
731 hwaddr |= devad << 16 | regnum;
732 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
733
734 data = ixgbe_msca_cmd(hw, cmd);
735 if (data < 0)
736 goto mii_bus_read_done;
737
738 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
739 data = ixgbe_msca_cmd(hw, cmd);
740 if (data < 0)
741 goto mii_bus_read_done;
742
743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
744 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
745
746mii_bus_read_done:
747 hw->mac.ops.release_swfw_sync(hw, gssr);
748 return data;
749}
750
751/**
752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
753 * @hw: pointer to hardware structure
754 * @addr: address
755 * @regnum: register number
756 * @val: value to write
757 * @gssr: semaphore flags to acquire
758 **/
759static int ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
760 int regnum, u16 val, u32 gssr)
761{
762 u32 hwaddr, cmd;
763 int err;
764
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
766 return -EBUSY;
767
768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
769
770 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
771 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
772 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
773 IXGBE_MSCA_MDI_COMMAND;
774
775 err = ixgbe_msca_cmd(hw, cmd);
776
777 hw->mac.ops.release_swfw_sync(hw, gssr);
778 return err;
779}
780
781/**
782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
783 * @hw: pointer to hardware structure
784 * @addr: address
785 * @devad: device address to read
786 * @regnum: register number
787 * @val: value to write
788 * @gssr: semaphore flags to acquire
789 **/
790static int ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
791 int devad, int regnum, u16 val,
792 u32 gssr)
793{
794 u32 hwaddr, cmd;
795 int err;
796
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
798 return -EBUSY;
799
800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
801
802 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
803 hwaddr |= devad << 16 | regnum;
804 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
805
806 err = ixgbe_msca_cmd(hw, cmd);
807 if (err < 0)
808 goto mii_bus_write_done;
809
810 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
811 err = ixgbe_msca_cmd(hw, cmd);
812
813mii_bus_write_done:
814 hw->mac.ops.release_swfw_sync(hw, gssr);
815 return err;
816}
817
818/**
819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register
820 * @bus: pointer to mii_bus structure which points to our driver private
821 * @addr: address
822 * @regnum: register number
823 **/
824static int ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum)
825{
826 struct ixgbe_adapter *adapter = bus->priv;
827 struct ixgbe_hw *hw = &adapter->hw;
828 u32 gssr = hw->phy.phy_semaphore_mask;
829
830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
831}
832
833/**
834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register
835 * @bus: pointer to mii_bus structure which points to our driver private
836 * @devad: device address to read
837 * @addr: address
838 * @regnum: register number
839 **/
840static int ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr,
841 int regnum)
842{
843 struct ixgbe_adapter *adapter = bus->priv;
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 gssr = hw->phy.phy_semaphore_mask;
846
847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
848}
849
850/**
851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register
852 * @bus: pointer to mii_bus structure which points to our driver private
853 * @addr: address
854 * @regnum: register number
855 * @val: value to write
856 **/
857static int ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum,
858 u16 val)
859{
860 struct ixgbe_adapter *adapter = bus->priv;
861 struct ixgbe_hw *hw = &adapter->hw;
862 u32 gssr = hw->phy.phy_semaphore_mask;
863
864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
865}
866
867/**
868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register
869 * @bus: pointer to mii_bus structure which points to our driver private
870 * @addr: address
871 * @devad: device address to read
872 * @regnum: register number
873 * @val: value to write
874 **/
875static int ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad,
876 int regnum, u16 val)
877{
878 struct ixgbe_adapter *adapter = bus->priv;
879 struct ixgbe_hw *hw = &adapter->hw;
880 u32 gssr = hw->phy.phy_semaphore_mask;
881
882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
883 gssr);
884}
885
886/**
887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
888 * @bus: pointer to mii_bus structure which points to our driver private
889 * @addr: address
890 * @regnum: register number
891 **/
892static int ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr,
893 int regnum)
894{
895 struct ixgbe_adapter *adapter = bus->priv;
896 struct ixgbe_hw *hw = &adapter->hw;
897 u32 gssr = hw->phy.phy_semaphore_mask;
898
899 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
901}
902
903/**
904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
905 * @bus: pointer to mii_bus structure which points to our driver private
906 * @addr: address
907 * @devad: device address to read
908 * @regnum: register number
909 **/
910static int ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr,
911 int devad, int regnum)
912{
913 struct ixgbe_adapter *adapter = bus->priv;
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 gssr = hw->phy.phy_semaphore_mask;
916
917 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
919}
920
921/**
922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
923 * @bus: pointer to mii_bus structure which points to our driver private
924 * @addr: address
925 * @regnum: register number
926 * @val: value to write
927 **/
928static int ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr,
929 int regnum, u16 val)
930{
931 struct ixgbe_adapter *adapter = bus->priv;
932 struct ixgbe_hw *hw = &adapter->hw;
933 u32 gssr = hw->phy.phy_semaphore_mask;
934
935 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
937}
938
939/**
940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
941 * @bus: pointer to mii_bus structure which points to our driver private
942 * @addr: address
943 * @devad: device address to read
944 * @regnum: register number
945 * @val: value to write
946 **/
947static int ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr,
948 int devad, int regnum, u16 val)
949{
950 struct ixgbe_adapter *adapter = bus->priv;
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 gssr = hw->phy.phy_semaphore_mask;
953
954 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
956 gssr);
957}
958
959/**
960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
961 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
962 *
963 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
964 * on domain 0, bus 0, devfn = 'devfn'
965 **/
966static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
967{
968 struct pci_dev *rp_pdev;
969 int bus;
970
971 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
972 if (rp_pdev && rp_pdev->subordinate) {
973 bus = rp_pdev->subordinate->number;
974 pci_dev_put(rp_pdev);
975 return pci_get_domain_bus_and_slot(0, bus, 0);
976 }
977
978 pci_dev_put(rp_pdev);
979 return NULL;
980}
981
982/**
983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
984 * @hw: pointer to hardware structure
985 *
986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
987 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
988 * but we only want to register one MDIO bus.
989 **/
990static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
991{
992 struct ixgbe_adapter *adapter = hw->back;
993 struct pci_dev *pdev = adapter->pdev;
994 struct pci_dev *func0_pdev;
995 bool has_mii = false;
996
997 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
998 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
999 * It's not valid for function 0 to be disabled and function 1 is up,
1000 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
1001 * of those two root ports
1002 */
1003 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
1004 if (func0_pdev) {
1005 if (func0_pdev == pdev)
1006 has_mii = true;
1007 goto out;
1008 }
1009 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
1010 if (func0_pdev == pdev)
1011 has_mii = true;
1012
1013out:
1014 pci_dev_put(func0_pdev);
1015 return has_mii;
1016}
1017
1018/**
1019 * ixgbe_mii_bus_init - mii_bus structure setup
1020 * @hw: pointer to hardware structure
1021 *
1022 * Returns 0 on success, negative on failure
1023 *
1024 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
1025 **/
1026int ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1027{
1028 int (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val);
1029 int (*read_c22)(struct mii_bus *bus, int addr, int regnum);
1030 int (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum,
1031 u16 val);
1032 int (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum);
1033 struct ixgbe_adapter *adapter = hw->back;
1034 struct pci_dev *pdev = adapter->pdev;
1035 struct device *dev = &adapter->netdev->dev;
1036 struct mii_bus *bus;
1037
1038 switch (hw->device_id) {
1039 /* C3000 SoCs */
1040 case IXGBE_DEV_ID_X550EM_A_KR:
1041 case IXGBE_DEV_ID_X550EM_A_KR_L:
1042 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1043 case IXGBE_DEV_ID_X550EM_A_SGMII:
1044 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1045 case IXGBE_DEV_ID_X550EM_A_10G_T:
1046 case IXGBE_DEV_ID_X550EM_A_SFP:
1047 case IXGBE_DEV_ID_X550EM_A_1G_T:
1048 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1049 if (!ixgbe_x550em_a_has_mii(hw))
1050 return 0;
1051 read_c22 = ixgbe_x550em_a_mii_bus_read_c22;
1052 write_c22 = ixgbe_x550em_a_mii_bus_write_c22;
1053 read_c45 = ixgbe_x550em_a_mii_bus_read_c45;
1054 write_c45 = ixgbe_x550em_a_mii_bus_write_c45;
1055 break;
1056 default:
1057 read_c22 = ixgbe_mii_bus_read_c22;
1058 write_c22 = ixgbe_mii_bus_write_c22;
1059 read_c45 = ixgbe_mii_bus_read_c45;
1060 write_c45 = ixgbe_mii_bus_write_c45;
1061 break;
1062 }
1063
1064 bus = devm_mdiobus_alloc(dev);
1065 if (!bus)
1066 return -ENOMEM;
1067
1068 bus->read = read_c22;
1069 bus->write = write_c22;
1070 bus->read_c45 = read_c45;
1071 bus->write_c45 = write_c45;
1072
1073 /* Use the position of the device in the PCI hierarchy as the id */
1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
1075 pci_name(pdev));
1076
1077 bus->name = "ixgbe-mdio";
1078 bus->priv = adapter;
1079 bus->parent = dev;
1080 bus->phy_mask = GENMASK(31, 0);
1081
1082 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
1083 * unfortunately that causes some clause 22 frames to be sent with
1084 * clause 45 addressing. We don't want that.
1085 */
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1087
1088 adapter->mii_bus = bus;
1089 return mdiobus_register(bus);
1090}
1091
1092/**
1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg
1094 * @hw: pointer to hardware structure
1095 *
1096 * Restart autonegotiation and PHY and waits for completion.
1097 **/
1098int ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1099{
1100 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1101 ixgbe_link_speed speed;
1102 bool autoneg = false;
1103 int status = 0;
1104
1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1106
1107 /* Set or unset auto-negotiation 10G advertisement */
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1109
1110 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1112 (speed & IXGBE_LINK_SPEED_10GB_FULL))
1113 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1114
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1116
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1118 MDIO_MMD_AN, &autoneg_reg);
1119
1120 if (hw->mac.type == ixgbe_mac_X550) {
1121 /* Set or unset auto-negotiation 5G advertisement */
1122 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1124 (speed & IXGBE_LINK_SPEED_5GB_FULL))
1125 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1126
1127 /* Set or unset auto-negotiation 2.5G advertisement */
1128 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1129 if ((hw->phy.autoneg_advertised &
1130 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1131 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1132 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1133 }
1134
1135 /* Set or unset auto-negotiation 1G advertisement */
1136 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1138 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1139 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1140
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1142 MDIO_MMD_AN, autoneg_reg);
1143
1144 /* Set or unset auto-negotiation 100M advertisement */
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1146
1147 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1149 (speed & IXGBE_LINK_SPEED_100_FULL))
1150 autoneg_reg |= ADVERTISE_100FULL;
1151
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1153
1154 /* Blocked by MNG FW so don't reset PHY */
1155 if (ixgbe_check_reset_blocked(hw))
1156 return 0;
1157
1158 /* Restart PHY autonegotiation and wait for completion */
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1160 MDIO_MMD_AN, &autoneg_reg);
1161
1162 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1163
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1165 MDIO_MMD_AN, autoneg_reg);
1166
1167 return status;
1168}
1169
1170/**
1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1172 * @hw: pointer to hardware structure
1173 * @speed: new link speed
1174 * @autoneg_wait_to_complete: unused
1175 **/
1176int ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1177 ixgbe_link_speed speed,
1178 bool autoneg_wait_to_complete)
1179{
1180 /* Clear autoneg_advertised and set new values based on input link
1181 * speed.
1182 */
1183 hw->phy.autoneg_advertised = 0;
1184
1185 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1187
1188 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1190
1191 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1193
1194 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1196
1197 if (speed & IXGBE_LINK_SPEED_100_FULL)
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1199
1200 if (speed & IXGBE_LINK_SPEED_10_FULL)
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1202
1203 /* Setup link based on the new speed settings */
1204 if (hw->phy.ops.setup_link)
1205 hw->phy.ops.setup_link(hw);
1206
1207 return 0;
1208}
1209
1210/**
1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1212 * @hw: pointer to hardware structure
1213 *
1214 * Determines the supported link capabilities by reading the PHY auto
1215 * negotiation register.
1216 */
1217static int ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1218{
1219 u16 speed_ability;
1220 int status;
1221
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1223 &speed_ability);
1224 if (status)
1225 return status;
1226
1227 if (speed_ability & MDIO_SPEED_10G)
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1229 if (speed_ability & MDIO_PMA_SPEED_1000)
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1231 if (speed_ability & MDIO_PMA_SPEED_100)
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1233
1234 switch (hw->mac.type) {
1235 case ixgbe_mac_X550:
1236 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1238 break;
1239 case ixgbe_mac_X550EM_x:
1240 case ixgbe_mac_x550em_a:
1241 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1242 break;
1243 default:
1244 break;
1245 }
1246
1247 return 0;
1248}
1249
1250/**
1251 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1252 * @hw: pointer to hardware structure
1253 * @speed: pointer to link speed
1254 * @autoneg: boolean auto-negotiation value
1255 */
1256int ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1257 ixgbe_link_speed *speed,
1258 bool *autoneg)
1259{
1260 int status = 0;
1261
1262 *autoneg = true;
1263 if (!hw->phy.speeds_supported)
1264 status = ixgbe_get_copper_speeds_supported(hw);
1265
1266 *speed = hw->phy.speeds_supported;
1267 return status;
1268}
1269
1270/**
1271 * ixgbe_check_phy_link_tnx - Determine link and speed status
1272 * @hw: pointer to hardware structure
1273 * @speed: link speed
1274 * @link_up: status of link
1275 *
1276 * Reads the VS1 register to determine if link is up and the current speed for
1277 * the PHY.
1278 **/
1279int ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1280 bool *link_up)
1281{
1282 u32 max_time_out = 10;
1283 u16 phy_speed = 0;
1284 u16 phy_link = 0;
1285 u16 phy_data = 0;
1286 u32 time_out;
1287 int status;
1288
1289 /* Initialize speed and link to default case */
1290 *link_up = false;
1291 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1292
1293 /*
1294 * Check current speed and link status of the PHY register.
1295 * This is a vendor specific register and may have to
1296 * be changed for other copper PHYs.
1297 */
1298 for (time_out = 0; time_out < max_time_out; time_out++) {
1299 udelay(10);
1300 status = hw->phy.ops.read_reg(hw,
1301 MDIO_STAT1,
1302 MDIO_MMD_VEND1,
1303 &phy_data);
1304 phy_link = phy_data &
1305 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1306 phy_speed = phy_data &
1307 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1308 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1309 *link_up = true;
1310 if (phy_speed ==
1311 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1312 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1313 break;
1314 }
1315 }
1316
1317 return status;
1318}
1319
1320/**
1321 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1322 * @hw: pointer to hardware structure
1323 *
1324 * Restart autonegotiation and PHY and waits for completion.
1325 * This function always returns success, this is nessary since
1326 * it is called via a function pointer that could call other
1327 * functions that could return an error.
1328 **/
1329int ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1330{
1331 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1332 bool autoneg = false;
1333 ixgbe_link_speed speed;
1334
1335 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1336
1337 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1338 /* Set or unset auto-negotiation 10G advertisement */
1339 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1340 MDIO_MMD_AN,
1341 &autoneg_reg);
1342
1343 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1344 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1345 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1346
1347 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1348 MDIO_MMD_AN,
1349 autoneg_reg);
1350 }
1351
1352 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1353 /* Set or unset auto-negotiation 1G advertisement */
1354 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1355 MDIO_MMD_AN,
1356 &autoneg_reg);
1357
1358 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1359 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1360 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1361
1362 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1363 MDIO_MMD_AN,
1364 autoneg_reg);
1365 }
1366
1367 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1368 /* Set or unset auto-negotiation 100M advertisement */
1369 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1370 MDIO_MMD_AN,
1371 &autoneg_reg);
1372
1373 autoneg_reg &= ~(ADVERTISE_100FULL |
1374 ADVERTISE_100HALF);
1375 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1376 autoneg_reg |= ADVERTISE_100FULL;
1377
1378 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1379 MDIO_MMD_AN,
1380 autoneg_reg);
1381 }
1382
1383 /* Blocked by MNG FW so don't reset PHY */
1384 if (ixgbe_check_reset_blocked(hw))
1385 return 0;
1386
1387 /* Restart PHY autonegotiation and wait for completion */
1388 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1389 MDIO_MMD_AN, &autoneg_reg);
1390
1391 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1392
1393 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1394 MDIO_MMD_AN, autoneg_reg);
1395 return 0;
1396}
1397
1398/**
1399 * ixgbe_reset_phy_nl - Performs a PHY reset
1400 * @hw: pointer to hardware structure
1401 **/
1402int ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1403{
1404 u16 phy_offset, control, eword, edata, block_crc;
1405 u16 list_offset, data_offset;
1406 bool end_data = false;
1407 u16 phy_data = 0;
1408 int ret_val;
1409 u32 i;
1410
1411 /* Blocked by MNG FW so bail */
1412 if (ixgbe_check_reset_blocked(hw))
1413 return 0;
1414
1415 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1416
1417 /* reset the PHY and poll for completion */
1418 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1419 (phy_data | MDIO_CTRL1_RESET));
1420
1421 for (i = 0; i < 100; i++) {
1422 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1423 &phy_data);
1424 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1425 break;
1426 usleep_range(10000, 20000);
1427 }
1428
1429 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1430 hw_dbg(hw, "PHY reset did not complete.\n");
1431 return -EIO;
1432 }
1433
1434 /* Get init offsets */
1435 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1436 &data_offset);
1437 if (ret_val)
1438 return ret_val;
1439
1440 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1441 data_offset++;
1442 while (!end_data) {
1443 /*
1444 * Read control word from PHY init contents offset
1445 */
1446 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1447 if (ret_val)
1448 goto err_eeprom;
1449 control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword);
1450 edata = eword & IXGBE_DATA_MASK_NL;
1451 switch (control) {
1452 case IXGBE_DELAY_NL:
1453 data_offset++;
1454 hw_dbg(hw, "DELAY: %d MS\n", edata);
1455 usleep_range(edata * 1000, edata * 2000);
1456 break;
1457 case IXGBE_DATA_NL:
1458 hw_dbg(hw, "DATA:\n");
1459 data_offset++;
1460 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1461 &phy_offset);
1462 if (ret_val)
1463 goto err_eeprom;
1464 for (i = 0; i < edata; i++) {
1465 ret_val = hw->eeprom.ops.read(hw, data_offset,
1466 &eword);
1467 if (ret_val)
1468 goto err_eeprom;
1469 hw->phy.ops.write_reg(hw, phy_offset,
1470 MDIO_MMD_PMAPMD, eword);
1471 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1472 phy_offset);
1473 data_offset++;
1474 phy_offset++;
1475 }
1476 break;
1477 case IXGBE_CONTROL_NL:
1478 data_offset++;
1479 hw_dbg(hw, "CONTROL:\n");
1480 if (edata == IXGBE_CONTROL_EOL_NL) {
1481 hw_dbg(hw, "EOL\n");
1482 end_data = true;
1483 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1484 hw_dbg(hw, "SOL\n");
1485 } else {
1486 hw_dbg(hw, "Bad control value\n");
1487 return -EIO;
1488 }
1489 break;
1490 default:
1491 hw_dbg(hw, "Bad control type\n");
1492 return -EIO;
1493 }
1494 }
1495
1496 return ret_val;
1497
1498err_eeprom:
1499 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1500 return -EIO;
1501}
1502
1503/**
1504 * ixgbe_identify_module_generic - Identifies module type
1505 * @hw: pointer to hardware structure
1506 *
1507 * Determines HW type and calls appropriate function.
1508 **/
1509int ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1510{
1511 switch (hw->mac.ops.get_media_type(hw)) {
1512 case ixgbe_media_type_fiber:
1513 return ixgbe_identify_sfp_module_generic(hw);
1514 case ixgbe_media_type_fiber_qsfp:
1515 return ixgbe_identify_qsfp_module_generic(hw);
1516 default:
1517 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1518 return -ENOENT;
1519 }
1520
1521 return -ENOENT;
1522}
1523
1524/**
1525 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1526 * @hw: pointer to hardware structure
1527 *
1528 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1529 **/
1530int ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1531{
1532 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1533 struct ixgbe_adapter *adapter = hw->back;
1534 u8 oui_bytes[3] = {0, 0, 0};
1535 u8 bitrate_nominal = 0;
1536 u8 comp_codes_10g = 0;
1537 u8 comp_codes_1g = 0;
1538 u16 enforce_sfp = 0;
1539 u32 vendor_oui = 0;
1540 u8 identifier = 0;
1541 u8 cable_tech = 0;
1542 u8 cable_spec = 0;
1543 int status;
1544
1545 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1546 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1547 return -ENOENT;
1548 }
1549
1550 /* LAN ID is needed for sfp_type determination */
1551 hw->mac.ops.set_lan_id(hw);
1552
1553 status = hw->phy.ops.read_i2c_eeprom(hw,
1554 IXGBE_SFF_IDENTIFIER,
1555 &identifier);
1556
1557 if (status)
1558 goto err_read_i2c_eeprom;
1559
1560 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1561 hw->phy.type = ixgbe_phy_sfp_unsupported;
1562 return -EOPNOTSUPP;
1563 }
1564 status = hw->phy.ops.read_i2c_eeprom(hw,
1565 IXGBE_SFF_1GBE_COMP_CODES,
1566 &comp_codes_1g);
1567
1568 if (status)
1569 goto err_read_i2c_eeprom;
1570
1571 status = hw->phy.ops.read_i2c_eeprom(hw,
1572 IXGBE_SFF_10GBE_COMP_CODES,
1573 &comp_codes_10g);
1574
1575 if (status)
1576 goto err_read_i2c_eeprom;
1577 status = hw->phy.ops.read_i2c_eeprom(hw,
1578 IXGBE_SFF_CABLE_TECHNOLOGY,
1579 &cable_tech);
1580 if (status)
1581 goto err_read_i2c_eeprom;
1582
1583 status = hw->phy.ops.read_i2c_eeprom(hw,
1584 IXGBE_SFF_BITRATE_NOMINAL,
1585 &bitrate_nominal);
1586 if (status)
1587 goto err_read_i2c_eeprom;
1588
1589 /* ID Module
1590 * =========
1591 * 0 SFP_DA_CU
1592 * 1 SFP_SR
1593 * 2 SFP_LR
1594 * 3 SFP_DA_CORE0 - 82599-specific
1595 * 4 SFP_DA_CORE1 - 82599-specific
1596 * 5 SFP_SR/LR_CORE0 - 82599-specific
1597 * 6 SFP_SR/LR_CORE1 - 82599-specific
1598 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1599 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1600 * 9 SFP_1g_cu_CORE0 - 82599-specific
1601 * 10 SFP_1g_cu_CORE1 - 82599-specific
1602 * 11 SFP_1g_sx_CORE0 - 82599-specific
1603 * 12 SFP_1g_sx_CORE1 - 82599-specific
1604 */
1605 if (hw->mac.type == ixgbe_mac_82598EB) {
1606 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1607 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1608 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1609 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1610 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1611 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1612 else
1613 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1614 } else {
1615 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1616 if (hw->bus.lan_id == 0)
1617 hw->phy.sfp_type =
1618 ixgbe_sfp_type_da_cu_core0;
1619 else
1620 hw->phy.sfp_type =
1621 ixgbe_sfp_type_da_cu_core1;
1622 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1623 hw->phy.ops.read_i2c_eeprom(
1624 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1625 &cable_spec);
1626 if (cable_spec &
1627 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1628 if (hw->bus.lan_id == 0)
1629 hw->phy.sfp_type =
1630 ixgbe_sfp_type_da_act_lmt_core0;
1631 else
1632 hw->phy.sfp_type =
1633 ixgbe_sfp_type_da_act_lmt_core1;
1634 } else {
1635 hw->phy.sfp_type =
1636 ixgbe_sfp_type_unknown;
1637 }
1638 } else if (comp_codes_10g &
1639 (IXGBE_SFF_10GBASESR_CAPABLE |
1640 IXGBE_SFF_10GBASELR_CAPABLE)) {
1641 if (hw->bus.lan_id == 0)
1642 hw->phy.sfp_type =
1643 ixgbe_sfp_type_srlr_core0;
1644 else
1645 hw->phy.sfp_type =
1646 ixgbe_sfp_type_srlr_core1;
1647 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1648 if (hw->bus.lan_id == 0)
1649 hw->phy.sfp_type =
1650 ixgbe_sfp_type_1g_cu_core0;
1651 else
1652 hw->phy.sfp_type =
1653 ixgbe_sfp_type_1g_cu_core1;
1654 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1655 if (hw->bus.lan_id == 0)
1656 hw->phy.sfp_type =
1657 ixgbe_sfp_type_1g_sx_core0;
1658 else
1659 hw->phy.sfp_type =
1660 ixgbe_sfp_type_1g_sx_core1;
1661 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1662 if (hw->bus.lan_id == 0)
1663 hw->phy.sfp_type =
1664 ixgbe_sfp_type_1g_lx_core0;
1665 else
1666 hw->phy.sfp_type =
1667 ixgbe_sfp_type_1g_lx_core1;
1668 /* Support only Ethernet 1000BASE-BX10, checking the Bit Rate
1669 * Nominal Value as per SFF-8472 by convention 1.25 Gb/s should
1670 * be rounded up to 0Dh (13 in units of 100 MBd) for 1000BASE-BX
1671 */
1672 } else if ((comp_codes_1g & IXGBE_SFF_BASEBX10_CAPABLE) &&
1673 (bitrate_nominal == 0xD)) {
1674 if (hw->bus.lan_id == 0)
1675 hw->phy.sfp_type =
1676 ixgbe_sfp_type_1g_bx_core0;
1677 else
1678 hw->phy.sfp_type =
1679 ixgbe_sfp_type_1g_bx_core1;
1680 } else {
1681 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1682 }
1683 }
1684
1685 if (hw->phy.sfp_type != stored_sfp_type)
1686 hw->phy.sfp_setup_needed = true;
1687
1688 /* Determine if the SFP+ PHY is dual speed or not. */
1689 hw->phy.multispeed_fiber = false;
1690 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1691 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1692 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1693 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1694 hw->phy.multispeed_fiber = true;
1695
1696 /* Determine PHY vendor */
1697 if (hw->phy.type != ixgbe_phy_nl) {
1698 hw->phy.id = identifier;
1699 status = hw->phy.ops.read_i2c_eeprom(hw,
1700 IXGBE_SFF_VENDOR_OUI_BYTE0,
1701 &oui_bytes[0]);
1702
1703 if (status != 0)
1704 goto err_read_i2c_eeprom;
1705
1706 status = hw->phy.ops.read_i2c_eeprom(hw,
1707 IXGBE_SFF_VENDOR_OUI_BYTE1,
1708 &oui_bytes[1]);
1709
1710 if (status != 0)
1711 goto err_read_i2c_eeprom;
1712
1713 status = hw->phy.ops.read_i2c_eeprom(hw,
1714 IXGBE_SFF_VENDOR_OUI_BYTE2,
1715 &oui_bytes[2]);
1716
1717 if (status != 0)
1718 goto err_read_i2c_eeprom;
1719
1720 vendor_oui =
1721 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1722 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1723 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1724
1725 switch (vendor_oui) {
1726 case IXGBE_SFF_VENDOR_OUI_TYCO:
1727 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1728 hw->phy.type =
1729 ixgbe_phy_sfp_passive_tyco;
1730 break;
1731 case IXGBE_SFF_VENDOR_OUI_FTL:
1732 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1733 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1734 else
1735 hw->phy.type = ixgbe_phy_sfp_ftl;
1736 break;
1737 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1738 hw->phy.type = ixgbe_phy_sfp_avago;
1739 break;
1740 case IXGBE_SFF_VENDOR_OUI_INTEL:
1741 hw->phy.type = ixgbe_phy_sfp_intel;
1742 break;
1743 default:
1744 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1745 hw->phy.type =
1746 ixgbe_phy_sfp_passive_unknown;
1747 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1748 hw->phy.type =
1749 ixgbe_phy_sfp_active_unknown;
1750 else
1751 hw->phy.type = ixgbe_phy_sfp_unknown;
1752 break;
1753 }
1754 }
1755
1756 /* Allow any DA cable vendor */
1757 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1758 IXGBE_SFF_DA_ACTIVE_CABLE))
1759 return 0;
1760
1761 /* Verify supported 1G SFP modules */
1762 if (comp_codes_10g == 0 &&
1763 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1764 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1767 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1768 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1769 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1770 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1771 hw->phy.type = ixgbe_phy_sfp_unsupported;
1772 return -EOPNOTSUPP;
1773 }
1774
1775 /* Anything else 82598-based is supported */
1776 if (hw->mac.type == ixgbe_mac_82598EB)
1777 return 0;
1778
1779 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1780 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1781 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1782 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1783 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1784 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1785 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1786 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
1787 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core0 ||
1788 hw->phy.sfp_type == ixgbe_sfp_type_1g_bx_core1)) {
1789 /* Make sure we're a supported PHY type */
1790 if (hw->phy.type == ixgbe_phy_sfp_intel)
1791 return 0;
1792 if (hw->allow_unsupported_sfp) {
1793 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1794 return 0;
1795 }
1796 hw_dbg(hw, "SFP+ module not supported\n");
1797 hw->phy.type = ixgbe_phy_sfp_unsupported;
1798 return -EOPNOTSUPP;
1799 }
1800 return 0;
1801
1802err_read_i2c_eeprom:
1803 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1804 if (hw->phy.type != ixgbe_phy_nl) {
1805 hw->phy.id = 0;
1806 hw->phy.type = ixgbe_phy_unknown;
1807 }
1808 return -ENOENT;
1809}
1810
1811/**
1812 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1813 * @hw: pointer to hardware structure
1814 *
1815 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1816 **/
1817static int ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1818{
1819 struct ixgbe_adapter *adapter = hw->back;
1820 int status;
1821 u32 vendor_oui = 0;
1822 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1823 u8 identifier = 0;
1824 u8 comp_codes_1g = 0;
1825 u8 comp_codes_10g = 0;
1826 u8 oui_bytes[3] = {0, 0, 0};
1827 u16 enforce_sfp = 0;
1828 u8 connector = 0;
1829 u8 cable_length = 0;
1830 u8 device_tech = 0;
1831 bool active_cable = false;
1832
1833 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1834 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1835 return -ENOENT;
1836 }
1837
1838 /* LAN ID is needed for sfp_type determination */
1839 hw->mac.ops.set_lan_id(hw);
1840
1841 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1842 &identifier);
1843
1844 if (status != 0)
1845 goto err_read_i2c_eeprom;
1846
1847 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1848 hw->phy.type = ixgbe_phy_sfp_unsupported;
1849 return -EOPNOTSUPP;
1850 }
1851
1852 hw->phy.id = identifier;
1853
1854 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1855 &comp_codes_10g);
1856
1857 if (status != 0)
1858 goto err_read_i2c_eeprom;
1859
1860 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1861 &comp_codes_1g);
1862
1863 if (status != 0)
1864 goto err_read_i2c_eeprom;
1865
1866 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1867 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1868 if (hw->bus.lan_id == 0)
1869 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1870 else
1871 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1872 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1873 IXGBE_SFF_10GBASELR_CAPABLE)) {
1874 if (hw->bus.lan_id == 0)
1875 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1876 else
1877 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1878 } else {
1879 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1880 active_cable = true;
1881
1882 if (!active_cable) {
1883 /* check for active DA cables that pre-date
1884 * SFF-8436 v3.6
1885 */
1886 hw->phy.ops.read_i2c_eeprom(hw,
1887 IXGBE_SFF_QSFP_CONNECTOR,
1888 &connector);
1889
1890 hw->phy.ops.read_i2c_eeprom(hw,
1891 IXGBE_SFF_QSFP_CABLE_LENGTH,
1892 &cable_length);
1893
1894 hw->phy.ops.read_i2c_eeprom(hw,
1895 IXGBE_SFF_QSFP_DEVICE_TECH,
1896 &device_tech);
1897
1898 if ((connector ==
1899 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1900 (cable_length > 0) &&
1901 ((device_tech >> 4) ==
1902 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1903 active_cable = true;
1904 }
1905
1906 if (active_cable) {
1907 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1908 if (hw->bus.lan_id == 0)
1909 hw->phy.sfp_type =
1910 ixgbe_sfp_type_da_act_lmt_core0;
1911 else
1912 hw->phy.sfp_type =
1913 ixgbe_sfp_type_da_act_lmt_core1;
1914 } else {
1915 /* unsupported module type */
1916 hw->phy.type = ixgbe_phy_sfp_unsupported;
1917 return -EOPNOTSUPP;
1918 }
1919 }
1920
1921 if (hw->phy.sfp_type != stored_sfp_type)
1922 hw->phy.sfp_setup_needed = true;
1923
1924 /* Determine if the QSFP+ PHY is dual speed or not. */
1925 hw->phy.multispeed_fiber = false;
1926 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1927 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1928 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1929 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1930 hw->phy.multispeed_fiber = true;
1931
1932 /* Determine PHY vendor for optical modules */
1933 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1934 IXGBE_SFF_10GBASELR_CAPABLE)) {
1935 status = hw->phy.ops.read_i2c_eeprom(hw,
1936 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1937 &oui_bytes[0]);
1938
1939 if (status != 0)
1940 goto err_read_i2c_eeprom;
1941
1942 status = hw->phy.ops.read_i2c_eeprom(hw,
1943 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1944 &oui_bytes[1]);
1945
1946 if (status != 0)
1947 goto err_read_i2c_eeprom;
1948
1949 status = hw->phy.ops.read_i2c_eeprom(hw,
1950 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1951 &oui_bytes[2]);
1952
1953 if (status != 0)
1954 goto err_read_i2c_eeprom;
1955
1956 vendor_oui =
1957 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1958 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1959 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1960
1961 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1962 hw->phy.type = ixgbe_phy_qsfp_intel;
1963 else
1964 hw->phy.type = ixgbe_phy_qsfp_unknown;
1965
1966 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1967 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1968 /* Make sure we're a supported PHY type */
1969 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1970 return 0;
1971 if (hw->allow_unsupported_sfp) {
1972 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1973 return 0;
1974 }
1975 hw_dbg(hw, "QSFP module not supported\n");
1976 hw->phy.type = ixgbe_phy_sfp_unsupported;
1977 return -EOPNOTSUPP;
1978 }
1979 return 0;
1980 }
1981 return 0;
1982
1983err_read_i2c_eeprom:
1984 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1985 hw->phy.id = 0;
1986 hw->phy.type = ixgbe_phy_unknown;
1987
1988 return -ENOENT;
1989}
1990
1991/**
1992 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1993 * @hw: pointer to hardware structure
1994 * @list_offset: offset to the SFP ID list
1995 * @data_offset: offset to the SFP data block
1996 *
1997 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1998 * so it returns the offsets to the phy init sequence block.
1999 **/
2000int ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
2001 u16 *list_offset,
2002 u16 *data_offset)
2003{
2004 u16 sfp_id;
2005 u16 sfp_type = hw->phy.sfp_type;
2006
2007 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
2008 return -EOPNOTSUPP;
2009
2010 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2011 return -ENOENT;
2012
2013 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
2014 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
2015 return -EOPNOTSUPP;
2016
2017 /*
2018 * Limiting active cables and 1G Phys must be initialized as
2019 * SR modules
2020 */
2021 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
2022 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2023 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
2024 sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2025 sfp_type == ixgbe_sfp_type_1g_bx_core0)
2026 sfp_type = ixgbe_sfp_type_srlr_core0;
2027 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
2028 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
2029 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
2030 sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2031 sfp_type == ixgbe_sfp_type_1g_bx_core1)
2032 sfp_type = ixgbe_sfp_type_srlr_core1;
2033
2034 /* Read offset to PHY init contents */
2035 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2036 hw_err(hw, "eeprom read at %d failed\n",
2037 IXGBE_PHY_INIT_OFFSET_NL);
2038 return -EIO;
2039 }
2040
2041 if ((!*list_offset) || (*list_offset == 0xFFFF))
2042 return -EIO;
2043
2044 /* Shift offset to first ID word */
2045 (*list_offset)++;
2046
2047 /*
2048 * Find the matching SFP ID in the EEPROM
2049 * and program the init sequence
2050 */
2051 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2052 goto err_phy;
2053
2054 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
2055 if (sfp_id == sfp_type) {
2056 (*list_offset)++;
2057 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2058 goto err_phy;
2059 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
2060 hw_dbg(hw, "SFP+ module not supported\n");
2061 return -EOPNOTSUPP;
2062 } else {
2063 break;
2064 }
2065 } else {
2066 (*list_offset) += 2;
2067 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2068 goto err_phy;
2069 }
2070 }
2071
2072 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
2073 hw_dbg(hw, "No matching SFP+ module found\n");
2074 return -EOPNOTSUPP;
2075 }
2076
2077 return 0;
2078
2079err_phy:
2080 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2081 return -EIO;
2082}
2083
2084/**
2085 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2086 * @hw: pointer to hardware structure
2087 * @byte_offset: EEPROM byte offset to read
2088 * @eeprom_data: value read
2089 *
2090 * Performs byte read operation to SFP module's EEPROM over I2C interface.
2091 **/
2092int ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2093 u8 *eeprom_data)
2094{
2095 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2096 IXGBE_I2C_EEPROM_DEV_ADDR,
2097 eeprom_data);
2098}
2099
2100/**
2101 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2102 * @hw: pointer to hardware structure
2103 * @byte_offset: byte offset at address 0xA2
2104 * @sff8472_data: value read
2105 *
2106 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2107 **/
2108int ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2109 u8 *sff8472_data)
2110{
2111 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2112 IXGBE_I2C_EEPROM_DEV_ADDR2,
2113 sff8472_data);
2114}
2115
2116/**
2117 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2118 * @hw: pointer to hardware structure
2119 * @byte_offset: EEPROM byte offset to write
2120 * @eeprom_data: value to write
2121 *
2122 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2123 **/
2124int ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2125 u8 eeprom_data)
2126{
2127 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2128 IXGBE_I2C_EEPROM_DEV_ADDR,
2129 eeprom_data);
2130}
2131
2132/**
2133 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2134 * @hw: pointer to hardware structure
2135 * @offset: eeprom offset to be read
2136 * @addr: I2C address to be read
2137 */
2138static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2139{
2140 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2141 offset == IXGBE_SFF_IDENTIFIER &&
2142 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2143 return true;
2144 return false;
2145}
2146
2147/**
2148 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2149 * @hw: pointer to hardware structure
2150 * @byte_offset: byte offset to read
2151 * @dev_addr: device address
2152 * @data: value read
2153 * @lock: true if to take and release semaphore
2154 *
2155 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2156 * a specified device address.
2157 */
2158static int ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2159 u8 dev_addr, u8 *data, bool lock)
2160{
2161 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2162 u32 max_retry = 10;
2163 bool nack = true;
2164 u32 retry = 0;
2165 int status;
2166
2167 if (hw->mac.type >= ixgbe_mac_X550)
2168 max_retry = 3;
2169 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2170 max_retry = IXGBE_SFP_DETECT_RETRIES;
2171
2172 *data = 0;
2173
2174 do {
2175 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2176 return -EBUSY;
2177
2178 ixgbe_i2c_start(hw);
2179
2180 /* Device Address and write indication */
2181 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2182 if (status != 0)
2183 goto fail;
2184
2185 status = ixgbe_get_i2c_ack(hw);
2186 if (status != 0)
2187 goto fail;
2188
2189 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2190 if (status != 0)
2191 goto fail;
2192
2193 status = ixgbe_get_i2c_ack(hw);
2194 if (status != 0)
2195 goto fail;
2196
2197 ixgbe_i2c_start(hw);
2198
2199 /* Device Address and read indication */
2200 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2201 if (status != 0)
2202 goto fail;
2203
2204 status = ixgbe_get_i2c_ack(hw);
2205 if (status != 0)
2206 goto fail;
2207
2208 status = ixgbe_clock_in_i2c_byte(hw, data);
2209 if (status != 0)
2210 goto fail;
2211
2212 status = ixgbe_clock_out_i2c_bit(hw, nack);
2213 if (status != 0)
2214 goto fail;
2215
2216 ixgbe_i2c_stop(hw);
2217 if (lock)
2218 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2219 return 0;
2220
2221fail:
2222 ixgbe_i2c_bus_clear(hw);
2223 if (lock) {
2224 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2225 msleep(100);
2226 }
2227 retry++;
2228 if (retry < max_retry)
2229 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2230 else
2231 hw_dbg(hw, "I2C byte read error.\n");
2232
2233 } while (retry < max_retry);
2234
2235 return status;
2236}
2237
2238/**
2239 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2240 * @hw: pointer to hardware structure
2241 * @byte_offset: byte offset to read
2242 * @dev_addr: device address
2243 * @data: value read
2244 *
2245 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2246 * a specified device address.
2247 */
2248int ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2249 u8 dev_addr, u8 *data)
2250{
2251 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2252 data, true);
2253}
2254
2255/**
2256 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2257 * @hw: pointer to hardware structure
2258 * @byte_offset: byte offset to read
2259 * @dev_addr: device address
2260 * @data: value read
2261 *
2262 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2263 * a specified device address.
2264 */
2265int ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2266 u8 dev_addr, u8 *data)
2267{
2268 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2269 data, false);
2270}
2271
2272/**
2273 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2274 * @hw: pointer to hardware structure
2275 * @byte_offset: byte offset to write
2276 * @dev_addr: device address
2277 * @data: value to write
2278 * @lock: true if to take and release semaphore
2279 *
2280 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2281 * a specified device address.
2282 */
2283static int ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2284 u8 dev_addr, u8 data, bool lock)
2285{
2286 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2287 u32 max_retry = 1;
2288 u32 retry = 0;
2289 int status;
2290
2291 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2292 return -EBUSY;
2293
2294 do {
2295 ixgbe_i2c_start(hw);
2296
2297 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2298 if (status != 0)
2299 goto fail;
2300
2301 status = ixgbe_get_i2c_ack(hw);
2302 if (status != 0)
2303 goto fail;
2304
2305 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2306 if (status != 0)
2307 goto fail;
2308
2309 status = ixgbe_get_i2c_ack(hw);
2310 if (status != 0)
2311 goto fail;
2312
2313 status = ixgbe_clock_out_i2c_byte(hw, data);
2314 if (status != 0)
2315 goto fail;
2316
2317 status = ixgbe_get_i2c_ack(hw);
2318 if (status != 0)
2319 goto fail;
2320
2321 ixgbe_i2c_stop(hw);
2322 if (lock)
2323 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2324 return 0;
2325
2326fail:
2327 ixgbe_i2c_bus_clear(hw);
2328 retry++;
2329 if (retry < max_retry)
2330 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2331 else
2332 hw_dbg(hw, "I2C byte write error.\n");
2333 } while (retry < max_retry);
2334
2335 if (lock)
2336 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2337
2338 return status;
2339}
2340
2341/**
2342 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2343 * @hw: pointer to hardware structure
2344 * @byte_offset: byte offset to write
2345 * @dev_addr: device address
2346 * @data: value to write
2347 *
2348 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2349 * a specified device address.
2350 */
2351int ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2352 u8 dev_addr, u8 data)
2353{
2354 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2355 data, true);
2356}
2357
2358/**
2359 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2360 * @hw: pointer to hardware structure
2361 * @byte_offset: byte offset to write
2362 * @dev_addr: device address
2363 * @data: value to write
2364 *
2365 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2366 * a specified device address.
2367 */
2368int ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2369 u8 dev_addr, u8 data)
2370{
2371 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2372 data, false);
2373}
2374
2375/**
2376 * ixgbe_i2c_start - Sets I2C start condition
2377 * @hw: pointer to hardware structure
2378 *
2379 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2380 * Set bit-bang mode on X550 hardware.
2381 **/
2382static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2383{
2384 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2385
2386 i2cctl |= IXGBE_I2C_BB_EN(hw);
2387
2388 /* Start condition must begin with data and clock high */
2389 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2390 ixgbe_raise_i2c_clk(hw, &i2cctl);
2391
2392 /* Setup time for start condition (4.7us) */
2393 udelay(IXGBE_I2C_T_SU_STA);
2394
2395 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2396
2397 /* Hold time for start condition (4us) */
2398 udelay(IXGBE_I2C_T_HD_STA);
2399
2400 ixgbe_lower_i2c_clk(hw, &i2cctl);
2401
2402 /* Minimum low period of clock is 4.7 us */
2403 udelay(IXGBE_I2C_T_LOW);
2404
2405}
2406
2407/**
2408 * ixgbe_i2c_stop - Sets I2C stop condition
2409 * @hw: pointer to hardware structure
2410 *
2411 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2412 * Disables bit-bang mode and negates data output enable on X550
2413 * hardware.
2414 **/
2415static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2416{
2417 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2418 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2419 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2420 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2421
2422 /* Stop condition must begin with data low and clock high */
2423 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2424 ixgbe_raise_i2c_clk(hw, &i2cctl);
2425
2426 /* Setup time for stop condition (4us) */
2427 udelay(IXGBE_I2C_T_SU_STO);
2428
2429 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2430
2431 /* bus free time between stop and start (4.7us)*/
2432 udelay(IXGBE_I2C_T_BUF);
2433
2434 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2435 i2cctl &= ~bb_en_bit;
2436 i2cctl |= data_oe_bit | clk_oe_bit;
2437 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2438 IXGBE_WRITE_FLUSH(hw);
2439 }
2440}
2441
2442/**
2443 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2444 * @hw: pointer to hardware structure
2445 * @data: data byte to clock in
2446 *
2447 * Clocks in one byte data via I2C data/clock
2448 **/
2449static int ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2450{
2451 bool bit = false;
2452 int i;
2453
2454 *data = 0;
2455 for (i = 7; i >= 0; i--) {
2456 ixgbe_clock_in_i2c_bit(hw, &bit);
2457 *data |= bit << i;
2458 }
2459
2460 return 0;
2461}
2462
2463/**
2464 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2465 * @hw: pointer to hardware structure
2466 * @data: data byte clocked out
2467 *
2468 * Clocks out one byte data via I2C data/clock
2469 **/
2470static int ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2471{
2472 bool bit = false;
2473 int status;
2474 u32 i2cctl;
2475 int i;
2476
2477 for (i = 7; i >= 0; i--) {
2478 bit = (data >> i) & 0x1;
2479 status = ixgbe_clock_out_i2c_bit(hw, bit);
2480
2481 if (status != 0)
2482 break;
2483 }
2484
2485 /* Release SDA line (set high) */
2486 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2487 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2488 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2490 IXGBE_WRITE_FLUSH(hw);
2491
2492 return status;
2493}
2494
2495/**
2496 * ixgbe_get_i2c_ack - Polls for I2C ACK
2497 * @hw: pointer to hardware structure
2498 *
2499 * Clocks in/out one bit via I2C data/clock
2500 **/
2501static int ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2502{
2503 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2504 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2505 u32 timeout = 10;
2506 bool ack = true;
2507 int status = 0;
2508 u32 i = 0;
2509
2510 if (data_oe_bit) {
2511 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2512 i2cctl |= data_oe_bit;
2513 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2514 IXGBE_WRITE_FLUSH(hw);
2515 }
2516 ixgbe_raise_i2c_clk(hw, &i2cctl);
2517
2518 /* Minimum high period of clock is 4us */
2519 udelay(IXGBE_I2C_T_HIGH);
2520
2521 /* Poll for ACK. Note that ACK in I2C spec is
2522 * transition from 1 to 0 */
2523 for (i = 0; i < timeout; i++) {
2524 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2525 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2526
2527 udelay(1);
2528 if (ack == 0)
2529 break;
2530 }
2531
2532 if (ack == 1) {
2533 hw_dbg(hw, "I2C ack was not received.\n");
2534 status = -EIO;
2535 }
2536
2537 ixgbe_lower_i2c_clk(hw, &i2cctl);
2538
2539 /* Minimum low period of clock is 4.7 us */
2540 udelay(IXGBE_I2C_T_LOW);
2541
2542 return status;
2543}
2544
2545/**
2546 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2547 * @hw: pointer to hardware structure
2548 * @data: read data value
2549 *
2550 * Clocks in one bit via I2C data/clock
2551 **/
2552static int ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2553{
2554 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2555 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2556
2557 if (data_oe_bit) {
2558 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2559 i2cctl |= data_oe_bit;
2560 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2561 IXGBE_WRITE_FLUSH(hw);
2562 }
2563 ixgbe_raise_i2c_clk(hw, &i2cctl);
2564
2565 /* Minimum high period of clock is 4us */
2566 udelay(IXGBE_I2C_T_HIGH);
2567
2568 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2569 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2570
2571 ixgbe_lower_i2c_clk(hw, &i2cctl);
2572
2573 /* Minimum low period of clock is 4.7 us */
2574 udelay(IXGBE_I2C_T_LOW);
2575
2576 return 0;
2577}
2578
2579/**
2580 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2581 * @hw: pointer to hardware structure
2582 * @data: data value to write
2583 *
2584 * Clocks out one bit via I2C data/clock
2585 **/
2586static int ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2587{
2588 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2589 int status;
2590
2591 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2592 if (status == 0) {
2593 ixgbe_raise_i2c_clk(hw, &i2cctl);
2594
2595 /* Minimum high period of clock is 4us */
2596 udelay(IXGBE_I2C_T_HIGH);
2597
2598 ixgbe_lower_i2c_clk(hw, &i2cctl);
2599
2600 /* Minimum low period of clock is 4.7 us.
2601 * This also takes care of the data hold time.
2602 */
2603 udelay(IXGBE_I2C_T_LOW);
2604 } else {
2605 hw_dbg(hw, "I2C data was not set to %X\n", data);
2606 return -EIO;
2607 }
2608
2609 return 0;
2610}
2611/**
2612 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2613 * @hw: pointer to hardware structure
2614 * @i2cctl: Current value of I2CCTL register
2615 *
2616 * Raises the I2C clock line '0'->'1'
2617 * Negates the I2C clock output enable on X550 hardware.
2618 **/
2619static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2620{
2621 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2622 u32 i = 0;
2623 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2624 u32 i2cctl_r = 0;
2625
2626 if (clk_oe_bit) {
2627 *i2cctl |= clk_oe_bit;
2628 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2629 }
2630
2631 for (i = 0; i < timeout; i++) {
2632 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2633 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2634 IXGBE_WRITE_FLUSH(hw);
2635 /* SCL rise time (1000ns) */
2636 udelay(IXGBE_I2C_T_RISE);
2637
2638 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2639 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2640 break;
2641 }
2642}
2643
2644/**
2645 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2646 * @hw: pointer to hardware structure
2647 * @i2cctl: Current value of I2CCTL register
2648 *
2649 * Lowers the I2C clock line '1'->'0'
2650 * Asserts the I2C clock output enable on X550 hardware.
2651 **/
2652static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2653{
2654
2655 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2656 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2657
2658 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2659 IXGBE_WRITE_FLUSH(hw);
2660
2661 /* SCL fall time (300ns) */
2662 udelay(IXGBE_I2C_T_FALL);
2663}
2664
2665/**
2666 * ixgbe_set_i2c_data - Sets the I2C data bit
2667 * @hw: pointer to hardware structure
2668 * @i2cctl: Current value of I2CCTL register
2669 * @data: I2C data value (0 or 1) to set
2670 *
2671 * Sets the I2C data bit
2672 * Asserts the I2C data output enable on X550 hardware.
2673 **/
2674static int ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2675{
2676 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2677
2678 if (data)
2679 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2680 else
2681 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2682 *i2cctl &= ~data_oe_bit;
2683
2684 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2685 IXGBE_WRITE_FLUSH(hw);
2686
2687 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2688 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2689
2690 if (!data) /* Can't verify data in this case */
2691 return 0;
2692 if (data_oe_bit) {
2693 *i2cctl |= data_oe_bit;
2694 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2695 IXGBE_WRITE_FLUSH(hw);
2696 }
2697
2698 /* Verify data was set correctly */
2699 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2700 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2701 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2702 return -EIO;
2703 }
2704
2705 return 0;
2706}
2707
2708/**
2709 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2710 * @hw: pointer to hardware structure
2711 * @i2cctl: Current value of I2CCTL register
2712 *
2713 * Returns the I2C data bit value
2714 * Negates the I2C data output enable on X550 hardware.
2715 **/
2716static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2717{
2718 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2719
2720 if (data_oe_bit) {
2721 *i2cctl |= data_oe_bit;
2722 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2723 IXGBE_WRITE_FLUSH(hw);
2724 udelay(IXGBE_I2C_T_FALL);
2725 }
2726
2727 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2728 return true;
2729 return false;
2730}
2731
2732/**
2733 * ixgbe_i2c_bus_clear - Clears the I2C bus
2734 * @hw: pointer to hardware structure
2735 *
2736 * Clears the I2C bus by sending nine clock pulses.
2737 * Used when data line is stuck low.
2738 **/
2739static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2740{
2741 u32 i2cctl;
2742 u32 i;
2743
2744 ixgbe_i2c_start(hw);
2745 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2746
2747 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2748
2749 for (i = 0; i < 9; i++) {
2750 ixgbe_raise_i2c_clk(hw, &i2cctl);
2751
2752 /* Min high period of clock is 4us */
2753 udelay(IXGBE_I2C_T_HIGH);
2754
2755 ixgbe_lower_i2c_clk(hw, &i2cctl);
2756
2757 /* Min low period of clock is 4.7us*/
2758 udelay(IXGBE_I2C_T_LOW);
2759 }
2760
2761 ixgbe_i2c_start(hw);
2762
2763 /* Put the i2c bus back to default state */
2764 ixgbe_i2c_stop(hw);
2765}
2766
2767/**
2768 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2769 * @hw: pointer to hardware structure
2770 *
2771 * Checks if the LASI temp alarm status was triggered due to overtemp
2772 *
2773 * Return true when an overtemp event detected, otherwise false.
2774 **/
2775bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2776{
2777 u16 phy_data = 0;
2778 u32 status;
2779
2780 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2781 return false;
2782
2783 /* Check that the LASI temp alarm status was triggered */
2784 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2785 MDIO_MMD_PMAPMD, &phy_data);
2786 if (status)
2787 return false;
2788
2789 return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2790}
2791
2792/** ixgbe_set_copper_phy_power - Control power for copper phy
2793 * @hw: pointer to hardware structure
2794 * @on: true for on, false for off
2795 **/
2796int ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2797{
2798 u32 status;
2799 u16 reg;
2800
2801 /* Bail if we don't have copper phy */
2802 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2803 return 0;
2804
2805 if (!on && ixgbe_mng_present(hw))
2806 return 0;
2807
2808 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2809 if (status)
2810 return status;
2811
2812 if (on) {
2813 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2814 } else {
2815 if (ixgbe_check_reset_blocked(hw))
2816 return 0;
2817 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2818 }
2819
2820 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2821 return status;
2822}
1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include <linux/pci.h>
5#include <linux/delay.h>
6#include <linux/iopoll.h>
7#include <linux/sched.h>
8
9#include "ixgbe.h"
10#include "ixgbe_phy.h"
11
12static void ixgbe_i2c_start(struct ixgbe_hw *hw);
13static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
14static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
15static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
16static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
17static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
18static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
19static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
20static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
21static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
22static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
23static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
24static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
25static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
26static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
27
28/**
29 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
30 * @hw: pointer to the hardware structure
31 * @byte: byte to send
32 *
33 * Returns an error code on error.
34 **/
35static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
36{
37 s32 status;
38
39 status = ixgbe_clock_out_i2c_byte(hw, byte);
40 if (status)
41 return status;
42 return ixgbe_get_i2c_ack(hw);
43}
44
45/**
46 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
47 * @hw: pointer to the hardware structure
48 * @byte: pointer to a u8 to receive the byte
49 *
50 * Returns an error code on error.
51 **/
52static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
53{
54 s32 status;
55
56 status = ixgbe_clock_in_i2c_byte(hw, byte);
57 if (status)
58 return status;
59 /* ACK */
60 return ixgbe_clock_out_i2c_bit(hw, false);
61}
62
63/**
64 * ixgbe_ones_comp_byte_add - Perform one's complement addition
65 * @add1: addend 1
66 * @add2: addend 2
67 *
68 * Returns one's complement 8-bit sum.
69 **/
70static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
71{
72 u16 sum = add1 + add2;
73
74 sum = (sum & 0xFF) + (sum >> 8);
75 return sum & 0xFF;
76}
77
78/**
79 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
80 * @hw: pointer to the hardware structure
81 * @addr: I2C bus address to read from
82 * @reg: I2C device register to read from
83 * @val: pointer to location to receive read value
84 * @lock: true if to take and release semaphore
85 *
86 * Returns an error code on error.
87 */
88s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
89 u16 reg, u16 *val, bool lock)
90{
91 u32 swfw_mask = hw->phy.phy_semaphore_mask;
92 int max_retry = 3;
93 int retry = 0;
94 u8 csum_byte;
95 u8 high_bits;
96 u8 low_bits;
97 u8 reg_high;
98 u8 csum;
99
100 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
101 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
102 csum = ~csum;
103 do {
104 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
105 return -EBUSY;
106 ixgbe_i2c_start(hw);
107 /* Device Address and write indication */
108 if (ixgbe_out_i2c_byte_ack(hw, addr))
109 goto fail;
110 /* Write bits 14:8 */
111 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
112 goto fail;
113 /* Write bits 7:0 */
114 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
115 goto fail;
116 /* Write csum */
117 if (ixgbe_out_i2c_byte_ack(hw, csum))
118 goto fail;
119 /* Re-start condition */
120 ixgbe_i2c_start(hw);
121 /* Device Address and read indication */
122 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
123 goto fail;
124 /* Get upper bits */
125 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
126 goto fail;
127 /* Get low bits */
128 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
129 goto fail;
130 /* Get csum */
131 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
132 goto fail;
133 /* NACK */
134 if (ixgbe_clock_out_i2c_bit(hw, false))
135 goto fail;
136 ixgbe_i2c_stop(hw);
137 if (lock)
138 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
139 *val = (high_bits << 8) | low_bits;
140 return 0;
141
142fail:
143 ixgbe_i2c_bus_clear(hw);
144 if (lock)
145 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
146 retry++;
147 if (retry < max_retry)
148 hw_dbg(hw, "I2C byte read combined error - Retry.\n");
149 else
150 hw_dbg(hw, "I2C byte read combined error.\n");
151 } while (retry < max_retry);
152
153 return -EIO;
154}
155
156/**
157 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
158 * @hw: pointer to the hardware structure
159 * @addr: I2C bus address to write to
160 * @reg: I2C device register to write to
161 * @val: value to write
162 * @lock: true if to take and release semaphore
163 *
164 * Returns an error code on error.
165 */
166s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr,
167 u16 reg, u16 val, bool lock)
168{
169 u32 swfw_mask = hw->phy.phy_semaphore_mask;
170 int max_retry = 1;
171 int retry = 0;
172 u8 reg_high;
173 u8 csum;
174
175 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
176 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
177 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
178 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
179 csum = ~csum;
180 do {
181 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
182 return -EBUSY;
183 ixgbe_i2c_start(hw);
184 /* Device Address and write indication */
185 if (ixgbe_out_i2c_byte_ack(hw, addr))
186 goto fail;
187 /* Write bits 14:8 */
188 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
189 goto fail;
190 /* Write bits 7:0 */
191 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
192 goto fail;
193 /* Write data 15:8 */
194 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
195 goto fail;
196 /* Write data 7:0 */
197 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
198 goto fail;
199 /* Write csum */
200 if (ixgbe_out_i2c_byte_ack(hw, csum))
201 goto fail;
202 ixgbe_i2c_stop(hw);
203 if (lock)
204 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
205 return 0;
206
207fail:
208 ixgbe_i2c_bus_clear(hw);
209 if (lock)
210 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
211 retry++;
212 if (retry < max_retry)
213 hw_dbg(hw, "I2C byte write combined error - Retry.\n");
214 else
215 hw_dbg(hw, "I2C byte write combined error.\n");
216 } while (retry < max_retry);
217
218 return -EIO;
219}
220
221/**
222 * ixgbe_probe_phy - Probe a single address for a PHY
223 * @hw: pointer to hardware structure
224 * @phy_addr: PHY address to probe
225 *
226 * Returns true if PHY found
227 **/
228static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
229{
230 u16 ext_ability = 0;
231
232 hw->phy.mdio.prtad = phy_addr;
233 if (mdio45_probe(&hw->phy.mdio, phy_addr) != 0)
234 return false;
235
236 if (ixgbe_get_phy_id(hw))
237 return false;
238
239 hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
240
241 if (hw->phy.type == ixgbe_phy_unknown) {
242 hw->phy.ops.read_reg(hw,
243 MDIO_PMA_EXTABLE,
244 MDIO_MMD_PMAPMD,
245 &ext_ability);
246 if (ext_ability &
247 (MDIO_PMA_EXTABLE_10GBT |
248 MDIO_PMA_EXTABLE_1000BT))
249 hw->phy.type = ixgbe_phy_cu_unknown;
250 else
251 hw->phy.type = ixgbe_phy_generic;
252 }
253
254 return true;
255}
256
257/**
258 * ixgbe_identify_phy_generic - Get physical layer module
259 * @hw: pointer to hardware structure
260 *
261 * Determines the physical layer module found on the current adapter.
262 **/
263s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
264{
265 u32 status = -EFAULT;
266 u32 phy_addr;
267
268 if (!hw->phy.phy_semaphore_mask) {
269 if (hw->bus.lan_id)
270 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
271 else
272 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
273 }
274
275 if (hw->phy.type != ixgbe_phy_unknown)
276 return 0;
277
278 if (hw->phy.nw_mng_if_sel) {
279 phy_addr = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
280 hw->phy.nw_mng_if_sel);
281 if (ixgbe_probe_phy(hw, phy_addr))
282 return 0;
283 else
284 return -EFAULT;
285 }
286
287 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
288 if (ixgbe_probe_phy(hw, phy_addr)) {
289 status = 0;
290 break;
291 }
292 }
293
294 /* Certain media types do not have a phy so an address will not
295 * be found and the code will take this path. Caller has to
296 * decide if it is an error or not.
297 */
298 if (status)
299 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
300
301 return status;
302}
303
304/**
305 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
306 * @hw: pointer to the hardware structure
307 *
308 * This function checks the MMNGC.MNG_VETO bit to see if there are
309 * any constraints on link from manageability. For MAC's that don't
310 * have this bit just return false since the link can not be blocked
311 * via this method.
312 **/
313bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
314{
315 u32 mmngc;
316
317 /* If we don't have this bit, it can't be blocking */
318 if (hw->mac.type == ixgbe_mac_82598EB)
319 return false;
320
321 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
322 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
323 hw_dbg(hw, "MNG_VETO bit detected.\n");
324 return true;
325 }
326
327 return false;
328}
329
330/**
331 * ixgbe_get_phy_id - Get the phy type
332 * @hw: pointer to hardware structure
333 *
334 **/
335static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
336{
337 s32 status;
338 u16 phy_id_high = 0;
339 u16 phy_id_low = 0;
340
341 status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD,
342 &phy_id_high);
343
344 if (!status) {
345 hw->phy.id = (u32)(phy_id_high << 16);
346 status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD,
347 &phy_id_low);
348 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
349 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
350 }
351 return status;
352}
353
354/**
355 * ixgbe_get_phy_type_from_id - Get the phy type
356 * @phy_id: hardware phy id
357 *
358 **/
359static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
360{
361 enum ixgbe_phy_type phy_type;
362
363 switch (phy_id) {
364 case TN1010_PHY_ID:
365 phy_type = ixgbe_phy_tn;
366 break;
367 case X550_PHY_ID2:
368 case X550_PHY_ID3:
369 case X540_PHY_ID:
370 phy_type = ixgbe_phy_aq;
371 break;
372 case QT2022_PHY_ID:
373 phy_type = ixgbe_phy_qt;
374 break;
375 case ATH_PHY_ID:
376 phy_type = ixgbe_phy_nl;
377 break;
378 case X557_PHY_ID:
379 case X557_PHY_ID2:
380 phy_type = ixgbe_phy_x550em_ext_t;
381 break;
382 case BCM54616S_E_PHY_ID:
383 phy_type = ixgbe_phy_ext_1g_t;
384 break;
385 default:
386 phy_type = ixgbe_phy_unknown;
387 break;
388 }
389
390 return phy_type;
391}
392
393/**
394 * ixgbe_reset_phy_generic - Performs a PHY reset
395 * @hw: pointer to hardware structure
396 **/
397s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
398{
399 u32 i;
400 u16 ctrl = 0;
401 s32 status = 0;
402
403 if (hw->phy.type == ixgbe_phy_unknown)
404 status = ixgbe_identify_phy_generic(hw);
405
406 if (status != 0 || hw->phy.type == ixgbe_phy_none)
407 return status;
408
409 /* Don't reset PHY if it's shut down due to overtemp. */
410 if (!hw->phy.reset_if_overtemp && hw->phy.ops.check_overtemp(hw))
411 return 0;
412
413 /* Blocked by MNG FW so bail */
414 if (ixgbe_check_reset_blocked(hw))
415 return 0;
416
417 /*
418 * Perform soft PHY reset to the PHY_XS.
419 * This will cause a soft reset to the PHY
420 */
421 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
422 MDIO_MMD_PHYXS,
423 MDIO_CTRL1_RESET);
424
425 /*
426 * Poll for reset bit to self-clear indicating reset is complete.
427 * Some PHYs could take up to 3 seconds to complete and need about
428 * 1.7 usec delay after the reset is complete.
429 */
430 for (i = 0; i < 30; i++) {
431 msleep(100);
432 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
433 status = hw->phy.ops.read_reg(hw,
434 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
435 MDIO_MMD_PMAPMD, &ctrl);
436 if (status)
437 return status;
438
439 if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
440 udelay(2);
441 break;
442 }
443 } else {
444 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1,
445 MDIO_MMD_PHYXS, &ctrl);
446 if (status)
447 return status;
448
449 if (!(ctrl & MDIO_CTRL1_RESET)) {
450 udelay(2);
451 break;
452 }
453 }
454 }
455
456 if (ctrl & MDIO_CTRL1_RESET) {
457 hw_dbg(hw, "PHY reset polling failed to complete.\n");
458 return -EIO;
459 }
460
461 return 0;
462}
463
464/**
465 * ixgbe_read_phy_reg_mdi - read PHY register
466 * @hw: pointer to hardware structure
467 * @reg_addr: 32 bit address of PHY register to read
468 * @device_type: 5 bit device type
469 * @phy_data: Pointer to read data from PHY register
470 *
471 * Reads a value from a specified PHY register without the SWFW lock
472 **/
473s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
474 u16 *phy_data)
475{
476 u32 i, data, command;
477
478 /* Setup and write the address cycle command */
479 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
480 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
481 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
482 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
483
484 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
485
486 /* Check every 10 usec to see if the address cycle completed.
487 * The MDI Command bit will clear when the operation is
488 * complete
489 */
490 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
491 udelay(10);
492
493 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
494 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
495 break;
496 }
497
498
499 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
500 hw_dbg(hw, "PHY address command did not complete.\n");
501 return -EIO;
502 }
503
504 /* Address cycle complete, setup and write the read
505 * command
506 */
507 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
508 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
509 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
510 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
511
512 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
513
514 /* Check every 10 usec to see if the address cycle
515 * completed. The MDI Command bit will clear when the
516 * operation is complete
517 */
518 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
519 udelay(10);
520
521 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
522 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
523 break;
524 }
525
526 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
527 hw_dbg(hw, "PHY read command didn't complete\n");
528 return -EIO;
529 }
530
531 /* Read operation is complete. Get the data
532 * from MSRWD
533 */
534 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
535 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
536 *phy_data = (u16)(data);
537
538 return 0;
539}
540
541/**
542 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
543 * using the SWFW lock - this function is needed in most cases
544 * @hw: pointer to hardware structure
545 * @reg_addr: 32 bit address of PHY register to read
546 * @device_type: 5 bit device type
547 * @phy_data: Pointer to read data from PHY register
548 **/
549s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
550 u32 device_type, u16 *phy_data)
551{
552 s32 status;
553 u32 gssr = hw->phy.phy_semaphore_mask;
554
555 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
556 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
557 phy_data);
558 hw->mac.ops.release_swfw_sync(hw, gssr);
559 } else {
560 return -EBUSY;
561 }
562
563 return status;
564}
565
566/**
567 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
568 * without SWFW lock
569 * @hw: pointer to hardware structure
570 * @reg_addr: 32 bit PHY register to write
571 * @device_type: 5 bit device type
572 * @phy_data: Data to write to the PHY register
573 **/
574s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
575 u32 device_type, u16 phy_data)
576{
577 u32 i, command;
578
579 /* Put the data in the MDI single read and write data register*/
580 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
581
582 /* Setup and write the address cycle command */
583 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
584 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
585 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
586 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
587
588 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
589
590 /*
591 * Check every 10 usec to see if the address cycle completed.
592 * The MDI Command bit will clear when the operation is
593 * complete
594 */
595 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
596 udelay(10);
597
598 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
599 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
600 break;
601 }
602
603 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
604 hw_dbg(hw, "PHY address cmd didn't complete\n");
605 return -EIO;
606 }
607
608 /*
609 * Address cycle complete, setup and write the write
610 * command
611 */
612 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
613 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
614 (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
615 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
616
617 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
618
619 /* Check every 10 usec to see if the address cycle
620 * completed. The MDI Command bit will clear when the
621 * operation is complete
622 */
623 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
624 udelay(10);
625
626 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
627 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
628 break;
629 }
630
631 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
632 hw_dbg(hw, "PHY write cmd didn't complete\n");
633 return -EIO;
634 }
635
636 return 0;
637}
638
639/**
640 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
641 * using SWFW lock- this function is needed in most cases
642 * @hw: pointer to hardware structure
643 * @reg_addr: 32 bit PHY register to write
644 * @device_type: 5 bit device type
645 * @phy_data: Data to write to the PHY register
646 **/
647s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
648 u32 device_type, u16 phy_data)
649{
650 s32 status;
651 u32 gssr = hw->phy.phy_semaphore_mask;
652
653 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
654 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
655 phy_data);
656 hw->mac.ops.release_swfw_sync(hw, gssr);
657 } else {
658 return -EBUSY;
659 }
660
661 return status;
662}
663
664#define IXGBE_HW_READ_REG(addr) IXGBE_READ_REG(hw, addr)
665
666/**
667 * ixgbe_msca_cmd - Write the command register and poll for completion/timeout
668 * @hw: pointer to hardware structure
669 * @cmd: command register value to write
670 **/
671static s32 ixgbe_msca_cmd(struct ixgbe_hw *hw, u32 cmd)
672{
673 IXGBE_WRITE_REG(hw, IXGBE_MSCA, cmd);
674
675 return readx_poll_timeout(IXGBE_HW_READ_REG, IXGBE_MSCA, cmd,
676 !(cmd & IXGBE_MSCA_MDI_COMMAND), 10,
677 10 * IXGBE_MDIO_COMMAND_TIMEOUT);
678}
679
680/**
681 * ixgbe_mii_bus_read_generic_c22 - Read a clause 22 register with gssr flags
682 * @hw: pointer to hardware structure
683 * @addr: address
684 * @regnum: register number
685 * @gssr: semaphore flags to acquire
686 **/
687static s32 ixgbe_mii_bus_read_generic_c22(struct ixgbe_hw *hw, int addr,
688 int regnum, u32 gssr)
689{
690 u32 hwaddr, cmd;
691 s32 data;
692
693 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
694 return -EBUSY;
695
696 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
697 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
698 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL |
699 IXGBE_MSCA_READ_AUTOINC | IXGBE_MSCA_MDI_COMMAND;
700
701 data = ixgbe_msca_cmd(hw, cmd);
702 if (data < 0)
703 goto mii_bus_read_done;
704
705 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
706 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
707
708mii_bus_read_done:
709 hw->mac.ops.release_swfw_sync(hw, gssr);
710 return data;
711}
712
713/**
714 * ixgbe_mii_bus_read_generic_c45 - Read a clause 45 register with gssr flags
715 * @hw: pointer to hardware structure
716 * @addr: address
717 * @devad: device address to read
718 * @regnum: register number
719 * @gssr: semaphore flags to acquire
720 **/
721static s32 ixgbe_mii_bus_read_generic_c45(struct ixgbe_hw *hw, int addr,
722 int devad, int regnum, u32 gssr)
723{
724 u32 hwaddr, cmd;
725 s32 data;
726
727 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
728 return -EBUSY;
729
730 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
731 hwaddr |= devad << 16 | regnum;
732 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
733
734 data = ixgbe_msca_cmd(hw, cmd);
735 if (data < 0)
736 goto mii_bus_read_done;
737
738 cmd = hwaddr | IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND;
739 data = ixgbe_msca_cmd(hw, cmd);
740 if (data < 0)
741 goto mii_bus_read_done;
742
743 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
744 data = (data >> IXGBE_MSRWD_READ_DATA_SHIFT) & GENMASK(16, 0);
745
746mii_bus_read_done:
747 hw->mac.ops.release_swfw_sync(hw, gssr);
748 return data;
749}
750
751/**
752 * ixgbe_mii_bus_write_generic_c22 - Write a clause 22 register with gssr flags
753 * @hw: pointer to hardware structure
754 * @addr: address
755 * @regnum: register number
756 * @val: value to write
757 * @gssr: semaphore flags to acquire
758 **/
759static s32 ixgbe_mii_bus_write_generic_c22(struct ixgbe_hw *hw, int addr,
760 int regnum, u16 val, u32 gssr)
761{
762 u32 hwaddr, cmd;
763 s32 err;
764
765 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
766 return -EBUSY;
767
768 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
769
770 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
771 hwaddr |= (regnum & GENMASK(5, 0)) << IXGBE_MSCA_DEV_TYPE_SHIFT;
772 cmd = hwaddr | IXGBE_MSCA_OLD_PROTOCOL | IXGBE_MSCA_WRITE |
773 IXGBE_MSCA_MDI_COMMAND;
774
775 err = ixgbe_msca_cmd(hw, cmd);
776
777 hw->mac.ops.release_swfw_sync(hw, gssr);
778 return err;
779}
780
781/**
782 * ixgbe_mii_bus_write_generic_c45 - Write a clause 45 register with gssr flags
783 * @hw: pointer to hardware structure
784 * @addr: address
785 * @devad: device address to read
786 * @regnum: register number
787 * @val: value to write
788 * @gssr: semaphore flags to acquire
789 **/
790static s32 ixgbe_mii_bus_write_generic_c45(struct ixgbe_hw *hw, int addr,
791 int devad, int regnum, u16 val,
792 u32 gssr)
793{
794 u32 hwaddr, cmd;
795 s32 err;
796
797 if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
798 return -EBUSY;
799
800 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)val);
801
802 hwaddr = addr << IXGBE_MSCA_PHY_ADDR_SHIFT;
803 hwaddr |= devad << 16 | regnum;
804 cmd = hwaddr | IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND;
805
806 err = ixgbe_msca_cmd(hw, cmd);
807 if (err < 0)
808 goto mii_bus_write_done;
809
810 cmd = hwaddr | IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND;
811 err = ixgbe_msca_cmd(hw, cmd);
812
813mii_bus_write_done:
814 hw->mac.ops.release_swfw_sync(hw, gssr);
815 return err;
816}
817
818/**
819 * ixgbe_mii_bus_read_c22 - Read a clause 22 register
820 * @bus: pointer to mii_bus structure which points to our driver private
821 * @addr: address
822 * @regnum: register number
823 **/
824static s32 ixgbe_mii_bus_read_c22(struct mii_bus *bus, int addr, int regnum)
825{
826 struct ixgbe_adapter *adapter = bus->priv;
827 struct ixgbe_hw *hw = &adapter->hw;
828 u32 gssr = hw->phy.phy_semaphore_mask;
829
830 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
831}
832
833/**
834 * ixgbe_mii_bus_read_c45 - Read a clause 45 register
835 * @bus: pointer to mii_bus structure which points to our driver private
836 * @devad: device address to read
837 * @addr: address
838 * @regnum: register number
839 **/
840static s32 ixgbe_mii_bus_read_c45(struct mii_bus *bus, int devad, int addr,
841 int regnum)
842{
843 struct ixgbe_adapter *adapter = bus->priv;
844 struct ixgbe_hw *hw = &adapter->hw;
845 u32 gssr = hw->phy.phy_semaphore_mask;
846
847 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
848}
849
850/**
851 * ixgbe_mii_bus_write_c22 - Write a clause 22 register
852 * @bus: pointer to mii_bus structure which points to our driver private
853 * @addr: address
854 * @regnum: register number
855 * @val: value to write
856 **/
857static s32 ixgbe_mii_bus_write_c22(struct mii_bus *bus, int addr, int regnum,
858 u16 val)
859{
860 struct ixgbe_adapter *adapter = bus->priv;
861 struct ixgbe_hw *hw = &adapter->hw;
862 u32 gssr = hw->phy.phy_semaphore_mask;
863
864 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
865}
866
867/**
868 * ixgbe_mii_bus_write_c45 - Write a clause 45 register
869 * @bus: pointer to mii_bus structure which points to our driver private
870 * @addr: address
871 * @devad: device address to read
872 * @regnum: register number
873 * @val: value to write
874 **/
875static s32 ixgbe_mii_bus_write_c45(struct mii_bus *bus, int addr, int devad,
876 int regnum, u16 val)
877{
878 struct ixgbe_adapter *adapter = bus->priv;
879 struct ixgbe_hw *hw = &adapter->hw;
880 u32 gssr = hw->phy.phy_semaphore_mask;
881
882 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
883 gssr);
884}
885
886/**
887 * ixgbe_x550em_a_mii_bus_read_c22 - Read a clause 22 register on x550em_a
888 * @bus: pointer to mii_bus structure which points to our driver private
889 * @addr: address
890 * @regnum: register number
891 **/
892static s32 ixgbe_x550em_a_mii_bus_read_c22(struct mii_bus *bus, int addr,
893 int regnum)
894{
895 struct ixgbe_adapter *adapter = bus->priv;
896 struct ixgbe_hw *hw = &adapter->hw;
897 u32 gssr = hw->phy.phy_semaphore_mask;
898
899 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
900 return ixgbe_mii_bus_read_generic_c22(hw, addr, regnum, gssr);
901}
902
903/**
904 * ixgbe_x550em_a_mii_bus_read_c45 - Read a clause 45 register on x550em_a
905 * @bus: pointer to mii_bus structure which points to our driver private
906 * @addr: address
907 * @devad: device address to read
908 * @regnum: register number
909 **/
910static s32 ixgbe_x550em_a_mii_bus_read_c45(struct mii_bus *bus, int addr,
911 int devad, int regnum)
912{
913 struct ixgbe_adapter *adapter = bus->priv;
914 struct ixgbe_hw *hw = &adapter->hw;
915 u32 gssr = hw->phy.phy_semaphore_mask;
916
917 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
918 return ixgbe_mii_bus_read_generic_c45(hw, addr, devad, regnum, gssr);
919}
920
921/**
922 * ixgbe_x550em_a_mii_bus_write_c22 - Write a clause 22 register on x550em_a
923 * @bus: pointer to mii_bus structure which points to our driver private
924 * @addr: address
925 * @regnum: register number
926 * @val: value to write
927 **/
928static s32 ixgbe_x550em_a_mii_bus_write_c22(struct mii_bus *bus, int addr,
929 int regnum, u16 val)
930{
931 struct ixgbe_adapter *adapter = bus->priv;
932 struct ixgbe_hw *hw = &adapter->hw;
933 u32 gssr = hw->phy.phy_semaphore_mask;
934
935 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
936 return ixgbe_mii_bus_write_generic_c22(hw, addr, regnum, val, gssr);
937}
938
939/**
940 * ixgbe_x550em_a_mii_bus_write_c45 - Write a clause 45 register on x550em_a
941 * @bus: pointer to mii_bus structure which points to our driver private
942 * @addr: address
943 * @devad: device address to read
944 * @regnum: register number
945 * @val: value to write
946 **/
947static s32 ixgbe_x550em_a_mii_bus_write_c45(struct mii_bus *bus, int addr,
948 int devad, int regnum, u16 val)
949{
950 struct ixgbe_adapter *adapter = bus->priv;
951 struct ixgbe_hw *hw = &adapter->hw;
952 u32 gssr = hw->phy.phy_semaphore_mask;
953
954 gssr |= IXGBE_GSSR_TOKEN_SM | IXGBE_GSSR_PHY0_SM;
955 return ixgbe_mii_bus_write_generic_c45(hw, addr, devad, regnum, val,
956 gssr);
957}
958
959/**
960 * ixgbe_get_first_secondary_devfn - get first device downstream of root port
961 * @devfn: PCI_DEVFN of root port on domain 0, bus 0
962 *
963 * Returns pci_dev pointer to PCI_DEVFN(0, 0) on subordinate side of root
964 * on domain 0, bus 0, devfn = 'devfn'
965 **/
966static struct pci_dev *ixgbe_get_first_secondary_devfn(unsigned int devfn)
967{
968 struct pci_dev *rp_pdev;
969 int bus;
970
971 rp_pdev = pci_get_domain_bus_and_slot(0, 0, devfn);
972 if (rp_pdev && rp_pdev->subordinate) {
973 bus = rp_pdev->subordinate->number;
974 pci_dev_put(rp_pdev);
975 return pci_get_domain_bus_and_slot(0, bus, 0);
976 }
977
978 pci_dev_put(rp_pdev);
979 return NULL;
980}
981
982/**
983 * ixgbe_x550em_a_has_mii - is this the first ixgbe x550em_a PCI function?
984 * @hw: pointer to hardware structure
985 *
986 * Returns true if hw points to lowest numbered PCI B:D.F x550_em_a device in
987 * the SoC. There are up to 4 MACs sharing a single MDIO bus on the x550em_a,
988 * but we only want to register one MDIO bus.
989 **/
990static bool ixgbe_x550em_a_has_mii(struct ixgbe_hw *hw)
991{
992 struct ixgbe_adapter *adapter = hw->back;
993 struct pci_dev *pdev = adapter->pdev;
994 struct pci_dev *func0_pdev;
995 bool has_mii = false;
996
997 /* For the C3000 family of SoCs (x550em_a) the internal ixgbe devices
998 * are always downstream of root ports @ 0000:00:16.0 & 0000:00:17.0
999 * It's not valid for function 0 to be disabled and function 1 is up,
1000 * so the lowest numbered ixgbe dev will be device 0 function 0 on one
1001 * of those two root ports
1002 */
1003 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x16, 0));
1004 if (func0_pdev) {
1005 if (func0_pdev == pdev)
1006 has_mii = true;
1007 goto out;
1008 }
1009 func0_pdev = ixgbe_get_first_secondary_devfn(PCI_DEVFN(0x17, 0));
1010 if (func0_pdev == pdev)
1011 has_mii = true;
1012
1013out:
1014 pci_dev_put(func0_pdev);
1015 return has_mii;
1016}
1017
1018/**
1019 * ixgbe_mii_bus_init - mii_bus structure setup
1020 * @hw: pointer to hardware structure
1021 *
1022 * Returns 0 on success, negative on failure
1023 *
1024 * ixgbe_mii_bus_init initializes a mii_bus structure in adapter
1025 **/
1026s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw)
1027{
1028 s32 (*write_c22)(struct mii_bus *bus, int addr, int regnum, u16 val);
1029 s32 (*read_c22)(struct mii_bus *bus, int addr, int regnum);
1030 s32 (*write_c45)(struct mii_bus *bus, int addr, int devad, int regnum,
1031 u16 val);
1032 s32 (*read_c45)(struct mii_bus *bus, int addr, int devad, int regnum);
1033 struct ixgbe_adapter *adapter = hw->back;
1034 struct pci_dev *pdev = adapter->pdev;
1035 struct device *dev = &adapter->netdev->dev;
1036 struct mii_bus *bus;
1037
1038 switch (hw->device_id) {
1039 /* C3000 SoCs */
1040 case IXGBE_DEV_ID_X550EM_A_KR:
1041 case IXGBE_DEV_ID_X550EM_A_KR_L:
1042 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1043 case IXGBE_DEV_ID_X550EM_A_SGMII:
1044 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
1045 case IXGBE_DEV_ID_X550EM_A_10G_T:
1046 case IXGBE_DEV_ID_X550EM_A_SFP:
1047 case IXGBE_DEV_ID_X550EM_A_1G_T:
1048 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
1049 if (!ixgbe_x550em_a_has_mii(hw))
1050 return 0;
1051 read_c22 = ixgbe_x550em_a_mii_bus_read_c22;
1052 write_c22 = ixgbe_x550em_a_mii_bus_write_c22;
1053 read_c45 = ixgbe_x550em_a_mii_bus_read_c45;
1054 write_c45 = ixgbe_x550em_a_mii_bus_write_c45;
1055 break;
1056 default:
1057 read_c22 = ixgbe_mii_bus_read_c22;
1058 write_c22 = ixgbe_mii_bus_write_c22;
1059 read_c45 = ixgbe_mii_bus_read_c45;
1060 write_c45 = ixgbe_mii_bus_write_c45;
1061 break;
1062 }
1063
1064 bus = devm_mdiobus_alloc(dev);
1065 if (!bus)
1066 return -ENOMEM;
1067
1068 bus->read = read_c22;
1069 bus->write = write_c22;
1070 bus->read_c45 = read_c45;
1071 bus->write_c45 = write_c45;
1072
1073 /* Use the position of the device in the PCI hierarchy as the id */
1074 snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mdio-%s", ixgbe_driver_name,
1075 pci_name(pdev));
1076
1077 bus->name = "ixgbe-mdio";
1078 bus->priv = adapter;
1079 bus->parent = dev;
1080 bus->phy_mask = GENMASK(31, 0);
1081
1082 /* Support clause 22/45 natively. ixgbe_probe() sets MDIO_EMULATE_C22
1083 * unfortunately that causes some clause 22 frames to be sent with
1084 * clause 45 addressing. We don't want that.
1085 */
1086 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_SUPPORTS_C22;
1087
1088 adapter->mii_bus = bus;
1089 return mdiobus_register(bus);
1090}
1091
1092/**
1093 * ixgbe_setup_phy_link_generic - Set and restart autoneg
1094 * @hw: pointer to hardware structure
1095 *
1096 * Restart autonegotiation and PHY and waits for completion.
1097 **/
1098s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
1099{
1100 s32 status = 0;
1101 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1102 bool autoneg = false;
1103 ixgbe_link_speed speed;
1104
1105 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1106
1107 /* Set or unset auto-negotiation 10G advertisement */
1108 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, &autoneg_reg);
1109
1110 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1111 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
1112 (speed & IXGBE_LINK_SPEED_10GB_FULL))
1113 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1114
1115 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, MDIO_MMD_AN, autoneg_reg);
1116
1117 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1118 MDIO_MMD_AN, &autoneg_reg);
1119
1120 if (hw->mac.type == ixgbe_mac_X550) {
1121 /* Set or unset auto-negotiation 5G advertisement */
1122 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
1123 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
1124 (speed & IXGBE_LINK_SPEED_5GB_FULL))
1125 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
1126
1127 /* Set or unset auto-negotiation 2.5G advertisement */
1128 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
1129 if ((hw->phy.autoneg_advertised &
1130 IXGBE_LINK_SPEED_2_5GB_FULL) &&
1131 (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
1132 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
1133 }
1134
1135 /* Set or unset auto-negotiation 1G advertisement */
1136 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
1137 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
1138 (speed & IXGBE_LINK_SPEED_1GB_FULL))
1139 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
1140
1141 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
1142 MDIO_MMD_AN, autoneg_reg);
1143
1144 /* Set or unset auto-negotiation 100M advertisement */
1145 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, &autoneg_reg);
1146
1147 autoneg_reg &= ~(ADVERTISE_100FULL | ADVERTISE_100HALF);
1148 if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
1149 (speed & IXGBE_LINK_SPEED_100_FULL))
1150 autoneg_reg |= ADVERTISE_100FULL;
1151
1152 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, MDIO_MMD_AN, autoneg_reg);
1153
1154 /* Blocked by MNG FW so don't reset PHY */
1155 if (ixgbe_check_reset_blocked(hw))
1156 return 0;
1157
1158 /* Restart PHY autonegotiation and wait for completion */
1159 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1160 MDIO_MMD_AN, &autoneg_reg);
1161
1162 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1163
1164 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1165 MDIO_MMD_AN, autoneg_reg);
1166
1167 return status;
1168}
1169
1170/**
1171 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
1172 * @hw: pointer to hardware structure
1173 * @speed: new link speed
1174 * @autoneg_wait_to_complete: unused
1175 **/
1176s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
1177 ixgbe_link_speed speed,
1178 bool autoneg_wait_to_complete)
1179{
1180 /* Clear autoneg_advertised and set new values based on input link
1181 * speed.
1182 */
1183 hw->phy.autoneg_advertised = 0;
1184
1185 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1186 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
1187
1188 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
1189 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
1190
1191 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
1192 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
1193
1194 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1195 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
1196
1197 if (speed & IXGBE_LINK_SPEED_100_FULL)
1198 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
1199
1200 if (speed & IXGBE_LINK_SPEED_10_FULL)
1201 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
1202
1203 /* Setup link based on the new speed settings */
1204 if (hw->phy.ops.setup_link)
1205 hw->phy.ops.setup_link(hw);
1206
1207 return 0;
1208}
1209
1210/**
1211 * ixgbe_get_copper_speeds_supported - Get copper link speed from phy
1212 * @hw: pointer to hardware structure
1213 *
1214 * Determines the supported link capabilities by reading the PHY auto
1215 * negotiation register.
1216 */
1217static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
1218{
1219 u16 speed_ability;
1220 s32 status;
1221
1222 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
1223 &speed_ability);
1224 if (status)
1225 return status;
1226
1227 if (speed_ability & MDIO_SPEED_10G)
1228 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
1229 if (speed_ability & MDIO_PMA_SPEED_1000)
1230 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
1231 if (speed_ability & MDIO_PMA_SPEED_100)
1232 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
1233
1234 switch (hw->mac.type) {
1235 case ixgbe_mac_X550:
1236 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
1237 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
1238 break;
1239 case ixgbe_mac_X550EM_x:
1240 case ixgbe_mac_x550em_a:
1241 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
1242 break;
1243 default:
1244 break;
1245 }
1246
1247 return 0;
1248}
1249
1250/**
1251 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
1252 * @hw: pointer to hardware structure
1253 * @speed: pointer to link speed
1254 * @autoneg: boolean auto-negotiation value
1255 */
1256s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
1257 ixgbe_link_speed *speed,
1258 bool *autoneg)
1259{
1260 s32 status = 0;
1261
1262 *autoneg = true;
1263 if (!hw->phy.speeds_supported)
1264 status = ixgbe_get_copper_speeds_supported(hw);
1265
1266 *speed = hw->phy.speeds_supported;
1267 return status;
1268}
1269
1270/**
1271 * ixgbe_check_phy_link_tnx - Determine link and speed status
1272 * @hw: pointer to hardware structure
1273 * @speed: link speed
1274 * @link_up: status of link
1275 *
1276 * Reads the VS1 register to determine if link is up and the current speed for
1277 * the PHY.
1278 **/
1279s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
1280 bool *link_up)
1281{
1282 s32 status;
1283 u32 time_out;
1284 u32 max_time_out = 10;
1285 u16 phy_link = 0;
1286 u16 phy_speed = 0;
1287 u16 phy_data = 0;
1288
1289 /* Initialize speed and link to default case */
1290 *link_up = false;
1291 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1292
1293 /*
1294 * Check current speed and link status of the PHY register.
1295 * This is a vendor specific register and may have to
1296 * be changed for other copper PHYs.
1297 */
1298 for (time_out = 0; time_out < max_time_out; time_out++) {
1299 udelay(10);
1300 status = hw->phy.ops.read_reg(hw,
1301 MDIO_STAT1,
1302 MDIO_MMD_VEND1,
1303 &phy_data);
1304 phy_link = phy_data &
1305 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1306 phy_speed = phy_data &
1307 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1308 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1309 *link_up = true;
1310 if (phy_speed ==
1311 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1312 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1313 break;
1314 }
1315 }
1316
1317 return status;
1318}
1319
1320/**
1321 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
1322 * @hw: pointer to hardware structure
1323 *
1324 * Restart autonegotiation and PHY and waits for completion.
1325 * This function always returns success, this is nessary since
1326 * it is called via a function pointer that could call other
1327 * functions that could return an error.
1328 **/
1329s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1330{
1331 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1332 bool autoneg = false;
1333 ixgbe_link_speed speed;
1334
1335 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1336
1337 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1338 /* Set or unset auto-negotiation 10G advertisement */
1339 hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
1340 MDIO_MMD_AN,
1341 &autoneg_reg);
1342
1343 autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G;
1344 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1345 autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G;
1346
1347 hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL,
1348 MDIO_MMD_AN,
1349 autoneg_reg);
1350 }
1351
1352 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1353 /* Set or unset auto-negotiation 1G advertisement */
1354 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1355 MDIO_MMD_AN,
1356 &autoneg_reg);
1357
1358 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1359 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1360 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1361
1362 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1363 MDIO_MMD_AN,
1364 autoneg_reg);
1365 }
1366
1367 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1368 /* Set or unset auto-negotiation 100M advertisement */
1369 hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
1370 MDIO_MMD_AN,
1371 &autoneg_reg);
1372
1373 autoneg_reg &= ~(ADVERTISE_100FULL |
1374 ADVERTISE_100HALF);
1375 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1376 autoneg_reg |= ADVERTISE_100FULL;
1377
1378 hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
1379 MDIO_MMD_AN,
1380 autoneg_reg);
1381 }
1382
1383 /* Blocked by MNG FW so don't reset PHY */
1384 if (ixgbe_check_reset_blocked(hw))
1385 return 0;
1386
1387 /* Restart PHY autonegotiation and wait for completion */
1388 hw->phy.ops.read_reg(hw, MDIO_CTRL1,
1389 MDIO_MMD_AN, &autoneg_reg);
1390
1391 autoneg_reg |= MDIO_AN_CTRL1_RESTART;
1392
1393 hw->phy.ops.write_reg(hw, MDIO_CTRL1,
1394 MDIO_MMD_AN, autoneg_reg);
1395 return 0;
1396}
1397
1398/**
1399 * ixgbe_reset_phy_nl - Performs a PHY reset
1400 * @hw: pointer to hardware structure
1401 **/
1402s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1403{
1404 u16 phy_offset, control, eword, edata, block_crc;
1405 bool end_data = false;
1406 u16 list_offset, data_offset;
1407 u16 phy_data = 0;
1408 s32 ret_val;
1409 u32 i;
1410
1411 /* Blocked by MNG FW so bail */
1412 if (ixgbe_check_reset_blocked(hw))
1413 return 0;
1414
1415 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data);
1416
1417 /* reset the PHY and poll for completion */
1418 hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1419 (phy_data | MDIO_CTRL1_RESET));
1420
1421 for (i = 0; i < 100; i++) {
1422 hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS,
1423 &phy_data);
1424 if ((phy_data & MDIO_CTRL1_RESET) == 0)
1425 break;
1426 usleep_range(10000, 20000);
1427 }
1428
1429 if ((phy_data & MDIO_CTRL1_RESET) != 0) {
1430 hw_dbg(hw, "PHY reset did not complete.\n");
1431 return -EIO;
1432 }
1433
1434 /* Get init offsets */
1435 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1436 &data_offset);
1437 if (ret_val)
1438 return ret_val;
1439
1440 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1441 data_offset++;
1442 while (!end_data) {
1443 /*
1444 * Read control word from PHY init contents offset
1445 */
1446 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1447 if (ret_val)
1448 goto err_eeprom;
1449 control = FIELD_GET(IXGBE_CONTROL_MASK_NL, eword);
1450 edata = eword & IXGBE_DATA_MASK_NL;
1451 switch (control) {
1452 case IXGBE_DELAY_NL:
1453 data_offset++;
1454 hw_dbg(hw, "DELAY: %d MS\n", edata);
1455 usleep_range(edata * 1000, edata * 2000);
1456 break;
1457 case IXGBE_DATA_NL:
1458 hw_dbg(hw, "DATA:\n");
1459 data_offset++;
1460 ret_val = hw->eeprom.ops.read(hw, data_offset++,
1461 &phy_offset);
1462 if (ret_val)
1463 goto err_eeprom;
1464 for (i = 0; i < edata; i++) {
1465 ret_val = hw->eeprom.ops.read(hw, data_offset,
1466 &eword);
1467 if (ret_val)
1468 goto err_eeprom;
1469 hw->phy.ops.write_reg(hw, phy_offset,
1470 MDIO_MMD_PMAPMD, eword);
1471 hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword,
1472 phy_offset);
1473 data_offset++;
1474 phy_offset++;
1475 }
1476 break;
1477 case IXGBE_CONTROL_NL:
1478 data_offset++;
1479 hw_dbg(hw, "CONTROL:\n");
1480 if (edata == IXGBE_CONTROL_EOL_NL) {
1481 hw_dbg(hw, "EOL\n");
1482 end_data = true;
1483 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1484 hw_dbg(hw, "SOL\n");
1485 } else {
1486 hw_dbg(hw, "Bad control value\n");
1487 return -EIO;
1488 }
1489 break;
1490 default:
1491 hw_dbg(hw, "Bad control type\n");
1492 return -EIO;
1493 }
1494 }
1495
1496 return ret_val;
1497
1498err_eeprom:
1499 hw_err(hw, "eeprom read at offset %d failed\n", data_offset);
1500 return -EIO;
1501}
1502
1503/**
1504 * ixgbe_identify_module_generic - Identifies module type
1505 * @hw: pointer to hardware structure
1506 *
1507 * Determines HW type and calls appropriate function.
1508 **/
1509s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1510{
1511 switch (hw->mac.ops.get_media_type(hw)) {
1512 case ixgbe_media_type_fiber:
1513 return ixgbe_identify_sfp_module_generic(hw);
1514 case ixgbe_media_type_fiber_qsfp:
1515 return ixgbe_identify_qsfp_module_generic(hw);
1516 default:
1517 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1518 return -ENOENT;
1519 }
1520
1521 return -ENOENT;
1522}
1523
1524/**
1525 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1526 * @hw: pointer to hardware structure
1527 *
1528 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1529 **/
1530s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1531{
1532 struct ixgbe_adapter *adapter = hw->back;
1533 s32 status;
1534 u32 vendor_oui = 0;
1535 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1536 u8 identifier = 0;
1537 u8 comp_codes_1g = 0;
1538 u8 comp_codes_10g = 0;
1539 u8 oui_bytes[3] = {0, 0, 0};
1540 u8 cable_tech = 0;
1541 u8 cable_spec = 0;
1542 u16 enforce_sfp = 0;
1543
1544 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1545 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1546 return -ENOENT;
1547 }
1548
1549 /* LAN ID is needed for sfp_type determination */
1550 hw->mac.ops.set_lan_id(hw);
1551
1552 status = hw->phy.ops.read_i2c_eeprom(hw,
1553 IXGBE_SFF_IDENTIFIER,
1554 &identifier);
1555
1556 if (status)
1557 goto err_read_i2c_eeprom;
1558
1559 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1560 hw->phy.type = ixgbe_phy_sfp_unsupported;
1561 return -EOPNOTSUPP;
1562 }
1563 status = hw->phy.ops.read_i2c_eeprom(hw,
1564 IXGBE_SFF_1GBE_COMP_CODES,
1565 &comp_codes_1g);
1566
1567 if (status)
1568 goto err_read_i2c_eeprom;
1569
1570 status = hw->phy.ops.read_i2c_eeprom(hw,
1571 IXGBE_SFF_10GBE_COMP_CODES,
1572 &comp_codes_10g);
1573
1574 if (status)
1575 goto err_read_i2c_eeprom;
1576 status = hw->phy.ops.read_i2c_eeprom(hw,
1577 IXGBE_SFF_CABLE_TECHNOLOGY,
1578 &cable_tech);
1579
1580 if (status)
1581 goto err_read_i2c_eeprom;
1582
1583 /* ID Module
1584 * =========
1585 * 0 SFP_DA_CU
1586 * 1 SFP_SR
1587 * 2 SFP_LR
1588 * 3 SFP_DA_CORE0 - 82599-specific
1589 * 4 SFP_DA_CORE1 - 82599-specific
1590 * 5 SFP_SR/LR_CORE0 - 82599-specific
1591 * 6 SFP_SR/LR_CORE1 - 82599-specific
1592 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1593 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1594 * 9 SFP_1g_cu_CORE0 - 82599-specific
1595 * 10 SFP_1g_cu_CORE1 - 82599-specific
1596 * 11 SFP_1g_sx_CORE0 - 82599-specific
1597 * 12 SFP_1g_sx_CORE1 - 82599-specific
1598 */
1599 if (hw->mac.type == ixgbe_mac_82598EB) {
1600 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1601 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1602 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1603 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1604 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1605 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1606 else
1607 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1608 } else {
1609 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1610 if (hw->bus.lan_id == 0)
1611 hw->phy.sfp_type =
1612 ixgbe_sfp_type_da_cu_core0;
1613 else
1614 hw->phy.sfp_type =
1615 ixgbe_sfp_type_da_cu_core1;
1616 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1617 hw->phy.ops.read_i2c_eeprom(
1618 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1619 &cable_spec);
1620 if (cable_spec &
1621 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1622 if (hw->bus.lan_id == 0)
1623 hw->phy.sfp_type =
1624 ixgbe_sfp_type_da_act_lmt_core0;
1625 else
1626 hw->phy.sfp_type =
1627 ixgbe_sfp_type_da_act_lmt_core1;
1628 } else {
1629 hw->phy.sfp_type =
1630 ixgbe_sfp_type_unknown;
1631 }
1632 } else if (comp_codes_10g &
1633 (IXGBE_SFF_10GBASESR_CAPABLE |
1634 IXGBE_SFF_10GBASELR_CAPABLE)) {
1635 if (hw->bus.lan_id == 0)
1636 hw->phy.sfp_type =
1637 ixgbe_sfp_type_srlr_core0;
1638 else
1639 hw->phy.sfp_type =
1640 ixgbe_sfp_type_srlr_core1;
1641 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1642 if (hw->bus.lan_id == 0)
1643 hw->phy.sfp_type =
1644 ixgbe_sfp_type_1g_cu_core0;
1645 else
1646 hw->phy.sfp_type =
1647 ixgbe_sfp_type_1g_cu_core1;
1648 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1649 if (hw->bus.lan_id == 0)
1650 hw->phy.sfp_type =
1651 ixgbe_sfp_type_1g_sx_core0;
1652 else
1653 hw->phy.sfp_type =
1654 ixgbe_sfp_type_1g_sx_core1;
1655 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1656 if (hw->bus.lan_id == 0)
1657 hw->phy.sfp_type =
1658 ixgbe_sfp_type_1g_lx_core0;
1659 else
1660 hw->phy.sfp_type =
1661 ixgbe_sfp_type_1g_lx_core1;
1662 } else {
1663 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1664 }
1665 }
1666
1667 if (hw->phy.sfp_type != stored_sfp_type)
1668 hw->phy.sfp_setup_needed = true;
1669
1670 /* Determine if the SFP+ PHY is dual speed or not. */
1671 hw->phy.multispeed_fiber = false;
1672 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1673 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1674 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1675 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1676 hw->phy.multispeed_fiber = true;
1677
1678 /* Determine PHY vendor */
1679 if (hw->phy.type != ixgbe_phy_nl) {
1680 hw->phy.id = identifier;
1681 status = hw->phy.ops.read_i2c_eeprom(hw,
1682 IXGBE_SFF_VENDOR_OUI_BYTE0,
1683 &oui_bytes[0]);
1684
1685 if (status != 0)
1686 goto err_read_i2c_eeprom;
1687
1688 status = hw->phy.ops.read_i2c_eeprom(hw,
1689 IXGBE_SFF_VENDOR_OUI_BYTE1,
1690 &oui_bytes[1]);
1691
1692 if (status != 0)
1693 goto err_read_i2c_eeprom;
1694
1695 status = hw->phy.ops.read_i2c_eeprom(hw,
1696 IXGBE_SFF_VENDOR_OUI_BYTE2,
1697 &oui_bytes[2]);
1698
1699 if (status != 0)
1700 goto err_read_i2c_eeprom;
1701
1702 vendor_oui =
1703 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1704 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1705 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1706
1707 switch (vendor_oui) {
1708 case IXGBE_SFF_VENDOR_OUI_TYCO:
1709 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1710 hw->phy.type =
1711 ixgbe_phy_sfp_passive_tyco;
1712 break;
1713 case IXGBE_SFF_VENDOR_OUI_FTL:
1714 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1715 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1716 else
1717 hw->phy.type = ixgbe_phy_sfp_ftl;
1718 break;
1719 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1720 hw->phy.type = ixgbe_phy_sfp_avago;
1721 break;
1722 case IXGBE_SFF_VENDOR_OUI_INTEL:
1723 hw->phy.type = ixgbe_phy_sfp_intel;
1724 break;
1725 default:
1726 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1727 hw->phy.type =
1728 ixgbe_phy_sfp_passive_unknown;
1729 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1730 hw->phy.type =
1731 ixgbe_phy_sfp_active_unknown;
1732 else
1733 hw->phy.type = ixgbe_phy_sfp_unknown;
1734 break;
1735 }
1736 }
1737
1738 /* Allow any DA cable vendor */
1739 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1740 IXGBE_SFF_DA_ACTIVE_CABLE))
1741 return 0;
1742
1743 /* Verify supported 1G SFP modules */
1744 if (comp_codes_10g == 0 &&
1745 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1746 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1747 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1748 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1749 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1750 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1751 hw->phy.type = ixgbe_phy_sfp_unsupported;
1752 return -EOPNOTSUPP;
1753 }
1754
1755 /* Anything else 82598-based is supported */
1756 if (hw->mac.type == ixgbe_mac_82598EB)
1757 return 0;
1758
1759 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1760 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1761 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1762 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1763 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1764 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1765 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1766 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1767 /* Make sure we're a supported PHY type */
1768 if (hw->phy.type == ixgbe_phy_sfp_intel)
1769 return 0;
1770 if (hw->allow_unsupported_sfp) {
1771 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1772 return 0;
1773 }
1774 hw_dbg(hw, "SFP+ module not supported\n");
1775 hw->phy.type = ixgbe_phy_sfp_unsupported;
1776 return -EOPNOTSUPP;
1777 }
1778 return 0;
1779
1780err_read_i2c_eeprom:
1781 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1782 if (hw->phy.type != ixgbe_phy_nl) {
1783 hw->phy.id = 0;
1784 hw->phy.type = ixgbe_phy_unknown;
1785 }
1786 return -ENOENT;
1787}
1788
1789/**
1790 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1791 * @hw: pointer to hardware structure
1792 *
1793 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1794 **/
1795static s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1796{
1797 struct ixgbe_adapter *adapter = hw->back;
1798 s32 status;
1799 u32 vendor_oui = 0;
1800 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1801 u8 identifier = 0;
1802 u8 comp_codes_1g = 0;
1803 u8 comp_codes_10g = 0;
1804 u8 oui_bytes[3] = {0, 0, 0};
1805 u16 enforce_sfp = 0;
1806 u8 connector = 0;
1807 u8 cable_length = 0;
1808 u8 device_tech = 0;
1809 bool active_cable = false;
1810
1811 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1812 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1813 return -ENOENT;
1814 }
1815
1816 /* LAN ID is needed for sfp_type determination */
1817 hw->mac.ops.set_lan_id(hw);
1818
1819 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1820 &identifier);
1821
1822 if (status != 0)
1823 goto err_read_i2c_eeprom;
1824
1825 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1826 hw->phy.type = ixgbe_phy_sfp_unsupported;
1827 return -EOPNOTSUPP;
1828 }
1829
1830 hw->phy.id = identifier;
1831
1832 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1833 &comp_codes_10g);
1834
1835 if (status != 0)
1836 goto err_read_i2c_eeprom;
1837
1838 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1839 &comp_codes_1g);
1840
1841 if (status != 0)
1842 goto err_read_i2c_eeprom;
1843
1844 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1845 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1846 if (hw->bus.lan_id == 0)
1847 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1848 else
1849 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1850 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1851 IXGBE_SFF_10GBASELR_CAPABLE)) {
1852 if (hw->bus.lan_id == 0)
1853 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1854 else
1855 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1856 } else {
1857 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1858 active_cable = true;
1859
1860 if (!active_cable) {
1861 /* check for active DA cables that pre-date
1862 * SFF-8436 v3.6
1863 */
1864 hw->phy.ops.read_i2c_eeprom(hw,
1865 IXGBE_SFF_QSFP_CONNECTOR,
1866 &connector);
1867
1868 hw->phy.ops.read_i2c_eeprom(hw,
1869 IXGBE_SFF_QSFP_CABLE_LENGTH,
1870 &cable_length);
1871
1872 hw->phy.ops.read_i2c_eeprom(hw,
1873 IXGBE_SFF_QSFP_DEVICE_TECH,
1874 &device_tech);
1875
1876 if ((connector ==
1877 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1878 (cable_length > 0) &&
1879 ((device_tech >> 4) ==
1880 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1881 active_cable = true;
1882 }
1883
1884 if (active_cable) {
1885 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1886 if (hw->bus.lan_id == 0)
1887 hw->phy.sfp_type =
1888 ixgbe_sfp_type_da_act_lmt_core0;
1889 else
1890 hw->phy.sfp_type =
1891 ixgbe_sfp_type_da_act_lmt_core1;
1892 } else {
1893 /* unsupported module type */
1894 hw->phy.type = ixgbe_phy_sfp_unsupported;
1895 return -EOPNOTSUPP;
1896 }
1897 }
1898
1899 if (hw->phy.sfp_type != stored_sfp_type)
1900 hw->phy.sfp_setup_needed = true;
1901
1902 /* Determine if the QSFP+ PHY is dual speed or not. */
1903 hw->phy.multispeed_fiber = false;
1904 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1905 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1906 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1907 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1908 hw->phy.multispeed_fiber = true;
1909
1910 /* Determine PHY vendor for optical modules */
1911 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1912 IXGBE_SFF_10GBASELR_CAPABLE)) {
1913 status = hw->phy.ops.read_i2c_eeprom(hw,
1914 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1915 &oui_bytes[0]);
1916
1917 if (status != 0)
1918 goto err_read_i2c_eeprom;
1919
1920 status = hw->phy.ops.read_i2c_eeprom(hw,
1921 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1922 &oui_bytes[1]);
1923
1924 if (status != 0)
1925 goto err_read_i2c_eeprom;
1926
1927 status = hw->phy.ops.read_i2c_eeprom(hw,
1928 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1929 &oui_bytes[2]);
1930
1931 if (status != 0)
1932 goto err_read_i2c_eeprom;
1933
1934 vendor_oui =
1935 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1936 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1937 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1938
1939 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1940 hw->phy.type = ixgbe_phy_qsfp_intel;
1941 else
1942 hw->phy.type = ixgbe_phy_qsfp_unknown;
1943
1944 hw->mac.ops.get_device_caps(hw, &enforce_sfp);
1945 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1946 /* Make sure we're a supported PHY type */
1947 if (hw->phy.type == ixgbe_phy_qsfp_intel)
1948 return 0;
1949 if (hw->allow_unsupported_sfp) {
1950 e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1951 return 0;
1952 }
1953 hw_dbg(hw, "QSFP module not supported\n");
1954 hw->phy.type = ixgbe_phy_sfp_unsupported;
1955 return -EOPNOTSUPP;
1956 }
1957 return 0;
1958 }
1959 return 0;
1960
1961err_read_i2c_eeprom:
1962 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1963 hw->phy.id = 0;
1964 hw->phy.type = ixgbe_phy_unknown;
1965
1966 return -ENOENT;
1967}
1968
1969/**
1970 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1971 * @hw: pointer to hardware structure
1972 * @list_offset: offset to the SFP ID list
1973 * @data_offset: offset to the SFP data block
1974 *
1975 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1976 * so it returns the offsets to the phy init sequence block.
1977 **/
1978s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1979 u16 *list_offset,
1980 u16 *data_offset)
1981{
1982 u16 sfp_id;
1983 u16 sfp_type = hw->phy.sfp_type;
1984
1985 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1986 return -EOPNOTSUPP;
1987
1988 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1989 return -ENOENT;
1990
1991 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1992 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1993 return -EOPNOTSUPP;
1994
1995 /*
1996 * Limiting active cables and 1G Phys must be initialized as
1997 * SR modules
1998 */
1999 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
2000 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2001 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
2002 sfp_type == ixgbe_sfp_type_1g_sx_core0)
2003 sfp_type = ixgbe_sfp_type_srlr_core0;
2004 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
2005 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
2006 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
2007 sfp_type == ixgbe_sfp_type_1g_sx_core1)
2008 sfp_type = ixgbe_sfp_type_srlr_core1;
2009
2010 /* Read offset to PHY init contents */
2011 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
2012 hw_err(hw, "eeprom read at %d failed\n",
2013 IXGBE_PHY_INIT_OFFSET_NL);
2014 return -EIO;
2015 }
2016
2017 if ((!*list_offset) || (*list_offset == 0xFFFF))
2018 return -EIO;
2019
2020 /* Shift offset to first ID word */
2021 (*list_offset)++;
2022
2023 /*
2024 * Find the matching SFP ID in the EEPROM
2025 * and program the init sequence
2026 */
2027 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2028 goto err_phy;
2029
2030 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
2031 if (sfp_id == sfp_type) {
2032 (*list_offset)++;
2033 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
2034 goto err_phy;
2035 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
2036 hw_dbg(hw, "SFP+ module not supported\n");
2037 return -EOPNOTSUPP;
2038 } else {
2039 break;
2040 }
2041 } else {
2042 (*list_offset) += 2;
2043 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
2044 goto err_phy;
2045 }
2046 }
2047
2048 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
2049 hw_dbg(hw, "No matching SFP+ module found\n");
2050 return -EOPNOTSUPP;
2051 }
2052
2053 return 0;
2054
2055err_phy:
2056 hw_err(hw, "eeprom read at offset %d failed\n", *list_offset);
2057 return -EIO;
2058}
2059
2060/**
2061 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
2062 * @hw: pointer to hardware structure
2063 * @byte_offset: EEPROM byte offset to read
2064 * @eeprom_data: value read
2065 *
2066 * Performs byte read operation to SFP module's EEPROM over I2C interface.
2067 **/
2068s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2069 u8 *eeprom_data)
2070{
2071 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2072 IXGBE_I2C_EEPROM_DEV_ADDR,
2073 eeprom_data);
2074}
2075
2076/**
2077 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
2078 * @hw: pointer to hardware structure
2079 * @byte_offset: byte offset at address 0xA2
2080 * @sff8472_data: value read
2081 *
2082 * Performs byte read operation to SFP module's SFF-8472 data over I2C
2083 **/
2084s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
2085 u8 *sff8472_data)
2086{
2087 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
2088 IXGBE_I2C_EEPROM_DEV_ADDR2,
2089 sff8472_data);
2090}
2091
2092/**
2093 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
2094 * @hw: pointer to hardware structure
2095 * @byte_offset: EEPROM byte offset to write
2096 * @eeprom_data: value to write
2097 *
2098 * Performs byte write operation to SFP module's EEPROM over I2C interface.
2099 **/
2100s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
2101 u8 eeprom_data)
2102{
2103 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
2104 IXGBE_I2C_EEPROM_DEV_ADDR,
2105 eeprom_data);
2106}
2107
2108/**
2109 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
2110 * @hw: pointer to hardware structure
2111 * @offset: eeprom offset to be read
2112 * @addr: I2C address to be read
2113 */
2114static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
2115{
2116 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
2117 offset == IXGBE_SFF_IDENTIFIER &&
2118 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2119 return true;
2120 return false;
2121}
2122
2123/**
2124 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
2125 * @hw: pointer to hardware structure
2126 * @byte_offset: byte offset to read
2127 * @dev_addr: device address
2128 * @data: value read
2129 * @lock: true if to take and release semaphore
2130 *
2131 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2132 * a specified device address.
2133 */
2134static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2135 u8 dev_addr, u8 *data, bool lock)
2136{
2137 s32 status;
2138 u32 max_retry = 10;
2139 u32 retry = 0;
2140 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2141 bool nack = true;
2142
2143 if (hw->mac.type >= ixgbe_mac_X550)
2144 max_retry = 3;
2145 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2146 max_retry = IXGBE_SFP_DETECT_RETRIES;
2147
2148 *data = 0;
2149
2150 do {
2151 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2152 return -EBUSY;
2153
2154 ixgbe_i2c_start(hw);
2155
2156 /* Device Address and write indication */
2157 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2158 if (status != 0)
2159 goto fail;
2160
2161 status = ixgbe_get_i2c_ack(hw);
2162 if (status != 0)
2163 goto fail;
2164
2165 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2166 if (status != 0)
2167 goto fail;
2168
2169 status = ixgbe_get_i2c_ack(hw);
2170 if (status != 0)
2171 goto fail;
2172
2173 ixgbe_i2c_start(hw);
2174
2175 /* Device Address and read indication */
2176 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2177 if (status != 0)
2178 goto fail;
2179
2180 status = ixgbe_get_i2c_ack(hw);
2181 if (status != 0)
2182 goto fail;
2183
2184 status = ixgbe_clock_in_i2c_byte(hw, data);
2185 if (status != 0)
2186 goto fail;
2187
2188 status = ixgbe_clock_out_i2c_bit(hw, nack);
2189 if (status != 0)
2190 goto fail;
2191
2192 ixgbe_i2c_stop(hw);
2193 if (lock)
2194 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2195 return 0;
2196
2197fail:
2198 ixgbe_i2c_bus_clear(hw);
2199 if (lock) {
2200 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2201 msleep(100);
2202 }
2203 retry++;
2204 if (retry < max_retry)
2205 hw_dbg(hw, "I2C byte read error - Retrying.\n");
2206 else
2207 hw_dbg(hw, "I2C byte read error.\n");
2208
2209 } while (retry < max_retry);
2210
2211 return status;
2212}
2213
2214/**
2215 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2216 * @hw: pointer to hardware structure
2217 * @byte_offset: byte offset to read
2218 * @dev_addr: device address
2219 * @data: value read
2220 *
2221 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2222 * a specified device address.
2223 */
2224s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2225 u8 dev_addr, u8 *data)
2226{
2227 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2228 data, true);
2229}
2230
2231/**
2232 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2233 * @hw: pointer to hardware structure
2234 * @byte_offset: byte offset to read
2235 * @dev_addr: device address
2236 * @data: value read
2237 *
2238 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2239 * a specified device address.
2240 */
2241s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2242 u8 dev_addr, u8 *data)
2243{
2244 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2245 data, false);
2246}
2247
2248/**
2249 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2250 * @hw: pointer to hardware structure
2251 * @byte_offset: byte offset to write
2252 * @dev_addr: device address
2253 * @data: value to write
2254 * @lock: true if to take and release semaphore
2255 *
2256 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2257 * a specified device address.
2258 */
2259static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2260 u8 dev_addr, u8 data, bool lock)
2261{
2262 s32 status;
2263 u32 max_retry = 1;
2264 u32 retry = 0;
2265 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2266
2267 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2268 return -EBUSY;
2269
2270 do {
2271 ixgbe_i2c_start(hw);
2272
2273 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2274 if (status != 0)
2275 goto fail;
2276
2277 status = ixgbe_get_i2c_ack(hw);
2278 if (status != 0)
2279 goto fail;
2280
2281 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2282 if (status != 0)
2283 goto fail;
2284
2285 status = ixgbe_get_i2c_ack(hw);
2286 if (status != 0)
2287 goto fail;
2288
2289 status = ixgbe_clock_out_i2c_byte(hw, data);
2290 if (status != 0)
2291 goto fail;
2292
2293 status = ixgbe_get_i2c_ack(hw);
2294 if (status != 0)
2295 goto fail;
2296
2297 ixgbe_i2c_stop(hw);
2298 if (lock)
2299 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2300 return 0;
2301
2302fail:
2303 ixgbe_i2c_bus_clear(hw);
2304 retry++;
2305 if (retry < max_retry)
2306 hw_dbg(hw, "I2C byte write error - Retrying.\n");
2307 else
2308 hw_dbg(hw, "I2C byte write error.\n");
2309 } while (retry < max_retry);
2310
2311 if (lock)
2312 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2313
2314 return status;
2315}
2316
2317/**
2318 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2319 * @hw: pointer to hardware structure
2320 * @byte_offset: byte offset to write
2321 * @dev_addr: device address
2322 * @data: value to write
2323 *
2324 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2325 * a specified device address.
2326 */
2327s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2328 u8 dev_addr, u8 data)
2329{
2330 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2331 data, true);
2332}
2333
2334/**
2335 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2336 * @hw: pointer to hardware structure
2337 * @byte_offset: byte offset to write
2338 * @dev_addr: device address
2339 * @data: value to write
2340 *
2341 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2342 * a specified device address.
2343 */
2344s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2345 u8 dev_addr, u8 data)
2346{
2347 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2348 data, false);
2349}
2350
2351/**
2352 * ixgbe_i2c_start - Sets I2C start condition
2353 * @hw: pointer to hardware structure
2354 *
2355 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2356 * Set bit-bang mode on X550 hardware.
2357 **/
2358static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2359{
2360 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2361
2362 i2cctl |= IXGBE_I2C_BB_EN(hw);
2363
2364 /* Start condition must begin with data and clock high */
2365 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2366 ixgbe_raise_i2c_clk(hw, &i2cctl);
2367
2368 /* Setup time for start condition (4.7us) */
2369 udelay(IXGBE_I2C_T_SU_STA);
2370
2371 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2372
2373 /* Hold time for start condition (4us) */
2374 udelay(IXGBE_I2C_T_HD_STA);
2375
2376 ixgbe_lower_i2c_clk(hw, &i2cctl);
2377
2378 /* Minimum low period of clock is 4.7 us */
2379 udelay(IXGBE_I2C_T_LOW);
2380
2381}
2382
2383/**
2384 * ixgbe_i2c_stop - Sets I2C stop condition
2385 * @hw: pointer to hardware structure
2386 *
2387 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2388 * Disables bit-bang mode and negates data output enable on X550
2389 * hardware.
2390 **/
2391static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2392{
2393 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2394 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2395 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2396 u32 bb_en_bit = IXGBE_I2C_BB_EN(hw);
2397
2398 /* Stop condition must begin with data low and clock high */
2399 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2400 ixgbe_raise_i2c_clk(hw, &i2cctl);
2401
2402 /* Setup time for stop condition (4us) */
2403 udelay(IXGBE_I2C_T_SU_STO);
2404
2405 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2406
2407 /* bus free time between stop and start (4.7us)*/
2408 udelay(IXGBE_I2C_T_BUF);
2409
2410 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2411 i2cctl &= ~bb_en_bit;
2412 i2cctl |= data_oe_bit | clk_oe_bit;
2413 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2414 IXGBE_WRITE_FLUSH(hw);
2415 }
2416}
2417
2418/**
2419 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2420 * @hw: pointer to hardware structure
2421 * @data: data byte to clock in
2422 *
2423 * Clocks in one byte data via I2C data/clock
2424 **/
2425static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2426{
2427 s32 i;
2428 bool bit = false;
2429
2430 *data = 0;
2431 for (i = 7; i >= 0; i--) {
2432 ixgbe_clock_in_i2c_bit(hw, &bit);
2433 *data |= bit << i;
2434 }
2435
2436 return 0;
2437}
2438
2439/**
2440 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2441 * @hw: pointer to hardware structure
2442 * @data: data byte clocked out
2443 *
2444 * Clocks out one byte data via I2C data/clock
2445 **/
2446static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2447{
2448 s32 status;
2449 s32 i;
2450 u32 i2cctl;
2451 bool bit = false;
2452
2453 for (i = 7; i >= 0; i--) {
2454 bit = (data >> i) & 0x1;
2455 status = ixgbe_clock_out_i2c_bit(hw, bit);
2456
2457 if (status != 0)
2458 break;
2459 }
2460
2461 /* Release SDA line (set high) */
2462 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2463 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2464 i2cctl |= IXGBE_I2C_DATA_OE_N_EN(hw);
2465 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2466 IXGBE_WRITE_FLUSH(hw);
2467
2468 return status;
2469}
2470
2471/**
2472 * ixgbe_get_i2c_ack - Polls for I2C ACK
2473 * @hw: pointer to hardware structure
2474 *
2475 * Clocks in/out one bit via I2C data/clock
2476 **/
2477static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2478{
2479 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2480 s32 status = 0;
2481 u32 i = 0;
2482 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2483 u32 timeout = 10;
2484 bool ack = true;
2485
2486 if (data_oe_bit) {
2487 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2488 i2cctl |= data_oe_bit;
2489 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2490 IXGBE_WRITE_FLUSH(hw);
2491 }
2492 ixgbe_raise_i2c_clk(hw, &i2cctl);
2493
2494 /* Minimum high period of clock is 4us */
2495 udelay(IXGBE_I2C_T_HIGH);
2496
2497 /* Poll for ACK. Note that ACK in I2C spec is
2498 * transition from 1 to 0 */
2499 for (i = 0; i < timeout; i++) {
2500 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2501 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2502
2503 udelay(1);
2504 if (ack == 0)
2505 break;
2506 }
2507
2508 if (ack == 1) {
2509 hw_dbg(hw, "I2C ack was not received.\n");
2510 status = -EIO;
2511 }
2512
2513 ixgbe_lower_i2c_clk(hw, &i2cctl);
2514
2515 /* Minimum low period of clock is 4.7 us */
2516 udelay(IXGBE_I2C_T_LOW);
2517
2518 return status;
2519}
2520
2521/**
2522 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2523 * @hw: pointer to hardware structure
2524 * @data: read data value
2525 *
2526 * Clocks in one bit via I2C data/clock
2527 **/
2528static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2529{
2530 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2531 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2532
2533 if (data_oe_bit) {
2534 i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2535 i2cctl |= data_oe_bit;
2536 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), i2cctl);
2537 IXGBE_WRITE_FLUSH(hw);
2538 }
2539 ixgbe_raise_i2c_clk(hw, &i2cctl);
2540
2541 /* Minimum high period of clock is 4us */
2542 udelay(IXGBE_I2C_T_HIGH);
2543
2544 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2545 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2546
2547 ixgbe_lower_i2c_clk(hw, &i2cctl);
2548
2549 /* Minimum low period of clock is 4.7 us */
2550 udelay(IXGBE_I2C_T_LOW);
2551
2552 return 0;
2553}
2554
2555/**
2556 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2557 * @hw: pointer to hardware structure
2558 * @data: data value to write
2559 *
2560 * Clocks out one bit via I2C data/clock
2561 **/
2562static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2563{
2564 s32 status;
2565 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2566
2567 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2568 if (status == 0) {
2569 ixgbe_raise_i2c_clk(hw, &i2cctl);
2570
2571 /* Minimum high period of clock is 4us */
2572 udelay(IXGBE_I2C_T_HIGH);
2573
2574 ixgbe_lower_i2c_clk(hw, &i2cctl);
2575
2576 /* Minimum low period of clock is 4.7 us.
2577 * This also takes care of the data hold time.
2578 */
2579 udelay(IXGBE_I2C_T_LOW);
2580 } else {
2581 hw_dbg(hw, "I2C data was not set to %X\n", data);
2582 return -EIO;
2583 }
2584
2585 return 0;
2586}
2587/**
2588 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2589 * @hw: pointer to hardware structure
2590 * @i2cctl: Current value of I2CCTL register
2591 *
2592 * Raises the I2C clock line '0'->'1'
2593 * Negates the I2C clock output enable on X550 hardware.
2594 **/
2595static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2596{
2597 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN(hw);
2598 u32 i = 0;
2599 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2600 u32 i2cctl_r = 0;
2601
2602 if (clk_oe_bit) {
2603 *i2cctl |= clk_oe_bit;
2604 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2605 }
2606
2607 for (i = 0; i < timeout; i++) {
2608 *i2cctl |= IXGBE_I2C_CLK_OUT(hw);
2609 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2610 IXGBE_WRITE_FLUSH(hw);
2611 /* SCL rise time (1000ns) */
2612 udelay(IXGBE_I2C_T_RISE);
2613
2614 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2615 if (i2cctl_r & IXGBE_I2C_CLK_IN(hw))
2616 break;
2617 }
2618}
2619
2620/**
2621 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2622 * @hw: pointer to hardware structure
2623 * @i2cctl: Current value of I2CCTL register
2624 *
2625 * Lowers the I2C clock line '1'->'0'
2626 * Asserts the I2C clock output enable on X550 hardware.
2627 **/
2628static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2629{
2630
2631 *i2cctl &= ~IXGBE_I2C_CLK_OUT(hw);
2632 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN(hw);
2633
2634 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2635 IXGBE_WRITE_FLUSH(hw);
2636
2637 /* SCL fall time (300ns) */
2638 udelay(IXGBE_I2C_T_FALL);
2639}
2640
2641/**
2642 * ixgbe_set_i2c_data - Sets the I2C data bit
2643 * @hw: pointer to hardware structure
2644 * @i2cctl: Current value of I2CCTL register
2645 * @data: I2C data value (0 or 1) to set
2646 *
2647 * Sets the I2C data bit
2648 * Asserts the I2C data output enable on X550 hardware.
2649 **/
2650static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2651{
2652 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2653
2654 if (data)
2655 *i2cctl |= IXGBE_I2C_DATA_OUT(hw);
2656 else
2657 *i2cctl &= ~IXGBE_I2C_DATA_OUT(hw);
2658 *i2cctl &= ~data_oe_bit;
2659
2660 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2661 IXGBE_WRITE_FLUSH(hw);
2662
2663 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2664 udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2665
2666 if (!data) /* Can't verify data in this case */
2667 return 0;
2668 if (data_oe_bit) {
2669 *i2cctl |= data_oe_bit;
2670 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2671 IXGBE_WRITE_FLUSH(hw);
2672 }
2673
2674 /* Verify data was set correctly */
2675 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2676 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2677 hw_dbg(hw, "Error - I2C data was not set to %X.\n", data);
2678 return -EIO;
2679 }
2680
2681 return 0;
2682}
2683
2684/**
2685 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2686 * @hw: pointer to hardware structure
2687 * @i2cctl: Current value of I2CCTL register
2688 *
2689 * Returns the I2C data bit value
2690 * Negates the I2C data output enable on X550 hardware.
2691 **/
2692static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2693{
2694 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN(hw);
2695
2696 if (data_oe_bit) {
2697 *i2cctl |= data_oe_bit;
2698 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL(hw), *i2cctl);
2699 IXGBE_WRITE_FLUSH(hw);
2700 udelay(IXGBE_I2C_T_FALL);
2701 }
2702
2703 if (*i2cctl & IXGBE_I2C_DATA_IN(hw))
2704 return true;
2705 return false;
2706}
2707
2708/**
2709 * ixgbe_i2c_bus_clear - Clears the I2C bus
2710 * @hw: pointer to hardware structure
2711 *
2712 * Clears the I2C bus by sending nine clock pulses.
2713 * Used when data line is stuck low.
2714 **/
2715static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2716{
2717 u32 i2cctl;
2718 u32 i;
2719
2720 ixgbe_i2c_start(hw);
2721 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL(hw));
2722
2723 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2724
2725 for (i = 0; i < 9; i++) {
2726 ixgbe_raise_i2c_clk(hw, &i2cctl);
2727
2728 /* Min high period of clock is 4us */
2729 udelay(IXGBE_I2C_T_HIGH);
2730
2731 ixgbe_lower_i2c_clk(hw, &i2cctl);
2732
2733 /* Min low period of clock is 4.7us*/
2734 udelay(IXGBE_I2C_T_LOW);
2735 }
2736
2737 ixgbe_i2c_start(hw);
2738
2739 /* Put the i2c bus back to default state */
2740 ixgbe_i2c_stop(hw);
2741}
2742
2743/**
2744 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2745 * @hw: pointer to hardware structure
2746 *
2747 * Checks if the LASI temp alarm status was triggered due to overtemp
2748 *
2749 * Return true when an overtemp event detected, otherwise false.
2750 **/
2751bool ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2752{
2753 u16 phy_data = 0;
2754 u32 status;
2755
2756 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2757 return false;
2758
2759 /* Check that the LASI temp alarm status was triggered */
2760 status = hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2761 MDIO_MMD_PMAPMD, &phy_data);
2762 if (status)
2763 return false;
2764
2765 return !!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM);
2766}
2767
2768/** ixgbe_set_copper_phy_power - Control power for copper phy
2769 * @hw: pointer to hardware structure
2770 * @on: true for on, false for off
2771 **/
2772s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2773{
2774 u32 status;
2775 u16 reg;
2776
2777 /* Bail if we don't have copper phy */
2778 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2779 return 0;
2780
2781 if (!on && ixgbe_mng_present(hw))
2782 return 0;
2783
2784 status = hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, ®);
2785 if (status)
2786 return status;
2787
2788 if (on) {
2789 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2790 } else {
2791 if (ixgbe_check_reset_blocked(hw))
2792 return 0;
2793 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2794 }
2795
2796 status = hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_VEND1, reg);
2797 return status;
2798}