1/*
   2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
   3 * Copyright © 2006-2009 Intel Corporation
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice (including the next
  13 * paragraph) shall be included in all copies or substantial portions of the
  14 * Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22 * DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors:
  25 *	Eric Anholt <eric@anholt.net>
  26 *	Jesse Barnes <jesse.barnes@intel.com>
  27 */
  28
  29#include <linux/delay.h>
  30#include <linux/hdmi.h>
  31#include <linux/i2c.h>
  32#include <linux/slab.h>
  33#include <linux/string_helpers.h>
  34
  35#include <drm/display/drm_hdcp_helper.h>
  36#include <drm/display/drm_hdmi_helper.h>
  37#include <drm/display/drm_scdc_helper.h>
  38#include <drm/drm_atomic_helper.h>
  39#include <drm/drm_crtc.h>
  40#include <drm/drm_edid.h>
  41#include <drm/intel_lpe_audio.h>
  42
  43#include "g4x_hdmi.h"
  44#include "i915_drv.h"
  45#include "i915_reg.h"
  46#include "intel_atomic.h"
  47#include "intel_audio.h"
  48#include "intel_connector.h"
  49#include "intel_cx0_phy.h"
  50#include "intel_ddi.h"
  51#include "intel_de.h"
  52#include "intel_display_driver.h"
  53#include "intel_display_types.h"
  54#include "intel_dp.h"
  55#include "intel_gmbus.h"
  56#include "intel_hdcp.h"
  57#include "intel_hdcp_regs.h"
  58#include "intel_hdmi.h"
  59#include "intel_lspcon.h"
  60#include "intel_panel.h"
  61#include "intel_snps_phy.h"
  62
  63inline struct drm_i915_private *intel_hdmi_to_i915(struct intel_hdmi *intel_hdmi)
  64{
  65	return to_i915(hdmi_to_dig_port(intel_hdmi)->base.base.dev);
  66}
  67
  68static void
  69assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
  70{
  71	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(intel_hdmi);
  72	u32 enabled_bits;
  73
  74	enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
  75
  76	drm_WARN(&dev_priv->drm,
  77		 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits,
  78		 "HDMI port enabled, expecting disabled\n");
  79}
  80
  81static void
  82assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv,
  83				     enum transcoder cpu_transcoder)
  84{
  85	drm_WARN(&dev_priv->drm,
  86		 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) &
  87		 TRANS_DDI_FUNC_ENABLE,
  88		 "HDMI transcoder function enabled, expecting disabled\n");
  89}
  90
  91static u32 g4x_infoframe_index(unsigned int type)
  92{
  93	switch (type) {
  94	case HDMI_PACKET_TYPE_GAMUT_METADATA:
  95		return VIDEO_DIP_SELECT_GAMUT;
  96	case HDMI_INFOFRAME_TYPE_AVI:
  97		return VIDEO_DIP_SELECT_AVI;
  98	case HDMI_INFOFRAME_TYPE_SPD:
  99		return VIDEO_DIP_SELECT_SPD;
 100	case HDMI_INFOFRAME_TYPE_VENDOR:
 101		return VIDEO_DIP_SELECT_VENDOR;
 102	default:
 103		MISSING_CASE(type);
 104		return 0;
 105	}
 106}
 107
 108static u32 g4x_infoframe_enable(unsigned int type)
 109{
 110	switch (type) {
 111	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 112		return VIDEO_DIP_ENABLE_GCP;
 113	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 114		return VIDEO_DIP_ENABLE_GAMUT;
 115	case DP_SDP_VSC:
 116		return 0;
 117	case HDMI_INFOFRAME_TYPE_AVI:
 118		return VIDEO_DIP_ENABLE_AVI;
 119	case HDMI_INFOFRAME_TYPE_SPD:
 120		return VIDEO_DIP_ENABLE_SPD;
 121	case HDMI_INFOFRAME_TYPE_VENDOR:
 122		return VIDEO_DIP_ENABLE_VENDOR;
 123	case HDMI_INFOFRAME_TYPE_DRM:
 124		return 0;
 125	default:
 126		MISSING_CASE(type);
 127		return 0;
 128	}
 129}
 130
 131static u32 hsw_infoframe_enable(unsigned int type)
 132{
 133	switch (type) {
 134	case HDMI_PACKET_TYPE_GENERAL_CONTROL:
 135		return VIDEO_DIP_ENABLE_GCP_HSW;
 136	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 137		return VIDEO_DIP_ENABLE_GMP_HSW;
 138	case DP_SDP_VSC:
 139		return VIDEO_DIP_ENABLE_VSC_HSW;
 140	case DP_SDP_PPS:
 141		return VDIP_ENABLE_PPS;
 142	case HDMI_INFOFRAME_TYPE_AVI:
 143		return VIDEO_DIP_ENABLE_AVI_HSW;
 144	case HDMI_INFOFRAME_TYPE_SPD:
 145		return VIDEO_DIP_ENABLE_SPD_HSW;
 146	case HDMI_INFOFRAME_TYPE_VENDOR:
 147		return VIDEO_DIP_ENABLE_VS_HSW;
 148	case HDMI_INFOFRAME_TYPE_DRM:
 149		return VIDEO_DIP_ENABLE_DRM_GLK;
 150	default:
 151		MISSING_CASE(type);
 152		return 0;
 153	}
 154}
 155
 156static i915_reg_t
 157hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 158		 enum transcoder cpu_transcoder,
 159		 unsigned int type,
 160		 int i)
 161{
 162	switch (type) {
 163	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 164		return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i);
 165	case DP_SDP_VSC:
 166		return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
 167	case DP_SDP_PPS:
 168		return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i);
 169	case HDMI_INFOFRAME_TYPE_AVI:
 170		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
 171	case HDMI_INFOFRAME_TYPE_SPD:
 172		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 173	case HDMI_INFOFRAME_TYPE_VENDOR:
 174		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
 175	case HDMI_INFOFRAME_TYPE_DRM:
 176		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 177	default:
 178		MISSING_CASE(type);
 179		return INVALID_MMIO_REG;
 180	}
 181}
 182
 183static int hsw_dip_data_size(struct drm_i915_private *dev_priv,
 184			     unsigned int type)
 185{
 186	switch (type) {
 187	case DP_SDP_VSC:
 188		return VIDEO_DIP_VSC_DATA_SIZE;
 189	case DP_SDP_PPS:
 190		return VIDEO_DIP_PPS_DATA_SIZE;
 191	case HDMI_PACKET_TYPE_GAMUT_METADATA:
 192		if (DISPLAY_VER(dev_priv) >= 11)
 193			return VIDEO_DIP_GMP_DATA_SIZE;
 194		else
 195			return VIDEO_DIP_DATA_SIZE;
 196	default:
 197		return VIDEO_DIP_DATA_SIZE;
 198	}
 199}
 200
 201static void g4x_write_infoframe(struct intel_encoder *encoder,
 202				const struct intel_crtc_state *crtc_state,
 203				unsigned int type,
 204				const void *frame, ssize_t len)
 205{
 206	const u32 *data = frame;
 207	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 208	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 209	int i;
 210
 211	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 212		 "Writing DIP with CTL reg disabled\n");
 213
 214	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 215	val |= g4x_infoframe_index(type);
 216
 217	val &= ~g4x_infoframe_enable(type);
 218
 219	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 220
 221	for (i = 0; i < len; i += 4) {
 222		intel_de_write(dev_priv, VIDEO_DIP_DATA, *data);
 223		data++;
 224	}
 225	/* Write every possible data byte to force correct ECC calculation. */
 226	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 227		intel_de_write(dev_priv, VIDEO_DIP_DATA, 0);
 228
 229	val |= g4x_infoframe_enable(type);
 230	val &= ~VIDEO_DIP_FREQ_MASK;
 231	val |= VIDEO_DIP_FREQ_VSYNC;
 232
 233	intel_de_write(dev_priv, VIDEO_DIP_CTL, val);
 234	intel_de_posting_read(dev_priv, VIDEO_DIP_CTL);
 235}
 236
 237static void g4x_read_infoframe(struct intel_encoder *encoder,
 238			       const struct intel_crtc_state *crtc_state,
 239			       unsigned int type,
 240			       void *frame, ssize_t len)
 241{
 242	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 243	u32 *data = frame;
 244	int i;
 245
 246	intel_de_rmw(dev_priv, VIDEO_DIP_CTL,
 247		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 248
 249	for (i = 0; i < len; i += 4)
 250		*data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA);
 251}
 252
 253static u32 g4x_infoframes_enabled(struct intel_encoder *encoder,
 254				  const struct intel_crtc_state *pipe_config)
 255{
 256	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 257	u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL);
 258
 259	if ((val & VIDEO_DIP_ENABLE) == 0)
 260		return 0;
 261
 262	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 263		return 0;
 264
 265	return val & (VIDEO_DIP_ENABLE_AVI |
 266		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 267}
 268
 269static void ibx_write_infoframe(struct intel_encoder *encoder,
 270				const struct intel_crtc_state *crtc_state,
 271				unsigned int type,
 272				const void *frame, ssize_t len)
 273{
 274	const u32 *data = frame;
 275	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 276	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 277	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 278	u32 val = intel_de_read(dev_priv, reg);
 279	int i;
 280
 281	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 282		 "Writing DIP with CTL reg disabled\n");
 283
 284	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 285	val |= g4x_infoframe_index(type);
 286
 287	val &= ~g4x_infoframe_enable(type);
 288
 289	intel_de_write(dev_priv, reg, val);
 290
 291	for (i = 0; i < len; i += 4) {
 292		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 293			       *data);
 294		data++;
 295	}
 296	/* Write every possible data byte to force correct ECC calculation. */
 297	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 298		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 299
 300	val |= g4x_infoframe_enable(type);
 301	val &= ~VIDEO_DIP_FREQ_MASK;
 302	val |= VIDEO_DIP_FREQ_VSYNC;
 303
 304	intel_de_write(dev_priv, reg, val);
 305	intel_de_posting_read(dev_priv, reg);
 306}
 307
 308static void ibx_read_infoframe(struct intel_encoder *encoder,
 309			       const struct intel_crtc_state *crtc_state,
 310			       unsigned int type,
 311			       void *frame, ssize_t len)
 312{
 313	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 314	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 315	u32 *data = frame;
 316	int i;
 317
 318	intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
 319		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 320
 321	for (i = 0; i < len; i += 4)
 322		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 323}
 324
 325static u32 ibx_infoframes_enabled(struct intel_encoder *encoder,
 326				  const struct intel_crtc_state *pipe_config)
 327{
 328	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 329	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 330	i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
 331	u32 val = intel_de_read(dev_priv, reg);
 332
 333	if ((val & VIDEO_DIP_ENABLE) == 0)
 334		return 0;
 335
 336	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 337		return 0;
 338
 339	return val & (VIDEO_DIP_ENABLE_AVI |
 340		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 341		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 342}
 343
 344static void cpt_write_infoframe(struct intel_encoder *encoder,
 345				const struct intel_crtc_state *crtc_state,
 346				unsigned int type,
 347				const void *frame, ssize_t len)
 348{
 349	const u32 *data = frame;
 350	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 351	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 352	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
 353	u32 val = intel_de_read(dev_priv, reg);
 354	int i;
 355
 356	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 357		 "Writing DIP with CTL reg disabled\n");
 358
 359	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 360	val |= g4x_infoframe_index(type);
 361
 362	/* The DIP control register spec says that we need to update the AVI
 363	 * infoframe without clearing its enable bit */
 364	if (type != HDMI_INFOFRAME_TYPE_AVI)
 365		val &= ~g4x_infoframe_enable(type);
 366
 367	intel_de_write(dev_priv, reg, val);
 368
 369	for (i = 0; i < len; i += 4) {
 370		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe),
 371			       *data);
 372		data++;
 373	}
 374	/* Write every possible data byte to force correct ECC calculation. */
 375	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 376		intel_de_write(dev_priv, TVIDEO_DIP_DATA(crtc->pipe), 0);
 377
 378	val |= g4x_infoframe_enable(type);
 379	val &= ~VIDEO_DIP_FREQ_MASK;
 380	val |= VIDEO_DIP_FREQ_VSYNC;
 381
 382	intel_de_write(dev_priv, reg, val);
 383	intel_de_posting_read(dev_priv, reg);
 384}
 385
 386static void cpt_read_infoframe(struct intel_encoder *encoder,
 387			       const struct intel_crtc_state *crtc_state,
 388			       unsigned int type,
 389			       void *frame, ssize_t len)
 390{
 391	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 392	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 393	u32 *data = frame;
 394	int i;
 395
 396	intel_de_rmw(dev_priv, TVIDEO_DIP_CTL(crtc->pipe),
 397		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 398
 399	for (i = 0; i < len; i += 4)
 400		*data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe));
 401}
 402
 403static u32 cpt_infoframes_enabled(struct intel_encoder *encoder,
 404				  const struct intel_crtc_state *pipe_config)
 405{
 406	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 407	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 408	u32 val = intel_de_read(dev_priv, TVIDEO_DIP_CTL(pipe));
 409
 410	if ((val & VIDEO_DIP_ENABLE) == 0)
 411		return 0;
 412
 413	return val & (VIDEO_DIP_ENABLE_AVI |
 414		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 415		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 416}
 417
 418static void vlv_write_infoframe(struct intel_encoder *encoder,
 419				const struct intel_crtc_state *crtc_state,
 420				unsigned int type,
 421				const void *frame, ssize_t len)
 422{
 423	const u32 *data = frame;
 424	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 425	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 426	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
 427	u32 val = intel_de_read(dev_priv, reg);
 428	int i;
 429
 430	drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE),
 431		 "Writing DIP with CTL reg disabled\n");
 432
 433	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
 434	val |= g4x_infoframe_index(type);
 435
 436	val &= ~g4x_infoframe_enable(type);
 437
 438	intel_de_write(dev_priv, reg, val);
 439
 440	for (i = 0; i < len; i += 4) {
 441		intel_de_write(dev_priv,
 442			       VLV_TVIDEO_DIP_DATA(crtc->pipe), *data);
 443		data++;
 444	}
 445	/* Write every possible data byte to force correct ECC calculation. */
 446	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
 447		intel_de_write(dev_priv,
 448			       VLV_TVIDEO_DIP_DATA(crtc->pipe), 0);
 449
 450	val |= g4x_infoframe_enable(type);
 451	val &= ~VIDEO_DIP_FREQ_MASK;
 452	val |= VIDEO_DIP_FREQ_VSYNC;
 453
 454	intel_de_write(dev_priv, reg, val);
 455	intel_de_posting_read(dev_priv, reg);
 456}
 457
 458static void vlv_read_infoframe(struct intel_encoder *encoder,
 459			       const struct intel_crtc_state *crtc_state,
 460			       unsigned int type,
 461			       void *frame, ssize_t len)
 462{
 463	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 464	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 465	u32 *data = frame;
 466	int i;
 467
 468	intel_de_rmw(dev_priv, VLV_TVIDEO_DIP_CTL(crtc->pipe),
 469		     VIDEO_DIP_SELECT_MASK | 0xf, g4x_infoframe_index(type));
 470
 471	for (i = 0; i < len; i += 4)
 472		*data++ = intel_de_read(dev_priv,
 473				        VLV_TVIDEO_DIP_DATA(crtc->pipe));
 474}
 475
 476static u32 vlv_infoframes_enabled(struct intel_encoder *encoder,
 477				  const struct intel_crtc_state *pipe_config)
 478{
 479	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 480	enum pipe pipe = to_intel_crtc(pipe_config->uapi.crtc)->pipe;
 481	u32 val = intel_de_read(dev_priv, VLV_TVIDEO_DIP_CTL(pipe));
 482
 483	if ((val & VIDEO_DIP_ENABLE) == 0)
 484		return 0;
 485
 486	if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(encoder->port))
 487		return 0;
 488
 489	return val & (VIDEO_DIP_ENABLE_AVI |
 490		      VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
 491		      VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
 492}
 493
 494void hsw_write_infoframe(struct intel_encoder *encoder,
 495			 const struct intel_crtc_state *crtc_state,
 496			 unsigned int type,
 497			 const void *frame, ssize_t len)
 498{
 499	const u32 *data = frame;
 500	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 501	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 502	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
 503	int data_size;
 504	int i;
 505	u32 val = intel_de_read(dev_priv, ctl_reg);
 506
 507	data_size = hsw_dip_data_size(dev_priv, type);
 508
 509	drm_WARN_ON(&dev_priv->drm, len > data_size);
 510
 511	val &= ~hsw_infoframe_enable(type);
 512	intel_de_write(dev_priv, ctl_reg, val);
 513
 514	for (i = 0; i < len; i += 4) {
 515		intel_de_write(dev_priv,
 516			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 517			       *data);
 518		data++;
 519	}
 520	/* Write every possible data byte to force correct ECC calculation. */
 521	for (; i < data_size; i += 4)
 522		intel_de_write(dev_priv,
 523			       hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2),
 524			       0);
 525
 526	/* Wa_14013475917 */
 527	if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC))
 528		val |= hsw_infoframe_enable(type);
 529
 530	if (type == DP_SDP_VSC)
 531		val |= VSC_DIP_HW_DATA_SW_HEA;
 532
 
 533	intel_de_write(dev_priv, ctl_reg, val);
 534	intel_de_posting_read(dev_priv, ctl_reg);
 535}
 536
 537void hsw_read_infoframe(struct intel_encoder *encoder,
 538			const struct intel_crtc_state *crtc_state,
 539			unsigned int type, void *frame, ssize_t len)
 540{
 541	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 542	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 543	u32 *data = frame;
 544	int i;
 545
 546	for (i = 0; i < len; i += 4)
 547		*data++ = intel_de_read(dev_priv,
 548				        hsw_dip_data_reg(dev_priv, cpu_transcoder, type, i >> 2));
 549}
 550
 551static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 552				  const struct intel_crtc_state *pipe_config)
 553{
 554	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 555	u32 val = intel_de_read(dev_priv,
 556				HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
 557	u32 mask;
 558
 559	mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 560		VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
 561		VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
 562
 563	if (DISPLAY_VER(dev_priv) >= 10)
 564		mask |= VIDEO_DIP_ENABLE_DRM_GLK;
 565
 566	return val & mask;
 567}
 568
 569static const u8 infoframe_type_to_idx[] = {
 570	HDMI_PACKET_TYPE_GENERAL_CONTROL,
 571	HDMI_PACKET_TYPE_GAMUT_METADATA,
 572	DP_SDP_VSC,
 573	HDMI_INFOFRAME_TYPE_AVI,
 574	HDMI_INFOFRAME_TYPE_SPD,
 575	HDMI_INFOFRAME_TYPE_VENDOR,
 576	HDMI_INFOFRAME_TYPE_DRM,
 577};
 578
 579u32 intel_hdmi_infoframe_enable(unsigned int type)
 580{
 581	int i;
 582
 583	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 584		if (infoframe_type_to_idx[i] == type)
 585			return BIT(i);
 586	}
 587
 588	return 0;
 589}
 590
 591u32 intel_hdmi_infoframes_enabled(struct intel_encoder *encoder,
 592				  const struct intel_crtc_state *crtc_state)
 593{
 594	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 595	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 596	u32 val, ret = 0;
 597	int i;
 598
 599	val = dig_port->infoframes_enabled(encoder, crtc_state);
 600
 601	/* map from hardware bits to dip idx */
 602	for (i = 0; i < ARRAY_SIZE(infoframe_type_to_idx); i++) {
 603		unsigned int type = infoframe_type_to_idx[i];
 604
 605		if (HAS_DDI(dev_priv)) {
 606			if (val & hsw_infoframe_enable(type))
 607				ret |= BIT(i);
 608		} else {
 609			if (val & g4x_infoframe_enable(type))
 610				ret |= BIT(i);
 611		}
 612	}
 613
 614	return ret;
 615}
 616
 617/*
 618 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 619 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 620 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 621 * used for both technologies.
 622 *
 623 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 624 * DW1:       DB3       | DB2 | DB1 | DB0
 625 * DW2:       DB7       | DB6 | DB5 | DB4
 626 * DW3: ...
 627 *
 628 * (HB is Header Byte, DB is Data Byte)
 629 *
 630 * The hdmi pack() functions don't know about that hardware specific hole so we
 631 * trick them by giving an offset into the buffer and moving back the header
 632 * bytes by one.
 633 */
 634static void intel_write_infoframe(struct intel_encoder *encoder,
 635				  const struct intel_crtc_state *crtc_state,
 636				  enum hdmi_infoframe_type type,
 637				  const union hdmi_infoframe *frame)
 638{
 639	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 640	u8 buffer[VIDEO_DIP_DATA_SIZE];
 641	ssize_t len;
 642
 643	if ((crtc_state->infoframes.enable &
 644	     intel_hdmi_infoframe_enable(type)) == 0)
 645		return;
 646
 647	if (drm_WARN_ON(encoder->base.dev, frame->any.type != type))
 648		return;
 649
 650	/* see comment above for the reason for this offset */
 651	len = hdmi_infoframe_pack_only(frame, buffer + 1, sizeof(buffer) - 1);
 652	if (drm_WARN_ON(encoder->base.dev, len < 0))
 653		return;
 654
 655	/* Insert the 'hole' (see big comment above) at position 3 */
 656	memmove(&buffer[0], &buffer[1], 3);
 657	buffer[3] = 0;
 658	len++;
 659
 660	dig_port->write_infoframe(encoder, crtc_state, type, buffer, len);
 661}
 662
 663void intel_read_infoframe(struct intel_encoder *encoder,
 664			  const struct intel_crtc_state *crtc_state,
 665			  enum hdmi_infoframe_type type,
 666			  union hdmi_infoframe *frame)
 667{
 668	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 669	u8 buffer[VIDEO_DIP_DATA_SIZE];
 670	int ret;
 671
 672	if ((crtc_state->infoframes.enable &
 673	     intel_hdmi_infoframe_enable(type)) == 0)
 674		return;
 675
 676	dig_port->read_infoframe(encoder, crtc_state,
 677				       type, buffer, sizeof(buffer));
 678
 679	/* Fill the 'hole' (see big comment above) at position 3 */
 680	memmove(&buffer[1], &buffer[0], 3);
 681
 682	/* see comment above for the reason for this offset */
 683	ret = hdmi_infoframe_unpack(frame, buffer + 1, sizeof(buffer) - 1);
 684	if (ret) {
 685		drm_dbg_kms(encoder->base.dev,
 686			    "Failed to unpack infoframe type 0x%02x\n", type);
 687		return;
 688	}
 689
 690	if (frame->any.type != type)
 691		drm_dbg_kms(encoder->base.dev,
 692			    "Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
 693			    frame->any.type, type);
 694}
 695
 696static bool
 697intel_hdmi_compute_avi_infoframe(struct intel_encoder *encoder,
 698				 struct intel_crtc_state *crtc_state,
 699				 struct drm_connector_state *conn_state)
 700{
 701	struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
 702	const struct drm_display_mode *adjusted_mode =
 703		&crtc_state->hw.adjusted_mode;
 704	struct drm_connector *connector = conn_state->connector;
 705	int ret;
 706
 707	if (!crtc_state->has_infoframe)
 708		return true;
 709
 710	crtc_state->infoframes.enable |=
 711		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
 712
 713	ret = drm_hdmi_avi_infoframe_from_display_mode(frame, connector,
 714						       adjusted_mode);
 715	if (ret)
 716		return false;
 717
 718	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
 719		frame->colorspace = HDMI_COLORSPACE_YUV420;
 720	else if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 721		frame->colorspace = HDMI_COLORSPACE_YUV444;
 722	else
 723		frame->colorspace = HDMI_COLORSPACE_RGB;
 724
 725	drm_hdmi_avi_infoframe_colorimetry(frame, conn_state);
 726
 727	/* nonsense combination */
 728	drm_WARN_ON(encoder->base.dev, crtc_state->limited_color_range &&
 729		    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 730
 731	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) {
 732		drm_hdmi_avi_infoframe_quant_range(frame, connector,
 733						   adjusted_mode,
 734						   crtc_state->limited_color_range ?
 735						   HDMI_QUANTIZATION_RANGE_LIMITED :
 736						   HDMI_QUANTIZATION_RANGE_FULL);
 737	} else {
 738		frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
 739		frame->ycc_quantization_range = HDMI_YCC_QUANTIZATION_RANGE_LIMITED;
 740	}
 741
 742	drm_hdmi_avi_infoframe_content_type(frame, conn_state);
 743
 744	/* TODO: handle pixel repetition for YCBCR420 outputs */
 745
 746	ret = hdmi_avi_infoframe_check(frame);
 747	if (drm_WARN_ON(encoder->base.dev, ret))
 748		return false;
 749
 750	return true;
 751}
 752
 753static bool
 754intel_hdmi_compute_spd_infoframe(struct intel_encoder *encoder,
 755				 struct intel_crtc_state *crtc_state,
 756				 struct drm_connector_state *conn_state)
 757{
 758	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 759	struct hdmi_spd_infoframe *frame = &crtc_state->infoframes.spd.spd;
 760	int ret;
 761
 762	if (!crtc_state->has_infoframe)
 763		return true;
 764
 765	crtc_state->infoframes.enable |=
 766		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_SPD);
 767
 768	if (IS_DGFX(i915))
 769		ret = hdmi_spd_infoframe_init(frame, "Intel", "Discrete gfx");
 770	else
 771		ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx");
 772
 773	if (drm_WARN_ON(encoder->base.dev, ret))
 774		return false;
 775
 776	frame->sdi = HDMI_SPD_SDI_PC;
 777
 778	ret = hdmi_spd_infoframe_check(frame);
 779	if (drm_WARN_ON(encoder->base.dev, ret))
 780		return false;
 781
 782	return true;
 783}
 784
 785static bool
 786intel_hdmi_compute_hdmi_infoframe(struct intel_encoder *encoder,
 787				  struct intel_crtc_state *crtc_state,
 788				  struct drm_connector_state *conn_state)
 789{
 790	struct hdmi_vendor_infoframe *frame =
 791		&crtc_state->infoframes.hdmi.vendor.hdmi;
 792	const struct drm_display_info *info =
 793		&conn_state->connector->display_info;
 794	int ret;
 795
 796	if (!crtc_state->has_infoframe || !info->has_hdmi_infoframe)
 797		return true;
 798
 799	crtc_state->infoframes.enable |=
 800		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_VENDOR);
 801
 802	ret = drm_hdmi_vendor_infoframe_from_display_mode(frame,
 803							  conn_state->connector,
 804							  &crtc_state->hw.adjusted_mode);
 805	if (drm_WARN_ON(encoder->base.dev, ret))
 806		return false;
 807
 808	ret = hdmi_vendor_infoframe_check(frame);
 809	if (drm_WARN_ON(encoder->base.dev, ret))
 810		return false;
 811
 812	return true;
 813}
 814
 815static bool
 816intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder,
 817				 struct intel_crtc_state *crtc_state,
 818				 struct drm_connector_state *conn_state)
 819{
 820	struct hdmi_drm_infoframe *frame = &crtc_state->infoframes.drm.drm;
 821	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 822	int ret;
 823
 824	if (DISPLAY_VER(dev_priv) < 10)
 825		return true;
 826
 827	if (!crtc_state->has_infoframe)
 828		return true;
 829
 830	if (!conn_state->hdr_output_metadata)
 831		return true;
 832
 833	crtc_state->infoframes.enable |=
 834		intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_DRM);
 835
 836	ret = drm_hdmi_infoframe_set_hdr_metadata(frame, conn_state);
 837	if (ret < 0) {
 838		drm_dbg_kms(&dev_priv->drm,
 839			    "couldn't set HDR metadata in infoframe\n");
 840		return false;
 841	}
 842
 843	ret = hdmi_drm_infoframe_check(frame);
 844	if (drm_WARN_ON(&dev_priv->drm, ret))
 845		return false;
 846
 847	return true;
 848}
 849
 850static void g4x_set_infoframes(struct intel_encoder *encoder,
 851			       bool enable,
 852			       const struct intel_crtc_state *crtc_state,
 853			       const struct drm_connector_state *conn_state)
 854{
 855	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 856	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 857	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
 858	i915_reg_t reg = VIDEO_DIP_CTL;
 859	u32 val = intel_de_read(dev_priv, reg);
 860	u32 port = VIDEO_DIP_PORT(encoder->port);
 861
 862	assert_hdmi_port_disabled(intel_hdmi);
 863
 864	/* If the registers were not initialized yet, they might be zeroes,
 865	 * which means we're selecting the AVI DIP and we're setting its
 866	 * frequency to once. This seems to really confuse the HW and make
 867	 * things stop working (the register spec says the AVI always needs to
 868	 * be sent every VSync). So here we avoid writing to the register more
 869	 * than we need and also explicitly select the AVI DIP and explicitly
 870	 * set its frequency to every VSync. Avoiding to write it twice seems to
 871	 * be enough to solve the problem, but being defensive shouldn't hurt us
 872	 * either. */
 873	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
 874
 875	if (!enable) {
 876		if (!(val & VIDEO_DIP_ENABLE))
 877			return;
 878		if (port != (val & VIDEO_DIP_PORT_MASK)) {
 879			drm_dbg_kms(&dev_priv->drm,
 880				    "video DIP still enabled on port %c\n",
 881				    (val & VIDEO_DIP_PORT_MASK) >> 29);
 882			return;
 883		}
 884		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
 885			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 886		intel_de_write(dev_priv, reg, val);
 887		intel_de_posting_read(dev_priv, reg);
 888		return;
 889	}
 890
 891	if (port != (val & VIDEO_DIP_PORT_MASK)) {
 892		if (val & VIDEO_DIP_ENABLE) {
 893			drm_dbg_kms(&dev_priv->drm,
 894				    "video DIP already enabled on port %c\n",
 895				    (val & VIDEO_DIP_PORT_MASK) >> 29);
 896			return;
 897		}
 898		val &= ~VIDEO_DIP_PORT_MASK;
 899		val |= port;
 900	}
 901
 902	val |= VIDEO_DIP_ENABLE;
 903	val &= ~(VIDEO_DIP_ENABLE_AVI |
 904		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
 905
 906	intel_de_write(dev_priv, reg, val);
 907	intel_de_posting_read(dev_priv, reg);
 908
 909	intel_write_infoframe(encoder, crtc_state,
 910			      HDMI_INFOFRAME_TYPE_AVI,
 911			      &crtc_state->infoframes.avi);
 912	intel_write_infoframe(encoder, crtc_state,
 913			      HDMI_INFOFRAME_TYPE_SPD,
 914			      &crtc_state->infoframes.spd);
 915	intel_write_infoframe(encoder, crtc_state,
 916			      HDMI_INFOFRAME_TYPE_VENDOR,
 917			      &crtc_state->infoframes.hdmi);
 918}
 919
 920/*
 921 * Determine if default_phase=1 can be indicated in the GCP infoframe.
 922 *
 923 * From HDMI specification 1.4a:
 924 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
 925 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
 926 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
 927 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
 928 *   phase of 0
 929 */
 930static bool gcp_default_phase_possible(int pipe_bpp,
 931				       const struct drm_display_mode *mode)
 932{
 933	unsigned int pixels_per_group;
 934
 935	switch (pipe_bpp) {
 936	case 30:
 937		/* 4 pixels in 5 clocks */
 938		pixels_per_group = 4;
 939		break;
 940	case 36:
 941		/* 2 pixels in 3 clocks */
 942		pixels_per_group = 2;
 943		break;
 944	case 48:
 945		/* 1 pixel in 2 clocks */
 946		pixels_per_group = 1;
 947		break;
 948	default:
 949		/* phase information not relevant for 8bpc */
 950		return false;
 951	}
 952
 953	return mode->crtc_hdisplay % pixels_per_group == 0 &&
 954		mode->crtc_htotal % pixels_per_group == 0 &&
 955		mode->crtc_hblank_start % pixels_per_group == 0 &&
 956		mode->crtc_hblank_end % pixels_per_group == 0 &&
 957		mode->crtc_hsync_start % pixels_per_group == 0 &&
 958		mode->crtc_hsync_end % pixels_per_group == 0 &&
 959		((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
 960		 mode->crtc_htotal/2 % pixels_per_group == 0);
 961}
 962
 963static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder,
 964					 const struct intel_crtc_state *crtc_state,
 965					 const struct drm_connector_state *conn_state)
 966{
 967	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 968	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 969	i915_reg_t reg;
 970
 971	if ((crtc_state->infoframes.enable &
 972	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 973		return false;
 974
 975	if (HAS_DDI(dev_priv))
 976		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
 977	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 978		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
 979	else if (HAS_PCH_SPLIT(dev_priv))
 980		reg = TVIDEO_DIP_GCP(crtc->pipe);
 981	else
 982		return false;
 983
 984	intel_de_write(dev_priv, reg, crtc_state->infoframes.gcp);
 985
 986	return true;
 987}
 988
 989void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder,
 990				   struct intel_crtc_state *crtc_state)
 991{
 992	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 993	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 994	i915_reg_t reg;
 995
 996	if ((crtc_state->infoframes.enable &
 997	     intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL)) == 0)
 998		return;
 999
1000	if (HAS_DDI(dev_priv))
1001		reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
1002	else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1003		reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
1004	else if (HAS_PCH_SPLIT(dev_priv))
1005		reg = TVIDEO_DIP_GCP(crtc->pipe);
1006	else
1007		return;
1008
1009	crtc_state->infoframes.gcp = intel_de_read(dev_priv, reg);
1010}
1011
1012static void intel_hdmi_compute_gcp_infoframe(struct intel_encoder *encoder,
1013					     struct intel_crtc_state *crtc_state,
1014					     struct drm_connector_state *conn_state)
1015{
1016	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1017
1018	if (IS_G4X(dev_priv) || !crtc_state->has_infoframe)
1019		return;
1020
1021	crtc_state->infoframes.enable |=
1022		intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GENERAL_CONTROL);
1023
1024	/* Indicate color indication for deep color mode */
1025	if (crtc_state->pipe_bpp > 24)
1026		crtc_state->infoframes.gcp |= GCP_COLOR_INDICATION;
1027
1028	/* Enable default_phase whenever the display mode is suitably aligned */
1029	if (gcp_default_phase_possible(crtc_state->pipe_bpp,
1030				       &crtc_state->hw.adjusted_mode))
1031		crtc_state->infoframes.gcp |= GCP_DEFAULT_PHASE_ENABLE;
1032}
1033
1034static void ibx_set_infoframes(struct intel_encoder *encoder,
1035			       bool enable,
1036			       const struct intel_crtc_state *crtc_state,
1037			       const struct drm_connector_state *conn_state)
1038{
1039	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1040	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1041	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1042	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
1043	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1044	u32 val = intel_de_read(dev_priv, reg);
1045	u32 port = VIDEO_DIP_PORT(encoder->port);
1046
1047	assert_hdmi_port_disabled(intel_hdmi);
1048
1049	/* See the big comment in g4x_set_infoframes() */
1050	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1051
1052	if (!enable) {
1053		if (!(val & VIDEO_DIP_ENABLE))
1054			return;
1055		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1056			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1057			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1058		intel_de_write(dev_priv, reg, val);
1059		intel_de_posting_read(dev_priv, reg);
1060		return;
1061	}
1062
1063	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1064		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1065			 "DIP already enabled on port %c\n",
1066			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1067		val &= ~VIDEO_DIP_PORT_MASK;
1068		val |= port;
1069	}
1070
1071	val |= VIDEO_DIP_ENABLE;
1072	val &= ~(VIDEO_DIP_ENABLE_AVI |
1073		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1074		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1075
1076	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1077		val |= VIDEO_DIP_ENABLE_GCP;
1078
1079	intel_de_write(dev_priv, reg, val);
1080	intel_de_posting_read(dev_priv, reg);
1081
1082	intel_write_infoframe(encoder, crtc_state,
1083			      HDMI_INFOFRAME_TYPE_AVI,
1084			      &crtc_state->infoframes.avi);
1085	intel_write_infoframe(encoder, crtc_state,
1086			      HDMI_INFOFRAME_TYPE_SPD,
1087			      &crtc_state->infoframes.spd);
1088	intel_write_infoframe(encoder, crtc_state,
1089			      HDMI_INFOFRAME_TYPE_VENDOR,
1090			      &crtc_state->infoframes.hdmi);
1091}
1092
1093static void cpt_set_infoframes(struct intel_encoder *encoder,
1094			       bool enable,
1095			       const struct intel_crtc_state *crtc_state,
1096			       const struct drm_connector_state *conn_state)
1097{
1098	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1099	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1100	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1101	i915_reg_t reg = TVIDEO_DIP_CTL(crtc->pipe);
1102	u32 val = intel_de_read(dev_priv, reg);
1103
1104	assert_hdmi_port_disabled(intel_hdmi);
1105
1106	/* See the big comment in g4x_set_infoframes() */
1107	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1108
1109	if (!enable) {
1110		if (!(val & VIDEO_DIP_ENABLE))
1111			return;
1112		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1113			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1114			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1115		intel_de_write(dev_priv, reg, val);
1116		intel_de_posting_read(dev_priv, reg);
1117		return;
1118	}
1119
1120	/* Set both together, unset both together: see the spec. */
1121	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
1122	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1123		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1124
1125	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1126		val |= VIDEO_DIP_ENABLE_GCP;
1127
1128	intel_de_write(dev_priv, reg, val);
1129	intel_de_posting_read(dev_priv, reg);
1130
1131	intel_write_infoframe(encoder, crtc_state,
1132			      HDMI_INFOFRAME_TYPE_AVI,
1133			      &crtc_state->infoframes.avi);
1134	intel_write_infoframe(encoder, crtc_state,
1135			      HDMI_INFOFRAME_TYPE_SPD,
1136			      &crtc_state->infoframes.spd);
1137	intel_write_infoframe(encoder, crtc_state,
1138			      HDMI_INFOFRAME_TYPE_VENDOR,
1139			      &crtc_state->infoframes.hdmi);
1140}
1141
1142static void vlv_set_infoframes(struct intel_encoder *encoder,
1143			       bool enable,
1144			       const struct intel_crtc_state *crtc_state,
1145			       const struct drm_connector_state *conn_state)
1146{
1147	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1148	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1149	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1150	i915_reg_t reg = VLV_TVIDEO_DIP_CTL(crtc->pipe);
1151	u32 val = intel_de_read(dev_priv, reg);
1152	u32 port = VIDEO_DIP_PORT(encoder->port);
1153
1154	assert_hdmi_port_disabled(intel_hdmi);
1155
1156	/* See the big comment in g4x_set_infoframes() */
1157	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
1158
1159	if (!enable) {
1160		if (!(val & VIDEO_DIP_ENABLE))
1161			return;
1162		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
1163			 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1164			 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1165		intel_de_write(dev_priv, reg, val);
1166		intel_de_posting_read(dev_priv, reg);
1167		return;
1168	}
1169
1170	if (port != (val & VIDEO_DIP_PORT_MASK)) {
1171		drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE,
1172			 "DIP already enabled on port %c\n",
1173			 (val & VIDEO_DIP_PORT_MASK) >> 29);
1174		val &= ~VIDEO_DIP_PORT_MASK;
1175		val |= port;
1176	}
1177
1178	val |= VIDEO_DIP_ENABLE;
1179	val &= ~(VIDEO_DIP_ENABLE_AVI |
1180		 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
1181		 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
1182
1183	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1184		val |= VIDEO_DIP_ENABLE_GCP;
1185
1186	intel_de_write(dev_priv, reg, val);
1187	intel_de_posting_read(dev_priv, reg);
1188
1189	intel_write_infoframe(encoder, crtc_state,
1190			      HDMI_INFOFRAME_TYPE_AVI,
1191			      &crtc_state->infoframes.avi);
1192	intel_write_infoframe(encoder, crtc_state,
1193			      HDMI_INFOFRAME_TYPE_SPD,
1194			      &crtc_state->infoframes.spd);
1195	intel_write_infoframe(encoder, crtc_state,
1196			      HDMI_INFOFRAME_TYPE_VENDOR,
1197			      &crtc_state->infoframes.hdmi);
1198}
1199
1200static void hsw_set_infoframes(struct intel_encoder *encoder,
1201			       bool enable,
1202			       const struct intel_crtc_state *crtc_state,
1203			       const struct drm_connector_state *conn_state)
1204{
1205	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1206	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
1207	u32 val = intel_de_read(dev_priv, reg);
1208
1209	assert_hdmi_transcoder_func_disabled(dev_priv,
1210					     crtc_state->cpu_transcoder);
1211
1212	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
1213		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
1214		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
1215		 VIDEO_DIP_ENABLE_DRM_GLK);
1216
1217	if (!enable) {
1218		intel_de_write(dev_priv, reg, val);
1219		intel_de_posting_read(dev_priv, reg);
1220		return;
1221	}
1222
1223	if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
1224		val |= VIDEO_DIP_ENABLE_GCP_HSW;
1225
1226	intel_de_write(dev_priv, reg, val);
1227	intel_de_posting_read(dev_priv, reg);
1228
1229	intel_write_infoframe(encoder, crtc_state,
1230			      HDMI_INFOFRAME_TYPE_AVI,
1231			      &crtc_state->infoframes.avi);
1232	intel_write_infoframe(encoder, crtc_state,
1233			      HDMI_INFOFRAME_TYPE_SPD,
1234			      &crtc_state->infoframes.spd);
1235	intel_write_infoframe(encoder, crtc_state,
1236			      HDMI_INFOFRAME_TYPE_VENDOR,
1237			      &crtc_state->infoframes.hdmi);
1238	intel_write_infoframe(encoder, crtc_state,
1239			      HDMI_INFOFRAME_TYPE_DRM,
1240			      &crtc_state->infoframes.drm);
1241}
1242
1243void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
1244{
1245	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1246	struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1247
1248	if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
1249		return;
1250
1251	drm_dbg_kms(&dev_priv->drm, "%s DP dual mode adaptor TMDS output\n",
1252		    enable ? "Enabling" : "Disabling");
1253
1254	drm_dp_dual_mode_set_tmds_output(&dev_priv->drm,
1255					 hdmi->dp_dual_mode.type, ddc, enable);
1256}
1257
1258static int intel_hdmi_hdcp_read(struct intel_digital_port *dig_port,
1259				unsigned int offset, void *buffer, size_t size)
1260{
1261	struct intel_hdmi *hdmi = &dig_port->hdmi;
1262	struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1263	int ret;
1264	u8 start = offset & 0xff;
1265	struct i2c_msg msgs[] = {
1266		{
1267			.addr = DRM_HDCP_DDC_ADDR,
1268			.flags = 0,
1269			.len = 1,
1270			.buf = &start,
1271		},
1272		{
1273			.addr = DRM_HDCP_DDC_ADDR,
1274			.flags = I2C_M_RD,
1275			.len = size,
1276			.buf = buffer
1277		}
1278	};
1279	ret = i2c_transfer(ddc, msgs, ARRAY_SIZE(msgs));
1280	if (ret == ARRAY_SIZE(msgs))
1281		return 0;
1282	return ret >= 0 ? -EIO : ret;
1283}
1284
1285static int intel_hdmi_hdcp_write(struct intel_digital_port *dig_port,
1286				 unsigned int offset, void *buffer, size_t size)
1287{
1288	struct intel_hdmi *hdmi = &dig_port->hdmi;
1289	struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1290	int ret;
1291	u8 *write_buf;
1292	struct i2c_msg msg;
1293
1294	write_buf = kzalloc(size + 1, GFP_KERNEL);
1295	if (!write_buf)
1296		return -ENOMEM;
1297
1298	write_buf[0] = offset & 0xff;
1299	memcpy(&write_buf[1], buffer, size);
1300
1301	msg.addr = DRM_HDCP_DDC_ADDR;
1302	msg.flags = 0,
1303	msg.len = size + 1,
1304	msg.buf = write_buf;
1305
1306	ret = i2c_transfer(ddc, &msg, 1);
1307	if (ret == 1)
1308		ret = 0;
1309	else if (ret >= 0)
1310		ret = -EIO;
1311
1312	kfree(write_buf);
1313	return ret;
1314}
1315
1316static
1317int intel_hdmi_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
1318				  u8 *an)
1319{
1320	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1321	struct intel_hdmi *hdmi = &dig_port->hdmi;
1322	struct i2c_adapter *ddc = hdmi->attached_connector->base.ddc;
1323	int ret;
1324
1325	ret = intel_hdmi_hdcp_write(dig_port, DRM_HDCP_DDC_AN, an,
1326				    DRM_HDCP_AN_LEN);
1327	if (ret) {
1328		drm_dbg_kms(&i915->drm, "Write An over DDC failed (%d)\n",
1329			    ret);
1330		return ret;
1331	}
1332
1333	ret = intel_gmbus_output_aksv(ddc);
1334	if (ret < 0) {
1335		drm_dbg_kms(&i915->drm, "Failed to output aksv (%d)\n", ret);
1336		return ret;
1337	}
1338	return 0;
1339}
1340
1341static int intel_hdmi_hdcp_read_bksv(struct intel_digital_port *dig_port,
1342				     u8 *bksv)
1343{
1344	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1345
1346	int ret;
1347	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BKSV, bksv,
1348				   DRM_HDCP_KSV_LEN);
1349	if (ret)
1350		drm_dbg_kms(&i915->drm, "Read Bksv over DDC failed (%d)\n",
1351			    ret);
1352	return ret;
1353}
1354
1355static
1356int intel_hdmi_hdcp_read_bstatus(struct intel_digital_port *dig_port,
1357				 u8 *bstatus)
1358{
1359	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1360
1361	int ret;
1362	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BSTATUS,
1363				   bstatus, DRM_HDCP_BSTATUS_LEN);
1364	if (ret)
1365		drm_dbg_kms(&i915->drm, "Read bstatus over DDC failed (%d)\n",
1366			    ret);
1367	return ret;
1368}
1369
1370static
1371int intel_hdmi_hdcp_repeater_present(struct intel_digital_port *dig_port,
1372				     bool *repeater_present)
1373{
1374	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1375	int ret;
1376	u8 val;
1377
1378	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1379	if (ret) {
1380		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1381			    ret);
1382		return ret;
1383	}
1384	*repeater_present = val & DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT;
1385	return 0;
1386}
1387
1388static
1389int intel_hdmi_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
1390				  u8 *ri_prime)
1391{
1392	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1393
1394	int ret;
1395	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_RI_PRIME,
1396				   ri_prime, DRM_HDCP_RI_LEN);
1397	if (ret)
1398		drm_dbg_kms(&i915->drm, "Read Ri' over DDC failed (%d)\n",
1399			    ret);
1400	return ret;
1401}
1402
1403static
1404int intel_hdmi_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
1405				   bool *ksv_ready)
1406{
1407	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1408	int ret;
1409	u8 val;
1410
1411	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_BCAPS, &val, 1);
1412	if (ret) {
1413		drm_dbg_kms(&i915->drm, "Read bcaps over DDC failed (%d)\n",
1414			    ret);
1415		return ret;
1416	}
1417	*ksv_ready = val & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY;
1418	return 0;
1419}
1420
1421static
1422int intel_hdmi_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
1423				  int num_downstream, u8 *ksv_fifo)
1424{
1425	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1426	int ret;
1427	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_KSV_FIFO,
1428				   ksv_fifo, num_downstream * DRM_HDCP_KSV_LEN);
1429	if (ret) {
1430		drm_dbg_kms(&i915->drm,
1431			    "Read ksv fifo over DDC failed (%d)\n", ret);
1432		return ret;
1433	}
1434	return 0;
1435}
1436
1437static
1438int intel_hdmi_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
1439				      int i, u32 *part)
1440{
1441	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1442	int ret;
1443
1444	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
1445		return -EINVAL;
1446
1447	ret = intel_hdmi_hdcp_read(dig_port, DRM_HDCP_DDC_V_PRIME(i),
1448				   part, DRM_HDCP_V_PRIME_PART_LEN);
1449	if (ret)
1450		drm_dbg_kms(&i915->drm, "Read V'[%d] over DDC failed (%d)\n",
1451			    i, ret);
1452	return ret;
1453}
1454
1455static int kbl_repositioning_enc_en_signal(struct intel_connector *connector,
1456					   enum transcoder cpu_transcoder)
1457{
1458	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1459	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1460	struct intel_crtc *crtc = to_intel_crtc(connector->base.state->crtc);
1461	u32 scanline;
1462	int ret;
1463
1464	for (;;) {
1465		scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe));
1466		if (scanline > 100 && scanline < 200)
1467			break;
1468		usleep_range(25, 50);
1469	}
1470
1471	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1472					 false, TRANS_DDI_HDCP_SIGNALLING);
1473	if (ret) {
1474		drm_err(&dev_priv->drm,
1475			"Disable HDCP signalling failed (%d)\n", ret);
1476		return ret;
1477	}
1478
1479	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, cpu_transcoder,
1480					 true, TRANS_DDI_HDCP_SIGNALLING);
1481	if (ret) {
1482		drm_err(&dev_priv->drm,
1483			"Enable HDCP signalling failed (%d)\n", ret);
1484		return ret;
1485	}
1486
1487	return 0;
1488}
1489
1490static
1491int intel_hdmi_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
1492				      enum transcoder cpu_transcoder,
1493				      bool enable)
1494{
1495	struct intel_hdmi *hdmi = &dig_port->hdmi;
1496	struct intel_connector *connector = hdmi->attached_connector;
1497	struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1498	int ret;
1499
1500	if (!enable)
1501		usleep_range(6, 60); /* Bspec says >= 6us */
1502
1503	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
1504					 cpu_transcoder, enable,
1505					 TRANS_DDI_HDCP_SIGNALLING);
1506	if (ret) {
1507		drm_err(&dev_priv->drm, "%s HDCP signalling failed (%d)\n",
1508			enable ? "Enable" : "Disable", ret);
1509		return ret;
1510	}
1511
1512	/*
1513	 * WA: To fix incorrect positioning of the window of
1514	 * opportunity and enc_en signalling in KABYLAKE.
1515	 */
1516	if (IS_KABYLAKE(dev_priv) && enable)
1517		return kbl_repositioning_enc_en_signal(connector,
1518						       cpu_transcoder);
1519
1520	return 0;
1521}
1522
1523static
1524bool intel_hdmi_hdcp_check_link_once(struct intel_digital_port *dig_port,
1525				     struct intel_connector *connector)
1526{
1527	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1528	enum port port = dig_port->base.port;
1529	enum transcoder cpu_transcoder = connector->hdcp.cpu_transcoder;
1530	int ret;
1531	union {
1532		u32 reg;
1533		u8 shim[DRM_HDCP_RI_LEN];
1534	} ri;
1535
1536	ret = intel_hdmi_hdcp_read_ri_prime(dig_port, ri.shim);
1537	if (ret)
1538		return false;
1539
1540	intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
1541
1542	/* Wait for Ri prime match */
1543	if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
1544		      (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
1545		     (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
1546		drm_dbg_kms(&i915->drm, "Ri' mismatch detected (%x)\n",
1547			intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder,
1548							port)));
1549		return false;
1550	}
1551	return true;
1552}
1553
1554static
1555bool intel_hdmi_hdcp_check_link(struct intel_digital_port *dig_port,
1556				struct intel_connector *connector)
1557{
1558	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1559	int retry;
1560
1561	for (retry = 0; retry < 3; retry++)
1562		if (intel_hdmi_hdcp_check_link_once(dig_port, connector))
1563			return true;
1564
1565	drm_err(&i915->drm, "Link check failed\n");
1566	return false;
1567}
1568
1569struct hdcp2_hdmi_msg_timeout {
1570	u8 msg_id;
1571	u16 timeout;
1572};
1573
1574static const struct hdcp2_hdmi_msg_timeout hdcp2_msg_timeout[] = {
1575	{ HDCP_2_2_AKE_SEND_CERT, HDCP_2_2_CERT_TIMEOUT_MS, },
1576	{ HDCP_2_2_AKE_SEND_PAIRING_INFO, HDCP_2_2_PAIRING_TIMEOUT_MS, },
1577	{ HDCP_2_2_LC_SEND_LPRIME, HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS, },
1578	{ HDCP_2_2_REP_SEND_RECVID_LIST, HDCP_2_2_RECVID_LIST_TIMEOUT_MS, },
1579	{ HDCP_2_2_REP_STREAM_READY, HDCP_2_2_STREAM_READY_TIMEOUT_MS, },
1580};
1581
1582static
1583int intel_hdmi_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
1584				    u8 *rx_status)
1585{
1586	return intel_hdmi_hdcp_read(dig_port,
1587				    HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET,
1588				    rx_status,
1589				    HDCP_2_2_HDMI_RXSTATUS_LEN);
1590}
1591
1592static int get_hdcp2_msg_timeout(u8 msg_id, bool is_paired)
1593{
1594	int i;
1595
1596	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME) {
1597		if (is_paired)
1598			return HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS;
1599		else
1600			return HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS;
1601	}
1602
1603	for (i = 0; i < ARRAY_SIZE(hdcp2_msg_timeout); i++) {
1604		if (hdcp2_msg_timeout[i].msg_id == msg_id)
1605			return hdcp2_msg_timeout[i].timeout;
1606	}
1607
1608	return -EINVAL;
1609}
1610
1611static int
1612hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
1613			      u8 msg_id, bool *msg_ready,
1614			      ssize_t *msg_sz)
1615{
1616	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1617	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1618	int ret;
1619
1620	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1621	if (ret < 0) {
1622		drm_dbg_kms(&i915->drm, "rx_status read failed. Err %d\n",
1623			    ret);
1624		return ret;
1625	}
1626
1627	*msg_sz = ((HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(rx_status[1]) << 8) |
1628		  rx_status[0]);
1629
1630	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST)
1631		*msg_ready = (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]) &&
1632			     *msg_sz);
1633	else
1634		*msg_ready = *msg_sz;
1635
1636	return 0;
1637}
1638
1639static ssize_t
1640intel_hdmi_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
1641			      u8 msg_id, bool paired)
1642{
1643	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1644	bool msg_ready = false;
1645	int timeout, ret;
1646	ssize_t msg_sz = 0;
1647
1648	timeout = get_hdcp2_msg_timeout(msg_id, paired);
1649	if (timeout < 0)
1650		return timeout;
1651
1652	ret = __wait_for(ret = hdcp2_detect_msg_availability(dig_port,
1653							     msg_id, &msg_ready,
1654							     &msg_sz),
1655			 !ret && msg_ready && msg_sz, timeout * 1000,
1656			 1000, 5 * 1000);
1657	if (ret)
1658		drm_dbg_kms(&i915->drm, "msg_id: %d, ret: %d, timeout: %d\n",
1659			    msg_id, ret, timeout);
1660
1661	return ret ? ret : msg_sz;
1662}
1663
1664static
1665int intel_hdmi_hdcp2_write_msg(struct intel_connector *connector,
1666			       void *buf, size_t size)
1667{
1668	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1669	unsigned int offset;
1670
1671	offset = HDCP_2_2_HDMI_REG_WR_MSG_OFFSET;
1672	return intel_hdmi_hdcp_write(dig_port, offset, buf, size);
1673}
1674
1675static
1676int intel_hdmi_hdcp2_read_msg(struct intel_connector *connector,
1677			      u8 msg_id, void *buf, size_t size)
1678{
1679	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1680	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1681	struct intel_hdmi *hdmi = &dig_port->hdmi;
1682	struct intel_hdcp *hdcp = &hdmi->attached_connector->hdcp;
1683	unsigned int offset;
1684	ssize_t ret;
1685
1686	ret = intel_hdmi_hdcp2_wait_for_msg(dig_port, msg_id,
1687					    hdcp->is_paired);
1688	if (ret < 0)
1689		return ret;
1690
1691	/*
1692	 * Available msg size should be equal to or lesser than the
1693	 * available buffer.
1694	 */
1695	if (ret > size) {
1696		drm_dbg_kms(&i915->drm,
1697			    "msg_sz(%zd) is more than exp size(%zu)\n",
1698			    ret, size);
1699		return -EINVAL;
1700	}
1701
1702	offset = HDCP_2_2_HDMI_REG_RD_MSG_OFFSET;
1703	ret = intel_hdmi_hdcp_read(dig_port, offset, buf, ret);
1704	if (ret)
1705		drm_dbg_kms(&i915->drm, "Failed to read msg_id: %d(%zd)\n",
1706			    msg_id, ret);
1707
1708	return ret;
1709}
1710
1711static
1712int intel_hdmi_hdcp2_check_link(struct intel_digital_port *dig_port,
1713				struct intel_connector *connector)
1714{
1715	u8 rx_status[HDCP_2_2_HDMI_RXSTATUS_LEN];
1716	int ret;
1717
1718	ret = intel_hdmi_hdcp2_read_rx_status(dig_port, rx_status);
1719	if (ret)
1720		return ret;
1721
1722	/*
1723	 * Re-auth request and Link Integrity Failures are represented by
1724	 * same bit. i.e reauth_req.
1725	 */
1726	if (HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(rx_status[1]))
1727		ret = HDCP_REAUTH_REQUEST;
1728	else if (HDCP_2_2_HDMI_RXSTATUS_READY(rx_status[1]))
1729		ret = HDCP_TOPOLOGY_CHANGE;
1730
1731	return ret;
1732}
1733
1734static
1735int intel_hdmi_hdcp2_get_capability(struct intel_connector *connector,
1736				    bool *capable)
1737{
1738	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
1739	u8 hdcp2_version;
1740	int ret;
1741
1742	*capable = false;
1743	ret = intel_hdmi_hdcp_read(dig_port, HDCP_2_2_HDMI_REG_VER_OFFSET,
1744				   &hdcp2_version, sizeof(hdcp2_version));
1745	if (!ret && hdcp2_version & HDCP_2_2_HDMI_SUPPORT_MASK)
1746		*capable = true;
1747
1748	return ret;
1749}
1750
1751static const struct intel_hdcp_shim intel_hdmi_hdcp_shim = {
1752	.write_an_aksv = intel_hdmi_hdcp_write_an_aksv,
1753	.read_bksv = intel_hdmi_hdcp_read_bksv,
1754	.read_bstatus = intel_hdmi_hdcp_read_bstatus,
1755	.repeater_present = intel_hdmi_hdcp_repeater_present,
1756	.read_ri_prime = intel_hdmi_hdcp_read_ri_prime,
1757	.read_ksv_ready = intel_hdmi_hdcp_read_ksv_ready,
1758	.read_ksv_fifo = intel_hdmi_hdcp_read_ksv_fifo,
1759	.read_v_prime_part = intel_hdmi_hdcp_read_v_prime_part,
1760	.toggle_signalling = intel_hdmi_hdcp_toggle_signalling,
1761	.check_link = intel_hdmi_hdcp_check_link,
1762	.write_2_2_msg = intel_hdmi_hdcp2_write_msg,
1763	.read_2_2_msg = intel_hdmi_hdcp2_read_msg,
1764	.check_2_2_link	= intel_hdmi_hdcp2_check_link,
1765	.hdcp_2_2_get_capability = intel_hdmi_hdcp2_get_capability,
1766	.protocol = HDCP_PROTOCOL_HDMI,
1767};
1768
1769static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder)
1770{
1771	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1772	int max_tmds_clock, vbt_max_tmds_clock;
1773
1774	if (DISPLAY_VER(dev_priv) >= 10)
1775		max_tmds_clock = 594000;
1776	else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv))
1777		max_tmds_clock = 300000;
1778	else if (DISPLAY_VER(dev_priv) >= 5)
1779		max_tmds_clock = 225000;
1780	else
1781		max_tmds_clock = 165000;
1782
1783	vbt_max_tmds_clock = intel_bios_hdmi_max_tmds_clock(encoder->devdata);
1784	if (vbt_max_tmds_clock)
1785		max_tmds_clock = min(max_tmds_clock, vbt_max_tmds_clock);
1786
1787	return max_tmds_clock;
1788}
1789
1790static bool intel_has_hdmi_sink(struct intel_hdmi *hdmi,
1791				const struct drm_connector_state *conn_state)
1792{
1793	struct intel_connector *connector = hdmi->attached_connector;
1794
1795	return connector->base.display_info.is_hdmi &&
1796		READ_ONCE(to_intel_digital_connector_state(conn_state)->force_audio) != HDMI_AUDIO_OFF_DVI;
1797}
1798
1799static bool intel_hdmi_is_ycbcr420(const struct intel_crtc_state *crtc_state)
1800{
1801	return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420;
1802}
1803
1804static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1805				 bool respect_downstream_limits,
1806				 bool has_hdmi_sink)
1807{
1808	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
1809	int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder);
1810
1811	if (respect_downstream_limits) {
1812		struct intel_connector *connector = hdmi->attached_connector;
1813		const struct drm_display_info *info = &connector->base.display_info;
1814
1815		if (hdmi->dp_dual_mode.max_tmds_clock)
1816			max_tmds_clock = min(max_tmds_clock,
1817					     hdmi->dp_dual_mode.max_tmds_clock);
1818
1819		if (info->max_tmds_clock)
1820			max_tmds_clock = min(max_tmds_clock,
1821					     info->max_tmds_clock);
1822		else if (!has_hdmi_sink)
1823			max_tmds_clock = min(max_tmds_clock, 165000);
1824	}
1825
1826	return max_tmds_clock;
1827}
1828
1829static enum drm_mode_status
1830hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1831		      int clock, bool respect_downstream_limits,
1832		      bool has_hdmi_sink)
1833{
1834	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1835	enum phy phy = intel_port_to_phy(dev_priv, hdmi_to_dig_port(hdmi)->base.port);
1836
1837	if (clock < 25000)
1838		return MODE_CLOCK_LOW;
1839	if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits,
1840					  has_hdmi_sink))
1841		return MODE_CLOCK_HIGH;
1842
1843	/* GLK DPLL can't generate 446-480 MHz */
1844	if (IS_GEMINILAKE(dev_priv) && clock > 446666 && clock < 480000)
1845		return MODE_CLOCK_RANGE;
1846
1847	/* BXT/GLK DPLL can't generate 223-240 MHz */
1848	if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1849	    clock > 223333 && clock < 240000)
1850		return MODE_CLOCK_RANGE;
1851
1852	/* CHV DPLL can't generate 216-240 MHz */
1853	if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1854		return MODE_CLOCK_RANGE;
1855
1856	/* ICL+ combo PHY PLL can't generate 500-533.2 MHz */
1857	if (intel_phy_is_combo(dev_priv, phy) && clock > 500000 && clock < 533200)
1858		return MODE_CLOCK_RANGE;
1859
1860	/* ICL+ TC PHY PLL can't generate 500-532.8 MHz */
1861	if (intel_phy_is_tc(dev_priv, phy) && clock > 500000 && clock < 532800)
1862		return MODE_CLOCK_RANGE;
1863
1864	/*
1865	 * SNPS PHYs' MPLLB table-based programming can only handle a fixed
1866	 * set of link rates.
1867	 *
1868	 * FIXME: We will hopefully get an algorithmic way of programming
1869	 * the MPLLB for HDMI in the future.
1870	 */
1871	if (DISPLAY_VER(dev_priv) >= 14)
1872		return intel_cx0_phy_check_hdmi_link_rate(hdmi, clock);
1873	else if (IS_DG2(dev_priv))
1874		return intel_snps_phy_check_hdmi_link_rate(clock);
1875
1876	return MODE_OK;
1877}
1878
1879int intel_hdmi_tmds_clock(int clock, int bpc,
1880			  enum intel_output_format sink_format)
1881{
1882	/* YCBCR420 TMDS rate requirement is half the pixel clock */
1883	if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1884		clock /= 2;
1885
1886	/*
1887	 * Need to adjust the port link by:
1888	 *  1.5x for 12bpc
1889	 *  1.25x for 10bpc
1890	 */
1891	return DIV_ROUND_CLOSEST(clock * bpc, 8);
1892}
1893
1894static bool intel_hdmi_source_bpc_possible(struct drm_i915_private *i915, int bpc)
1895{
1896	switch (bpc) {
1897	case 12:
1898		return !HAS_GMCH(i915);
1899	case 10:
1900		return DISPLAY_VER(i915) >= 11;
1901	case 8:
1902		return true;
1903	default:
1904		MISSING_CASE(bpc);
1905		return false;
1906	}
1907}
1908
1909static bool intel_hdmi_sink_bpc_possible(struct drm_connector *connector,
1910					 int bpc, bool has_hdmi_sink,
1911					 enum intel_output_format sink_format)
1912{
1913	const struct drm_display_info *info = &connector->display_info;
1914	const struct drm_hdmi_info *hdmi = &info->hdmi;
1915
1916	switch (bpc) {
1917	case 12:
1918		if (!has_hdmi_sink)
1919			return false;
1920
1921		if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1922			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36;
1923		else
1924			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36;
1925	case 10:
1926		if (!has_hdmi_sink)
1927			return false;
1928
1929		if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420)
1930			return hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_30;
1931		else
1932			return info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30;
1933	case 8:
1934		return true;
1935	default:
1936		MISSING_CASE(bpc);
1937		return false;
1938	}
1939}
1940
1941static enum drm_mode_status
1942intel_hdmi_mode_clock_valid(struct drm_connector *connector, int clock,
1943			    bool has_hdmi_sink,
1944			    enum intel_output_format sink_format)
1945{
1946	struct drm_i915_private *i915 = to_i915(connector->dev);
1947	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1948	enum drm_mode_status status = MODE_OK;
1949	int bpc;
1950
1951	/*
1952	 * Try all color depths since valid port clock range
1953	 * can have holes. Any mode that can be used with at
1954	 * least one color depth is accepted.
1955	 */
1956	for (bpc = 12; bpc >= 8; bpc -= 2) {
1957		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc, sink_format);
1958
1959		if (!intel_hdmi_source_bpc_possible(i915, bpc))
1960			continue;
1961
1962		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink, sink_format))
1963			continue;
1964
1965		status = hdmi_port_clock_valid(hdmi, tmds_clock, true, has_hdmi_sink);
1966		if (status == MODE_OK)
1967			return MODE_OK;
1968	}
1969
1970	/* can never happen */
1971	drm_WARN_ON(&i915->drm, status == MODE_OK);
1972
1973	return status;
1974}
1975
1976static enum drm_mode_status
1977intel_hdmi_mode_valid(struct drm_connector *connector,
1978		      struct drm_display_mode *mode)
1979{
1980	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
1981	struct drm_i915_private *dev_priv = intel_hdmi_to_i915(hdmi);
1982	enum drm_mode_status status;
1983	int clock = mode->clock;
1984	int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1985	bool has_hdmi_sink = intel_has_hdmi_sink(hdmi, connector->state);
1986	bool ycbcr_420_only;
1987	enum intel_output_format sink_format;
1988
1989	status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1990	if (status != MODE_OK)
1991		return status;
1992
1993	if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1994		clock *= 2;
1995
1996	if (clock > max_dotclk)
1997		return MODE_CLOCK_HIGH;
1998
1999	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
2000		if (!has_hdmi_sink)
2001			return MODE_CLOCK_LOW;
2002		clock *= 2;
2003	}
2004
2005	/*
2006	 * HDMI2.1 requires higher resolution modes like 8k60, 4K120 to be
2007	 * enumerated only if FRL is supported. Current platforms do not support
2008	 * FRL so prune the higher resolution modes that require doctclock more
2009	 * than 600MHz.
2010	 */
2011	if (clock > 600000)
2012		return MODE_CLOCK_HIGH;
2013
2014	ycbcr_420_only = drm_mode_is_420_only(&connector->display_info, mode);
2015
2016	if (ycbcr_420_only)
2017		sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2018	else
2019		sink_format = INTEL_OUTPUT_FORMAT_RGB;
2020
2021	status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2022	if (status != MODE_OK) {
2023		if (ycbcr_420_only ||
2024		    !connector->ycbcr_420_allowed ||
2025		    !drm_mode_is_420_also(&connector->display_info, mode))
2026			return status;
2027
2028		sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2029		status = intel_hdmi_mode_clock_valid(connector, clock, has_hdmi_sink, sink_format);
2030		if (status != MODE_OK)
2031			return status;
2032	}
2033
2034	return intel_mode_valid_max_plane_size(dev_priv, mode, false);
2035}
2036
2037bool intel_hdmi_bpc_possible(const struct intel_crtc_state *crtc_state,
2038			     int bpc, bool has_hdmi_sink)
2039{
2040	struct drm_atomic_state *state = crtc_state->uapi.state;
2041	struct drm_connector_state *connector_state;
2042	struct drm_connector *connector;
2043	int i;
2044
2045	for_each_new_connector_in_state(state, connector, connector_state, i) {
2046		if (connector_state->crtc != crtc_state->uapi.crtc)
2047			continue;
2048
2049		if (!intel_hdmi_sink_bpc_possible(connector, bpc, has_hdmi_sink,
2050						  crtc_state->sink_format))
2051			return false;
2052	}
2053
2054	return true;
2055}
2056
2057static bool hdmi_bpc_possible(const struct intel_crtc_state *crtc_state, int bpc)
2058{
2059	struct drm_i915_private *dev_priv =
2060		to_i915(crtc_state->uapi.crtc->dev);
2061	const struct drm_display_mode *adjusted_mode =
2062		&crtc_state->hw.adjusted_mode;
2063
2064	if (!intel_hdmi_source_bpc_possible(dev_priv, bpc))
2065		return false;
2066
2067	/* Display Wa_1405510057:icl,ehl */
2068	if (intel_hdmi_is_ycbcr420(crtc_state) &&
2069	    bpc == 10 && DISPLAY_VER(dev_priv) == 11 &&
2070	    (adjusted_mode->crtc_hblank_end -
2071	     adjusted_mode->crtc_hblank_start) % 8 == 2)
2072		return false;
2073
2074	return intel_hdmi_bpc_possible(crtc_state, bpc, crtc_state->has_hdmi_sink);
2075}
2076
2077static int intel_hdmi_compute_bpc(struct intel_encoder *encoder,
2078				  struct intel_crtc_state *crtc_state,
2079				  int clock, bool respect_downstream_limits)
2080{
2081	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2082	int bpc;
2083
2084	/*
2085	 * pipe_bpp could already be below 8bpc due to FDI
2086	 * bandwidth constraints. HDMI minimum is 8bpc however.
2087	 */
2088	bpc = max(crtc_state->pipe_bpp / 3, 8);
2089
2090	/*
2091	 * We will never exceed downstream TMDS clock limits while
2092	 * attempting deep color. If the user insists on forcing an
2093	 * out of spec mode they will have to be satisfied with 8bpc.
2094	 */
2095	if (!respect_downstream_limits)
2096		bpc = 8;
2097
2098	for (; bpc >= 8; bpc -= 2) {
2099		int tmds_clock = intel_hdmi_tmds_clock(clock, bpc,
2100						       crtc_state->sink_format);
2101
2102		if (hdmi_bpc_possible(crtc_state, bpc) &&
2103		    hdmi_port_clock_valid(intel_hdmi, tmds_clock,
2104					  respect_downstream_limits,
2105					  crtc_state->has_hdmi_sink) == MODE_OK)
2106			return bpc;
2107	}
2108
2109	return -EINVAL;
2110}
2111
2112static int intel_hdmi_compute_clock(struct intel_encoder *encoder,
2113				    struct intel_crtc_state *crtc_state,
2114				    bool respect_downstream_limits)
2115{
2116	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2117	const struct drm_display_mode *adjusted_mode =
2118		&crtc_state->hw.adjusted_mode;
2119	int bpc, clock = adjusted_mode->crtc_clock;
2120
2121	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2122		clock *= 2;
2123
2124	bpc = intel_hdmi_compute_bpc(encoder, crtc_state, clock,
2125				     respect_downstream_limits);
2126	if (bpc < 0)
2127		return bpc;
2128
2129	crtc_state->port_clock =
2130		intel_hdmi_tmds_clock(clock, bpc, crtc_state->sink_format);
2131
2132	/*
2133	 * pipe_bpp could already be below 8bpc due to
2134	 * FDI bandwidth constraints. We shouldn't bump it
2135	 * back up to the HDMI minimum 8bpc in that case.
2136	 */
2137	crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3);
2138
2139	drm_dbg_kms(&i915->drm,
2140		    "picking %d bpc for HDMI output (pipe bpp: %d)\n",
2141		    bpc, crtc_state->pipe_bpp);
2142
2143	return 0;
2144}
2145
2146bool intel_hdmi_limited_color_range(const struct intel_crtc_state *crtc_state,
2147				    const struct drm_connector_state *conn_state)
2148{
2149	const struct intel_digital_connector_state *intel_conn_state =
2150		to_intel_digital_connector_state(conn_state);
2151	const struct drm_display_mode *adjusted_mode =
2152		&crtc_state->hw.adjusted_mode;
2153
2154	/*
2155	 * Our YCbCr output is always limited range.
2156	 * crtc_state->limited_color_range only applies to RGB,
2157	 * and it must never be set for YCbCr or we risk setting
2158	 * some conflicting bits in TRANSCONF which will mess up
2159	 * the colors on the monitor.
2160	 */
2161	if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
2162		return false;
2163
2164	if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
2165		/* See CEA-861-E - 5.1 Default Encoding Parameters */
2166		return crtc_state->has_hdmi_sink &&
2167			drm_default_rgb_quant_range(adjusted_mode) ==
2168			HDMI_QUANTIZATION_RANGE_LIMITED;
2169	} else {
2170		return intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
2171	}
2172}
2173
2174static bool intel_hdmi_has_audio(struct intel_encoder *encoder,
2175				 const struct intel_crtc_state *crtc_state,
2176				 const struct drm_connector_state *conn_state)
2177{
2178	struct drm_connector *connector = conn_state->connector;
2179	const struct intel_digital_connector_state *intel_conn_state =
2180		to_intel_digital_connector_state(conn_state);
2181
2182	if (!crtc_state->has_hdmi_sink)
2183		return false;
2184
2185	if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
2186		return connector->display_info.has_audio;
2187	else
2188		return intel_conn_state->force_audio == HDMI_AUDIO_ON;
2189}
2190
2191static enum intel_output_format
2192intel_hdmi_sink_format(const struct intel_crtc_state *crtc_state,
2193		       struct intel_connector *connector,
2194		       bool ycbcr_420_output)
2195{
2196	if (!crtc_state->has_hdmi_sink)
2197		return INTEL_OUTPUT_FORMAT_RGB;
2198
2199	if (connector->base.ycbcr_420_allowed && ycbcr_420_output)
2200		return INTEL_OUTPUT_FORMAT_YCBCR420;
2201	else
2202		return INTEL_OUTPUT_FORMAT_RGB;
2203}
2204
2205static enum intel_output_format
2206intel_hdmi_output_format(const struct intel_crtc_state *crtc_state)
2207{
2208	return crtc_state->sink_format;
2209}
2210
2211static int intel_hdmi_compute_output_format(struct intel_encoder *encoder,
2212					    struct intel_crtc_state *crtc_state,
2213					    const struct drm_connector_state *conn_state,
2214					    bool respect_downstream_limits)
2215{
2216	struct intel_connector *connector = to_intel_connector(conn_state->connector);
2217	const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2218	const struct drm_display_info *info = &connector->base.display_info;
2219	struct drm_i915_private *i915 = to_i915(connector->base.dev);
2220	bool ycbcr_420_only = drm_mode_is_420_only(info, adjusted_mode);
2221	int ret;
2222
2223	crtc_state->sink_format =
2224		intel_hdmi_sink_format(crtc_state, connector, ycbcr_420_only);
2225
2226	if (ycbcr_420_only && crtc_state->sink_format != INTEL_OUTPUT_FORMAT_YCBCR420) {
2227		drm_dbg_kms(&i915->drm,
2228			    "YCbCr 4:2:0 mode but YCbCr 4:2:0 output not possible. Falling back to RGB.\n");
2229		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_RGB;
2230	}
2231
2232	crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2233	ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2234	if (ret) {
2235		if (crtc_state->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
2236		    !crtc_state->has_hdmi_sink ||
2237		    !connector->base.ycbcr_420_allowed ||
2238		    !drm_mode_is_420_also(info, adjusted_mode))
2239			return ret;
2240
2241		crtc_state->sink_format = INTEL_OUTPUT_FORMAT_YCBCR420;
2242		crtc_state->output_format = intel_hdmi_output_format(crtc_state);
2243		ret = intel_hdmi_compute_clock(encoder, crtc_state, respect_downstream_limits);
2244	}
2245
2246	return ret;
2247}
2248
2249static bool intel_hdmi_is_cloned(const struct intel_crtc_state *crtc_state)
2250{
2251	return crtc_state->uapi.encoder_mask &&
2252		!is_power_of_2(crtc_state->uapi.encoder_mask);
2253}
2254
2255static bool source_supports_scrambling(struct intel_encoder *encoder)
2256{
2257	/*
2258	 * Gen 10+ support HDMI 2.0 : the max tmds clock is 594MHz, and
2259	 * scrambling is supported.
2260	 * But there seem to be cases where certain platforms that support
2261	 * HDMI 2.0, have an HDMI1.4 retimer chip, and the max tmds clock is
2262	 * capped by VBT to less than 340MHz.
2263	 *
2264	 * In such cases when an HDMI2.0 sink is connected, it creates a
2265	 * problem : the platform and the sink both support scrambling but the
2266	 * HDMI 1.4 retimer chip doesn't.
2267	 *
2268	 * So go for scrambling, based on the max tmds clock taking into account,
2269	 * restrictions coming from VBT.
2270	 */
2271	return intel_hdmi_source_max_tmds_clock(encoder) > 340000;
2272}
2273
2274bool intel_hdmi_compute_has_hdmi_sink(struct intel_encoder *encoder,
2275				      const struct intel_crtc_state *crtc_state,
2276				      const struct drm_connector_state *conn_state)
2277{
2278	struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
2279
2280	return intel_has_hdmi_sink(hdmi, conn_state) &&
2281		!intel_hdmi_is_cloned(crtc_state);
2282}
2283
2284int intel_hdmi_compute_config(struct intel_encoder *encoder,
2285			      struct intel_crtc_state *pipe_config,
2286			      struct drm_connector_state *conn_state)
2287{
2288	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2289	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2290	struct drm_connector *connector = conn_state->connector;
2291	struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
2292	int ret;
2293
2294	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
2295		return -EINVAL;
2296
2297	if (!connector->interlace_allowed &&
2298	    adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
2299		return -EINVAL;
2300
2301	pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2302
2303	if (pipe_config->has_hdmi_sink)
2304		pipe_config->has_infoframe = true;
2305
2306	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
2307		pipe_config->pixel_multiplier = 2;
2308
2309	pipe_config->has_audio =
2310		intel_hdmi_has_audio(encoder, pipe_config, conn_state) &&
2311		intel_audio_compute_config(encoder, pipe_config, conn_state);
2312
2313	/*
2314	 * Try to respect downstream TMDS clock limits first, if
2315	 * that fails assume the user might know something we don't.
2316	 */
2317	ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, true);
2318	if (ret)
2319		ret = intel_hdmi_compute_output_format(encoder, pipe_config, conn_state, false);
2320	if (ret) {
2321		drm_dbg_kms(&dev_priv->drm,
2322			    "unsupported HDMI clock (%d kHz), rejecting mode\n",
2323			    pipe_config->hw.adjusted_mode.crtc_clock);
2324		return ret;
2325	}
2326
2327	if (intel_hdmi_is_ycbcr420(pipe_config)) {
2328		ret = intel_panel_fitting(pipe_config, conn_state);
2329		if (ret)
2330			return ret;
2331	}
2332
2333	pipe_config->limited_color_range =
2334		intel_hdmi_limited_color_range(pipe_config, conn_state);
2335
2336	if (conn_state->picture_aspect_ratio)
2337		adjusted_mode->picture_aspect_ratio =
2338			conn_state->picture_aspect_ratio;
2339
2340	pipe_config->lane_count = 4;
2341
2342	if (scdc->scrambling.supported && source_supports_scrambling(encoder)) {
2343		if (scdc->scrambling.low_rates)
2344			pipe_config->hdmi_scrambling = true;
2345
2346		if (pipe_config->port_clock > 340000) {
2347			pipe_config->hdmi_scrambling = true;
2348			pipe_config->hdmi_high_tmds_clock_ratio = true;
2349		}
2350	}
2351
2352	intel_hdmi_compute_gcp_infoframe(encoder, pipe_config,
2353					 conn_state);
2354
2355	if (!intel_hdmi_compute_avi_infoframe(encoder, pipe_config, conn_state)) {
2356		drm_dbg_kms(&dev_priv->drm, "bad AVI infoframe\n");
2357		return -EINVAL;
2358	}
2359
2360	if (!intel_hdmi_compute_spd_infoframe(encoder, pipe_config, conn_state)) {
2361		drm_dbg_kms(&dev_priv->drm, "bad SPD infoframe\n");
2362		return -EINVAL;
2363	}
2364
2365	if (!intel_hdmi_compute_hdmi_infoframe(encoder, pipe_config, conn_state)) {
2366		drm_dbg_kms(&dev_priv->drm, "bad HDMI infoframe\n");
2367		return -EINVAL;
2368	}
2369
2370	if (!intel_hdmi_compute_drm_infoframe(encoder, pipe_config, conn_state)) {
2371		drm_dbg_kms(&dev_priv->drm, "bad DRM infoframe\n");
2372		return -EINVAL;
2373	}
2374
2375	return 0;
2376}
2377
2378void intel_hdmi_encoder_shutdown(struct intel_encoder *encoder)
2379{
2380	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
2381
2382	/*
2383	 * Give a hand to buggy BIOSen which forget to turn
2384	 * the TMDS output buffers back on after a reboot.
2385	 */
2386	intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2387}
2388
2389static void
2390intel_hdmi_unset_edid(struct drm_connector *connector)
2391{
2392	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2393
2394	intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
2395	intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
2396
2397	drm_edid_free(to_intel_connector(connector)->detect_edid);
2398	to_intel_connector(connector)->detect_edid = NULL;
2399}
2400
2401static void
2402intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector)
2403{
2404	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2405	struct intel_hdmi *hdmi = intel_attached_hdmi(to_intel_connector(connector));
2406	struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base;
2407	struct i2c_adapter *ddc = connector->ddc;
2408	enum drm_dp_dual_mode_type type;
2409
2410	type = drm_dp_dual_mode_detect(&dev_priv->drm, ddc);
2411
2412	/*
2413	 * Type 1 DVI adaptors are not required to implement any
2414	 * registers, so we can't always detect their presence.
2415	 * Ideally we should be able to check the state of the
2416	 * CONFIG1 pin, but no such luck on our hardware.
2417	 *
2418	 * The only method left to us is to check the VBT to see
2419	 * if the port is a dual mode capable DP port.
2420	 */
2421	if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
2422		if (!connector->force &&
2423		    intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2424			drm_dbg_kms(&dev_priv->drm,
2425				    "Assuming DP dual mode adaptor presence based on VBT\n");
2426			type = DRM_DP_DUAL_MODE_TYPE1_DVI;
2427		} else {
2428			type = DRM_DP_DUAL_MODE_NONE;
2429		}
2430	}
2431
2432	if (type == DRM_DP_DUAL_MODE_NONE)
2433		return;
2434
2435	hdmi->dp_dual_mode.type = type;
2436	hdmi->dp_dual_mode.max_tmds_clock =
2437		drm_dp_dual_mode_max_tmds_clock(&dev_priv->drm, type, ddc);
2438
2439	drm_dbg_kms(&dev_priv->drm,
2440		    "DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
2441		    drm_dp_get_dual_mode_type_name(type),
2442		    hdmi->dp_dual_mode.max_tmds_clock);
2443
2444	/* Older VBTs are often buggy and can't be trusted :( Play it safe. */
2445	if ((DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) &&
2446	    !intel_bios_encoder_supports_dp_dual_mode(encoder->devdata)) {
2447		drm_dbg_kms(&dev_priv->drm,
2448			    "Ignoring DP dual mode adaptor max TMDS clock for native HDMI port\n");
2449		hdmi->dp_dual_mode.max_tmds_clock = 0;
2450	}
2451}
2452
2453static bool
2454intel_hdmi_set_edid(struct drm_connector *connector)
2455{
2456	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2457	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2458	struct i2c_adapter *ddc = connector->ddc;
2459	intel_wakeref_t wakeref;
2460	const struct drm_edid *drm_edid;
2461	bool connected = false;
2462
2463	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2464
2465	drm_edid = drm_edid_read_ddc(connector, ddc);
2466
2467	if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
2468		drm_dbg_kms(&dev_priv->drm,
2469			    "HDMI GMBUS EDID read failed, retry using GPIO bit-banging\n");
2470		intel_gmbus_force_bit(ddc, true);
2471		drm_edid = drm_edid_read_ddc(connector, ddc);
2472		intel_gmbus_force_bit(ddc, false);
2473	}
2474
2475	/* Below we depend on display info having been updated */
2476	drm_edid_connector_update(connector, drm_edid);
2477
2478	to_intel_connector(connector)->detect_edid = drm_edid;
2479
2480	if (drm_edid_is_digital(drm_edid)) {
2481		intel_hdmi_dp_dual_mode_detect(connector);
2482
2483		connected = true;
2484	}
2485
2486	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2487
2488	cec_notifier_set_phys_addr(intel_hdmi->cec_notifier,
2489				   connector->display_info.source_physical_address);
2490
2491	return connected;
2492}
2493
2494static enum drm_connector_status
2495intel_hdmi_detect(struct drm_connector *connector, bool force)
2496{
2497	enum drm_connector_status status = connector_status_disconnected;
2498	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2499	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(to_intel_connector(connector));
2500	struct intel_encoder *encoder = &hdmi_to_dig_port(intel_hdmi)->base;
2501	intel_wakeref_t wakeref;
2502
2503	drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n",
2504		    connector->base.id, connector->name);
2505
2506	if (!intel_display_device_enabled(dev_priv))
2507		return connector_status_disconnected;
2508
2509	if (!intel_display_driver_check_access(dev_priv))
2510		return connector->status;
2511
2512	wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
2513
2514	if (DISPLAY_VER(dev_priv) >= 11 &&
2515	    !intel_digital_port_connected(encoder))
2516		goto out;
2517
2518	intel_hdmi_unset_edid(connector);
2519
2520	if (intel_hdmi_set_edid(connector))
2521		status = connector_status_connected;
2522
2523out:
2524	intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS, wakeref);
2525
2526	if (status != connector_status_connected)
2527		cec_notifier_phys_addr_invalidate(intel_hdmi->cec_notifier);
2528
2529	return status;
2530}
2531
2532static void
2533intel_hdmi_force(struct drm_connector *connector)
2534{
2535	struct drm_i915_private *i915 = to_i915(connector->dev);
2536
2537	drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s]\n",
2538		    connector->base.id, connector->name);
2539
2540	if (!intel_display_driver_check_access(i915))
2541		return;
2542
2543	intel_hdmi_unset_edid(connector);
2544
2545	if (connector->status != connector_status_connected)
2546		return;
2547
2548	intel_hdmi_set_edid(connector);
2549}
2550
2551static int intel_hdmi_get_modes(struct drm_connector *connector)
2552{
2553	/* drm_edid_connector_update() done in ->detect() or ->force() */
2554	return drm_edid_connector_add_modes(connector);
2555}
2556
2557static int
2558intel_hdmi_connector_register(struct drm_connector *connector)
2559{
2560	int ret;
2561
2562	ret = intel_connector_register(connector);
2563	if (ret)
2564		return ret;
2565
2566	return ret;
2567}
2568
2569static void intel_hdmi_connector_unregister(struct drm_connector *connector)
2570{
2571	struct cec_notifier *n = intel_attached_hdmi(to_intel_connector(connector))->cec_notifier;
2572
2573	cec_notifier_conn_unregister(n);
2574
2575	intel_connector_unregister(connector);
2576}
2577
2578static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
2579	.detect = intel_hdmi_detect,
2580	.force = intel_hdmi_force,
2581	.fill_modes = drm_helper_probe_single_connector_modes,
2582	.atomic_get_property = intel_digital_connector_atomic_get_property,
2583	.atomic_set_property = intel_digital_connector_atomic_set_property,
2584	.late_register = intel_hdmi_connector_register,
2585	.early_unregister = intel_hdmi_connector_unregister,
2586	.destroy = intel_connector_destroy,
2587	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2588	.atomic_duplicate_state = intel_digital_connector_duplicate_state,
2589};
2590
2591static int intel_hdmi_connector_atomic_check(struct drm_connector *connector,
2592					     struct drm_atomic_state *state)
2593{
2594	struct drm_i915_private *i915 = to_i915(state->dev);
2595
2596	if (HAS_DDI(i915))
2597		return intel_digital_connector_atomic_check(connector, state);
2598	else
2599		return g4x_hdmi_connector_atomic_check(connector, state);
2600}
2601
2602static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
2603	.get_modes = intel_hdmi_get_modes,
2604	.mode_valid = intel_hdmi_mode_valid,
2605	.atomic_check = intel_hdmi_connector_atomic_check,
2606};
2607
2608static void
2609intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
2610{
2611	struct drm_i915_private *dev_priv = to_i915(connector->dev);
2612
2613	intel_attach_force_audio_property(connector);
2614	intel_attach_broadcast_rgb_property(connector);
2615	intel_attach_aspect_ratio_property(connector);
2616
2617	intel_attach_hdmi_colorspace_property(connector);
2618	drm_connector_attach_content_type_property(connector);
2619
2620	if (DISPLAY_VER(dev_priv) >= 10)
2621		drm_connector_attach_hdr_output_metadata_property(connector);
2622
2623	if (!HAS_GMCH(dev_priv))
2624		drm_connector_attach_max_bpc_property(connector, 8, 12);
2625}
2626
2627/*
2628 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
2629 * @encoder: intel_encoder
2630 * @connector: drm_connector
2631 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
2632 *  or reset the high tmds clock ratio for scrambling
2633 * @scrambling: bool to Indicate if the function needs to set or reset
2634 *  sink scrambling
2635 *
2636 * This function handles scrambling on HDMI 2.0 capable sinks.
2637 * If required clock rate is > 340 Mhz && scrambling is supported by sink
2638 * it enables scrambling. This should be called before enabling the HDMI
2639 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
2640 * detect a scrambled clock within 100 ms.
2641 *
2642 * Returns:
2643 * True on success, false on failure.
2644 */
2645bool intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
2646				       struct drm_connector *connector,
2647				       bool high_tmds_clock_ratio,
2648				       bool scrambling)
2649{
2650	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651	struct drm_scrambling *sink_scrambling =
2652		&connector->display_info.hdmi.scdc.scrambling;
2653
2654	if (!sink_scrambling->supported)
2655		return true;
2656
2657	drm_dbg_kms(&dev_priv->drm,
2658		    "[CONNECTOR:%d:%s] scrambling=%s, TMDS bit clock ratio=1/%d\n",
2659		    connector->base.id, connector->name,
2660		    str_yes_no(scrambling), high_tmds_clock_ratio ? 40 : 10);
2661
2662	/* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
2663	return drm_scdc_set_high_tmds_clock_ratio(connector, high_tmds_clock_ratio) &&
2664		drm_scdc_set_scrambling(connector, scrambling);
2665}
2666
2667static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2668{
2669	u8 ddc_pin;
2670
2671	switch (port) {
2672	case PORT_B:
2673		ddc_pin = GMBUS_PIN_DPB;
2674		break;
2675	case PORT_C:
2676		ddc_pin = GMBUS_PIN_DPC;
2677		break;
2678	case PORT_D:
2679		ddc_pin = GMBUS_PIN_DPD_CHV;
2680		break;
2681	default:
2682		MISSING_CASE(port);
2683		ddc_pin = GMBUS_PIN_DPB;
2684		break;
2685	}
2686	return ddc_pin;
2687}
2688
2689static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2690{
2691	u8 ddc_pin;
2692
2693	switch (port) {
2694	case PORT_B:
2695		ddc_pin = GMBUS_PIN_1_BXT;
2696		break;
2697	case PORT_C:
2698		ddc_pin = GMBUS_PIN_2_BXT;
2699		break;
2700	default:
2701		MISSING_CASE(port);
2702		ddc_pin = GMBUS_PIN_1_BXT;
2703		break;
2704	}
2705	return ddc_pin;
2706}
2707
2708static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2709			      enum port port)
2710{
2711	u8 ddc_pin;
2712
2713	switch (port) {
2714	case PORT_B:
2715		ddc_pin = GMBUS_PIN_1_BXT;
2716		break;
2717	case PORT_C:
2718		ddc_pin = GMBUS_PIN_2_BXT;
2719		break;
2720	case PORT_D:
2721		ddc_pin = GMBUS_PIN_4_CNP;
2722		break;
2723	case PORT_F:
2724		ddc_pin = GMBUS_PIN_3_BXT;
2725		break;
2726	default:
2727		MISSING_CASE(port);
2728		ddc_pin = GMBUS_PIN_1_BXT;
2729		break;
2730	}
2731	return ddc_pin;
2732}
2733
2734static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2735{
2736	enum phy phy = intel_port_to_phy(dev_priv, port);
2737
2738	if (intel_phy_is_combo(dev_priv, phy))
2739		return GMBUS_PIN_1_BXT + port;
2740	else if (intel_phy_is_tc(dev_priv, phy))
2741		return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port);
2742
2743	drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port));
2744	return GMBUS_PIN_2_BXT;
2745}
2746
2747static u8 mcc_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2748{
2749	enum phy phy = intel_port_to_phy(dev_priv, port);
2750	u8 ddc_pin;
2751
2752	switch (phy) {
2753	case PHY_A:
2754		ddc_pin = GMBUS_PIN_1_BXT;
2755		break;
2756	case PHY_B:
2757		ddc_pin = GMBUS_PIN_2_BXT;
2758		break;
2759	case PHY_C:
2760		ddc_pin = GMBUS_PIN_9_TC1_ICP;
2761		break;
2762	default:
2763		MISSING_CASE(phy);
2764		ddc_pin = GMBUS_PIN_1_BXT;
2765		break;
2766	}
2767	return ddc_pin;
2768}
2769
2770static u8 rkl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2771{
2772	enum phy phy = intel_port_to_phy(dev_priv, port);
2773
2774	WARN_ON(port == PORT_C);
2775
2776	/*
2777	 * Pin mapping for RKL depends on which PCH is present.  With TGP, the
2778	 * final two outputs use type-c pins, even though they're actually
2779	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2780	 * all outputs.
2781	 */
2782	if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP && phy >= PHY_C)
2783		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2784
2785	return GMBUS_PIN_1_BXT + phy;
2786}
2787
2788static u8 gen9bc_tgp_port_to_ddc_pin(struct drm_i915_private *i915, enum port port)
2789{
2790	enum phy phy = intel_port_to_phy(i915, port);
2791
2792	drm_WARN_ON(&i915->drm, port == PORT_A);
2793
2794	/*
2795	 * Pin mapping for GEN9 BC depends on which PCH is present.  With TGP,
2796	 * final two outputs use type-c pins, even though they're actually
2797	 * combo outputs.  With CMP, the traditional DDI A-D pins are used for
2798	 * all outputs.
2799	 */
2800	if (INTEL_PCH_TYPE(i915) >= PCH_TGP && phy >= PHY_C)
2801		return GMBUS_PIN_9_TC1_ICP + phy - PHY_C;
2802
2803	return GMBUS_PIN_1_BXT + phy;
2804}
2805
2806static u8 dg1_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2807{
2808	return intel_port_to_phy(dev_priv, port) + 1;
2809}
2810
2811static u8 adls_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
2812{
2813	enum phy phy = intel_port_to_phy(dev_priv, port);
2814
2815	WARN_ON(port == PORT_B || port == PORT_C);
2816
2817	/*
2818	 * Pin mapping for ADL-S requires TC pins for all combo phy outputs
2819	 * except first combo output.
2820	 */
2821	if (phy == PHY_A)
2822		return GMBUS_PIN_1_BXT;
2823
2824	return GMBUS_PIN_9_TC1_ICP + phy - PHY_B;
2825}
2826
2827static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
2828			      enum port port)
2829{
2830	u8 ddc_pin;
2831
2832	switch (port) {
2833	case PORT_B:
2834		ddc_pin = GMBUS_PIN_DPB;
2835		break;
2836	case PORT_C:
2837		ddc_pin = GMBUS_PIN_DPC;
2838		break;
2839	case PORT_D:
2840		ddc_pin = GMBUS_PIN_DPD;
2841		break;
2842	default:
2843		MISSING_CASE(port);
2844		ddc_pin = GMBUS_PIN_DPB;
2845		break;
2846	}
2847	return ddc_pin;
2848}
2849
2850static u8 intel_hdmi_default_ddc_pin(struct intel_encoder *encoder)
2851{
2852	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2853	enum port port = encoder->port;
2854	u8 ddc_pin;
2855
2856	if (IS_ALDERLAKE_S(dev_priv))
2857		ddc_pin = adls_port_to_ddc_pin(dev_priv, port);
2858	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
2859		ddc_pin = dg1_port_to_ddc_pin(dev_priv, port);
2860	else if (IS_ROCKETLAKE(dev_priv))
2861		ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2862	else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2863		ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2864	else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
2865		 HAS_PCH_TGP(dev_priv))
2866		ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2867	else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2868		ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
2869	else if (HAS_PCH_CNP(dev_priv))
2870		ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
2871	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
2872		ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
2873	else if (IS_CHERRYVIEW(dev_priv))
2874		ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
2875	else
2876		ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
2877
2878	return ddc_pin;
2879}
2880
2881static struct intel_encoder *
2882get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
2883{
2884	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2885	struct intel_encoder *other;
2886
2887	for_each_intel_encoder(&i915->drm, other) {
2888		struct intel_connector *connector;
2889
2890		if (other == encoder)
2891			continue;
2892
2893		if (!intel_encoder_is_dig_port(other))
2894			continue;
2895
2896		connector = enc_to_dig_port(other)->hdmi.attached_connector;
2897
2898		if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
2899			return other;
2900	}
2901
2902	return NULL;
2903}
2904
2905static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
2906{
2907	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2908	struct intel_encoder *other;
2909	const char *source;
2910	u8 ddc_pin;
2911
2912	ddc_pin = intel_bios_hdmi_ddc_pin(encoder->devdata);
2913	source = "VBT";
2914
2915	if (!ddc_pin) {
2916		ddc_pin = intel_hdmi_default_ddc_pin(encoder);
2917		source = "platform default";
2918	}
2919
2920	if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
2921		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Invalid DDC pin %d\n",
2922			    encoder->base.base.id, encoder->base.name, ddc_pin);
2923		return 0;
2924	}
2925
2926	other = get_encoder_by_ddc_pin(encoder, ddc_pin);
2927	if (other) {
2928		drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] DDC pin %d already claimed by [ENCODER:%d:%s]\n",
2929			    encoder->base.base.id, encoder->base.name, ddc_pin,
2930			    other->base.base.id, other->base.name);
2931		return 0;
2932	}
2933
2934	drm_dbg_kms(&i915->drm,
2935		    "[ENCODER:%d:%s] Using DDC pin 0x%x (%s)\n",
2936		    encoder->base.base.id, encoder->base.name,
2937		    ddc_pin, source);
2938
2939	return ddc_pin;
2940}
2941
2942void intel_infoframe_init(struct intel_digital_port *dig_port)
2943{
2944	struct drm_i915_private *dev_priv =
2945		to_i915(dig_port->base.base.dev);
2946
2947	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2948		dig_port->write_infoframe = vlv_write_infoframe;
2949		dig_port->read_infoframe = vlv_read_infoframe;
2950		dig_port->set_infoframes = vlv_set_infoframes;
2951		dig_port->infoframes_enabled = vlv_infoframes_enabled;
2952	} else if (IS_G4X(dev_priv)) {
2953		dig_port->write_infoframe = g4x_write_infoframe;
2954		dig_port->read_infoframe = g4x_read_infoframe;
2955		dig_port->set_infoframes = g4x_set_infoframes;
2956		dig_port->infoframes_enabled = g4x_infoframes_enabled;
2957	} else if (HAS_DDI(dev_priv)) {
2958		if (intel_bios_encoder_is_lspcon(dig_port->base.devdata)) {
2959			dig_port->write_infoframe = lspcon_write_infoframe;
2960			dig_port->read_infoframe = lspcon_read_infoframe;
2961			dig_port->set_infoframes = lspcon_set_infoframes;
2962			dig_port->infoframes_enabled = lspcon_infoframes_enabled;
2963		} else {
2964			dig_port->write_infoframe = hsw_write_infoframe;
2965			dig_port->read_infoframe = hsw_read_infoframe;
2966			dig_port->set_infoframes = hsw_set_infoframes;
2967			dig_port->infoframes_enabled = hsw_infoframes_enabled;
2968		}
2969	} else if (HAS_PCH_IBX(dev_priv)) {
2970		dig_port->write_infoframe = ibx_write_infoframe;
2971		dig_port->read_infoframe = ibx_read_infoframe;
2972		dig_port->set_infoframes = ibx_set_infoframes;
2973		dig_port->infoframes_enabled = ibx_infoframes_enabled;
2974	} else {
2975		dig_port->write_infoframe = cpt_write_infoframe;
2976		dig_port->read_infoframe = cpt_read_infoframe;
2977		dig_port->set_infoframes = cpt_set_infoframes;
2978		dig_port->infoframes_enabled = cpt_infoframes_enabled;
2979	}
2980}
2981
2982void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
2983			       struct intel_connector *intel_connector)
2984{
2985	struct drm_connector *connector = &intel_connector->base;
2986	struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2987	struct intel_encoder *intel_encoder = &dig_port->base;
2988	struct drm_device *dev = intel_encoder->base.dev;
2989	struct drm_i915_private *dev_priv = to_i915(dev);
2990	enum port port = intel_encoder->port;
2991	struct cec_connector_info conn_info;
2992	u8 ddc_pin;
2993
2994	drm_dbg_kms(&dev_priv->drm,
2995		    "Adding HDMI connector on [ENCODER:%d:%s]\n",
2996		    intel_encoder->base.base.id, intel_encoder->base.name);
2997
2998	if (DISPLAY_VER(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A))
2999		return;
3000
3001	if (drm_WARN(dev, dig_port->max_lanes < 4,
3002		     "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n",
3003		     dig_port->max_lanes, intel_encoder->base.base.id,
3004		     intel_encoder->base.name))
3005		return;
3006
3007	ddc_pin = intel_hdmi_ddc_pin(intel_encoder);
3008	if (!ddc_pin)
3009		return;
3010
3011	drm_connector_init_with_ddc(dev, connector,
3012				    &intel_hdmi_connector_funcs,
3013				    DRM_MODE_CONNECTOR_HDMIA,
3014				    intel_gmbus_get_adapter(dev_priv, ddc_pin));
3015
3016	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
3017
3018	if (DISPLAY_VER(dev_priv) < 12)
3019		connector->interlace_allowed = true;
3020
3021	connector->stereo_allowed = true;
3022
3023	if (DISPLAY_VER(dev_priv) >= 10)
3024		connector->ycbcr_420_allowed = true;
3025
3026	intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
3027	intel_connector->base.polled = intel_connector->polled;
3028
3029	if (HAS_DDI(dev_priv))
3030		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
3031	else
3032		intel_connector->get_hw_state = intel_connector_get_hw_state;
3033
3034	intel_hdmi_add_properties(intel_hdmi, connector);
3035
3036	intel_connector_attach_encoder(intel_connector, intel_encoder);
3037	intel_hdmi->attached_connector = intel_connector;
3038
3039	if (is_hdcp_supported(dev_priv, port)) {
3040		int ret = intel_hdcp_init(intel_connector, dig_port,
3041					  &intel_hdmi_hdcp_shim);
3042		if (ret)
3043			drm_dbg_kms(&dev_priv->drm,
3044				    "HDCP init failed, skipping.\n");
3045	}
3046
3047	cec_fill_conn_info_from_drm(&conn_info, connector);
3048
3049	intel_hdmi->cec_notifier =
3050		cec_notifier_conn_register(dev->dev, port_identifier(port),
3051					   &conn_info);
3052	if (!intel_hdmi->cec_notifier)
3053		drm_dbg_kms(&dev_priv->drm, "CEC notifier get failed\n");
3054}
3055
3056/*
3057 * intel_hdmi_dsc_get_slice_height - get the dsc slice_height
3058 * @vactive: Vactive of a display mode
3059 *
3060 * @return: appropriate dsc slice height for a given mode.
3061 */
3062int intel_hdmi_dsc_get_slice_height(int vactive)
3063{
3064	int slice_height;
3065
3066	/*
3067	 * Slice Height determination : HDMI2.1 Section 7.7.5.2
3068	 * Select smallest slice height >=96, that results in a valid PPS and
3069	 * requires minimum padding lines required for final slice.
3070	 *
3071	 * Assumption : Vactive is even.
3072	 */
3073	for (slice_height = 96; slice_height <= vactive; slice_height += 2)
3074		if (vactive % slice_height == 0)
3075			return slice_height;
3076
3077	return 0;
3078}
3079
3080/*
3081 * intel_hdmi_dsc_get_num_slices - get no. of dsc slices based on dsc encoder
3082 * and dsc decoder capabilities
3083 *
3084 * @crtc_state: intel crtc_state
3085 * @src_max_slices: maximum slices supported by the DSC encoder
3086 * @src_max_slice_width: maximum slice width supported by DSC encoder
3087 * @hdmi_max_slices: maximum slices supported by sink DSC decoder
3088 * @hdmi_throughput: maximum clock per slice (MHz) supported by HDMI sink
3089 *
3090 * @return: num of dsc slices that can be supported by the dsc encoder
3091 * and decoder.
3092 */
3093int
3094intel_hdmi_dsc_get_num_slices(const struct intel_crtc_state *crtc_state,
3095			      int src_max_slices, int src_max_slice_width,
3096			      int hdmi_max_slices, int hdmi_throughput)
3097{
3098/* Pixel rates in KPixels/sec */
3099#define HDMI_DSC_PEAK_PIXEL_RATE		2720000
3100/*
3101 * Rates at which the source and sink are required to process pixels in each
3102 * slice, can be two levels: either atleast 340000KHz or atleast 40000KHz.
3103 */
3104#define HDMI_DSC_MAX_ENC_THROUGHPUT_0		340000
3105#define HDMI_DSC_MAX_ENC_THROUGHPUT_1		400000
3106
3107/* Spec limits the slice width to 2720 pixels */
3108#define MAX_HDMI_SLICE_WIDTH			2720
3109	int kslice_adjust;
3110	int adjusted_clk_khz;
3111	int min_slices;
3112	int target_slices;
3113	int max_throughput; /* max clock freq. in khz per slice */
3114	int max_slice_width;
3115	int slice_width;
3116	int pixel_clock = crtc_state->hw.adjusted_mode.crtc_clock;
3117
3118	if (!hdmi_throughput)
3119		return 0;
3120
3121	/*
3122	 * Slice Width determination : HDMI2.1 Section 7.7.5.1
3123	 * kslice_adjust factor for 4:2:0, and 4:2:2 formats is 0.5, where as
3124	 * for 4:4:4 is 1.0. Multiplying these factors by 10 and later
3125	 * dividing adjusted clock value by 10.
3126	 */
3127	if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3128	    crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB)
3129		kslice_adjust = 10;
3130	else
3131		kslice_adjust = 5;
3132
3133	/*
3134	 * As per spec, the rate at which the source and the sink process
3135	 * the pixels per slice are at two levels: atleast 340Mhz or 400Mhz.
3136	 * This depends upon the pixel clock rate and output formats
3137	 * (kslice adjust).
3138	 * If pixel clock * kslice adjust >= 2720MHz slices can be processed
3139	 * at max 340MHz, otherwise they can be processed at max 400MHz.
3140	 */
3141
3142	adjusted_clk_khz = DIV_ROUND_UP(kslice_adjust * pixel_clock, 10);
3143
3144	if (adjusted_clk_khz <= HDMI_DSC_PEAK_PIXEL_RATE)
3145		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_0;
3146	else
3147		max_throughput = HDMI_DSC_MAX_ENC_THROUGHPUT_1;
3148
3149	/*
3150	 * Taking into account the sink's capability for maximum
3151	 * clock per slice (in MHz) as read from HF-VSDB.
3152	 */
3153	max_throughput = min(max_throughput, hdmi_throughput * 1000);
3154
3155	min_slices = DIV_ROUND_UP(adjusted_clk_khz, max_throughput);
3156	max_slice_width = min(MAX_HDMI_SLICE_WIDTH, src_max_slice_width);
3157
3158	/*
3159	 * Keep on increasing the num of slices/line, starting from min_slices
3160	 * per line till we get such a number, for which the slice_width is
3161	 * just less than max_slice_width. The slices/line selected should be
3162	 * less than or equal to the max horizontal slices that the combination
3163	 * of PCON encoder and HDMI decoder can support.
3164	 */
3165	slice_width = max_slice_width;
3166
3167	do {
3168		if (min_slices <= 1 && src_max_slices >= 1 && hdmi_max_slices >= 1)
3169			target_slices = 1;
3170		else if (min_slices <= 2 && src_max_slices >= 2 && hdmi_max_slices >= 2)
3171			target_slices = 2;
3172		else if (min_slices <= 4 && src_max_slices >= 4 && hdmi_max_slices >= 4)
3173			target_slices = 4;
3174		else if (min_slices <= 8 && src_max_slices >= 8 && hdmi_max_slices >= 8)
3175			target_slices = 8;
3176		else if (min_slices <= 12 && src_max_slices >= 12 && hdmi_max_slices >= 12)
3177			target_slices = 12;
3178		else if (min_slices <= 16 && src_max_slices >= 16 && hdmi_max_slices >= 16)
3179			target_slices = 16;
3180		else
3181			return 0;
3182
3183		slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, target_slices);
3184		if (slice_width >= max_slice_width)
3185			min_slices = target_slices + 1;
3186	} while (slice_width >= max_slice_width);
3187
3188	return target_slices;
3189}
3190
3191/*
3192 * intel_hdmi_dsc_get_bpp - get the appropriate compressed bits_per_pixel based on
3193 * source and sink capabilities.
3194 *
3195 * @src_fraction_bpp: fractional bpp supported by the source
3196 * @slice_width: dsc slice width supported by the source and sink
3197 * @num_slices: num of slices supported by the source and sink
3198 * @output_format: video output format
3199 * @hdmi_all_bpp: sink supports decoding of 1/16th bpp setting
3200 * @hdmi_max_chunk_bytes: max bytes in a line of chunks supported by sink
3201 *
3202 * @return: compressed bits_per_pixel in step of 1/16 of bits_per_pixel
3203 */
3204int
3205intel_hdmi_dsc_get_bpp(int src_fractional_bpp, int slice_width, int num_slices,
3206		       int output_format, bool hdmi_all_bpp,
3207		       int hdmi_max_chunk_bytes)
3208{
3209	int max_dsc_bpp, min_dsc_bpp;
3210	int target_bytes;
3211	bool bpp_found = false;
3212	int bpp_decrement_x16;
3213	int bpp_target;
3214	int bpp_target_x16;
3215
3216	/*
3217	 * Get min bpp and max bpp as per Table 7.23, in HDMI2.1 spec
3218	 * Start with the max bpp and keep on decrementing with
3219	 * fractional bpp, if supported by PCON DSC encoder
3220	 *
3221	 * for each bpp we check if no of bytes can be supported by HDMI sink
3222	 */
3223
3224	/* Assuming: bpc as 8*/
3225	if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) {
3226		min_dsc_bpp = 6;
3227		max_dsc_bpp = 3 * 4; /* 3*bpc/2 */
3228	} else if (output_format == INTEL_OUTPUT_FORMAT_YCBCR444 ||
3229		   output_format == INTEL_OUTPUT_FORMAT_RGB) {
3230		min_dsc_bpp = 8;
3231		max_dsc_bpp = 3 * 8; /* 3*bpc */
3232	} else {
3233		/* Assuming 4:2:2 encoding */
3234		min_dsc_bpp = 7;
3235		max_dsc_bpp = 2 * 8; /* 2*bpc */
3236	}
3237
3238	/*
3239	 * Taking into account if all dsc_all_bpp supported by HDMI2.1 sink
3240	 * Section 7.7.34 : Source shall not enable compressed Video
3241	 * Transport with bpp_target settings above 12 bpp unless
3242	 * DSC_all_bpp is set to 1.
3243	 */
3244	if (!hdmi_all_bpp)
3245		max_dsc_bpp = min(max_dsc_bpp, 12);
3246
3247	/*
3248	 * The Sink has a limit of compressed data in bytes for a scanline,
3249	 * as described in max_chunk_bytes field in HFVSDB block of edid.
3250	 * The no. of bytes depend on the target bits per pixel that the
3251	 * source configures. So we start with the max_bpp and calculate
3252	 * the target_chunk_bytes. We keep on decrementing the target_bpp,
3253	 * till we get the target_chunk_bytes just less than what the sink's
3254	 * max_chunk_bytes, or else till we reach the min_dsc_bpp.
3255	 *
3256	 * The decrement is according to the fractional support from PCON DSC
3257	 * encoder. For fractional BPP we use bpp_target as a multiple of 16.
3258	 *
3259	 * bpp_target_x16 = bpp_target * 16
3260	 * So we need to decrement by {1, 2, 4, 8, 16} for fractional bpps
3261	 * {1/16, 1/8, 1/4, 1/2, 1} respectively.
3262	 */
3263
3264	bpp_target = max_dsc_bpp;
3265
3266	/* src does not support fractional bpp implies decrement by 16 for bppx16 */
3267	if (!src_fractional_bpp)
3268		src_fractional_bpp = 1;
3269	bpp_decrement_x16 = DIV_ROUND_UP(16, src_fractional_bpp);
3270	bpp_target_x16 = (bpp_target * 16) - bpp_decrement_x16;
3271
3272	while (bpp_target_x16 > (min_dsc_bpp * 16)) {
3273		int bpp;
3274
3275		bpp = DIV_ROUND_UP(bpp_target_x16, 16);
3276		target_bytes = DIV_ROUND_UP((num_slices * slice_width * bpp), 8);
3277		if (target_bytes <= hdmi_max_chunk_bytes) {
3278			bpp_found = true;
3279			break;
3280		}
3281		bpp_target_x16 -= bpp_decrement_x16;
3282	}
3283	if (bpp_found)
3284		return bpp_target_x16;
3285
3286	return 0;
3287}