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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "amdgpu_pm.h"
27#include "soc15.h"
28#include "soc15d.h"
29#include "jpeg_v4_0_3.h"
30
31#include "vcn/vcn_5_0_0_offset.h"
32#include "vcn/vcn_5_0_0_sh_mask.h"
33#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
34
35static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
36static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
37static int jpeg_v5_0_0_set_powergating_state(void *handle,
38 enum amd_powergating_state state);
39
40/**
41 * jpeg_v5_0_0_early_init - set function pointers
42 *
43 * @handle: amdgpu_device pointer
44 *
45 * Set ring and irq function pointers
46 */
47static int jpeg_v5_0_0_early_init(void *handle)
48{
49 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
50
51 adev->jpeg.num_jpeg_inst = 1;
52 adev->jpeg.num_jpeg_rings = 1;
53
54 jpeg_v5_0_0_set_dec_ring_funcs(adev);
55 jpeg_v5_0_0_set_irq_funcs(adev);
56
57 return 0;
58}
59
60/**
61 * jpeg_v5_0_0_sw_init - sw init for JPEG block
62 *
63 * @handle: amdgpu_device pointer
64 *
65 * Load firmware and sw initialization
66 */
67static int jpeg_v5_0_0_sw_init(void *handle)
68{
69 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
70 struct amdgpu_ring *ring;
71 int r;
72
73 /* JPEG TRAP */
74 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
75 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
76 if (r)
77 return r;
78
79 r = amdgpu_jpeg_sw_init(adev);
80 if (r)
81 return r;
82
83 r = amdgpu_jpeg_resume(adev);
84 if (r)
85 return r;
86
87 ring = adev->jpeg.inst->ring_dec;
88 ring->use_doorbell = true;
89 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
90 ring->vm_hub = AMDGPU_MMHUB0(0);
91
92 sprintf(ring->name, "jpeg_dec");
93 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
94 AMDGPU_RING_PRIO_DEFAULT, NULL);
95 if (r)
96 return r;
97
98 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
99 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
100
101 return 0;
102}
103
104/**
105 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block
106 *
107 * @handle: amdgpu_device pointer
108 *
109 * JPEG suspend and free up sw allocation
110 */
111static int jpeg_v5_0_0_sw_fini(void *handle)
112{
113 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
114 int r;
115
116 r = amdgpu_jpeg_suspend(adev);
117 if (r)
118 return r;
119
120 r = amdgpu_jpeg_sw_fini(adev);
121
122 return r;
123}
124
125/**
126 * jpeg_v5_0_0_hw_init - start and test JPEG block
127 *
128 * @handle: amdgpu_device pointer
129 *
130 */
131static int jpeg_v5_0_0_hw_init(void *handle)
132{
133 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
134 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
135 int r;
136
137 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
138 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
139
140 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
141 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
142 VCN_JPEG_DB_CTRL__EN_MASK);
143
144 r = amdgpu_ring_test_helper(ring);
145 if (r)
146 return r;
147
148 DRM_DEV_INFO(adev->dev, "JPEG decode initialized successfully.\n");
149
150 return 0;
151}
152
153/**
154 * jpeg_v5_0_0_hw_fini - stop the hardware block
155 *
156 * @handle: amdgpu_device pointer
157 *
158 * Stop the JPEG block, mark ring as not ready any more
159 */
160static int jpeg_v5_0_0_hw_fini(void *handle)
161{
162 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
163
164 cancel_delayed_work_sync(&adev->vcn.idle_work);
165
166 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
167 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
168 jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
169
170 return 0;
171}
172
173/**
174 * jpeg_v5_0_0_suspend - suspend JPEG block
175 *
176 * @handle: amdgpu_device pointer
177 *
178 * HW fini and suspend JPEG block
179 */
180static int jpeg_v5_0_0_suspend(void *handle)
181{
182 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
183 int r;
184
185 r = jpeg_v5_0_0_hw_fini(adev);
186 if (r)
187 return r;
188
189 r = amdgpu_jpeg_suspend(adev);
190
191 return r;
192}
193
194/**
195 * jpeg_v5_0_0_resume - resume JPEG block
196 *
197 * @handle: amdgpu_device pointer
198 *
199 * Resume firmware and hw init JPEG block
200 */
201static int jpeg_v5_0_0_resume(void *handle)
202{
203 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
204 int r;
205
206 r = amdgpu_jpeg_resume(adev);
207 if (r)
208 return r;
209
210 r = jpeg_v5_0_0_hw_init(adev);
211
212 return r;
213}
214
215static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev)
216{
217 uint32_t data = 0;
218
219 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
220
221 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
222 data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK
223 | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK);
224 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
225}
226
227static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)
228{
229 uint32_t data = 0;
230
231 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
232
233 data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT;
234 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
235
236 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
237 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK
238 |JPEG_CGC_GATE__JPEG_ENC_MASK
239 |JPEG_CGC_GATE__JMCIF_MASK
240 |JPEG_CGC_GATE__JRBBM_MASK);
241 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
242}
243
244static int jpeg_v5_0_0_disable_static_power_gating(struct amdgpu_device *adev)
245{
246 uint32_t data = 0;
247
248 data = 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT;
249 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data);
250 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0,
251 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
252
253 /* disable anti hang mechanism */
254 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
255 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
256
257 /* keep the JPEG in static PG mode */
258 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
259 ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK);
260
261 return 0;
262}
263
264static int jpeg_v5_0_0_enable_static_power_gating(struct amdgpu_device *adev)
265{
266 /* enable anti hang mechanism */
267 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
268 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
269 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
270
271 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
272 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
273 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
274 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
275 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
276 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
277 }
278
279 return 0;
280}
281
282/**
283 * jpeg_v5_0_0_start - start JPEG block
284 *
285 * @adev: amdgpu_device pointer
286 *
287 * Setup and start the JPEG block
288 */
289static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
290{
291 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
292 int r;
293
294 if (adev->pm.dpm_enabled)
295 amdgpu_dpm_enable_jpeg(adev, true);
296
297 /* disable power gating */
298 r = jpeg_v5_0_0_disable_static_power_gating(adev);
299 if (r)
300 return r;
301
302 /* JPEG disable CGC */
303 jpeg_v5_0_0_disable_clock_gating(adev);
304
305 /* MJPEG global tiling registers */
306 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
307 adev->gfx.config.gb_addr_config);
308
309
310 /* enable JMI channel */
311 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
312 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
313
314 /* enable System Interrupt for JRBC */
315 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
316 JPEG_SYS_INT_EN__DJRBC0_MASK,
317 ~JPEG_SYS_INT_EN__DJRBC0_MASK);
318
319 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
320 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
321 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
322 lower_32_bits(ring->gpu_addr));
323 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
324 upper_32_bits(ring->gpu_addr));
325 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
326 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
327 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
328 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
329 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
330
331 return 0;
332}
333
334/**
335 * jpeg_v5_0_0_stop - stop JPEG block
336 *
337 * @adev: amdgpu_device pointer
338 *
339 * stop the JPEG block
340 */
341static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)
342{
343 int r;
344
345 /* reset JMI */
346 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
347 UVD_JMI_CNTL__SOFT_RESET_MASK,
348 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
349
350 jpeg_v5_0_0_enable_clock_gating(adev);
351
352 /* enable power gating */
353 r = jpeg_v5_0_0_enable_static_power_gating(adev);
354 if (r)
355 return r;
356
357 if (adev->pm.dpm_enabled)
358 amdgpu_dpm_enable_jpeg(adev, false);
359
360 return 0;
361}
362
363/**
364 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer
365 *
366 * @ring: amdgpu_ring pointer
367 *
368 * Returns the current hardware read pointer
369 */
370static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
371{
372 struct amdgpu_device *adev = ring->adev;
373
374 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
375}
376
377/**
378 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer
379 *
380 * @ring: amdgpu_ring pointer
381 *
382 * Returns the current hardware write pointer
383 */
384static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
385{
386 struct amdgpu_device *adev = ring->adev;
387
388 if (ring->use_doorbell)
389 return *ring->wptr_cpu_addr;
390 else
391 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
392}
393
394/**
395 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer
396 *
397 * @ring: amdgpu_ring pointer
398 *
399 * Commits the write pointer to the hardware
400 */
401static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
402{
403 struct amdgpu_device *adev = ring->adev;
404
405 if (ring->use_doorbell) {
406 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
407 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
408 } else {
409 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
410 }
411}
412
413static bool jpeg_v5_0_0_is_idle(void *handle)
414{
415 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
416 int ret = 1;
417
418 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
419 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
420 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
421
422 return ret;
423}
424
425static int jpeg_v5_0_0_wait_for_idle(void *handle)
426{
427 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
428
429 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
430 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
431 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
432}
433
434static int jpeg_v5_0_0_set_clockgating_state(void *handle,
435 enum amd_clockgating_state state)
436{
437 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
438 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
439
440 if (enable) {
441 if (!jpeg_v5_0_0_is_idle(handle))
442 return -EBUSY;
443 jpeg_v5_0_0_enable_clock_gating(adev);
444 } else {
445 jpeg_v5_0_0_disable_clock_gating(adev);
446 }
447
448 return 0;
449}
450
451static int jpeg_v5_0_0_set_powergating_state(void *handle,
452 enum amd_powergating_state state)
453{
454 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
455 int ret;
456
457 if (state == adev->jpeg.cur_state)
458 return 0;
459
460 if (state == AMD_PG_STATE_GATE)
461 ret = jpeg_v5_0_0_stop(adev);
462 else
463 ret = jpeg_v5_0_0_start(adev);
464
465 if (!ret)
466 adev->jpeg.cur_state = state;
467
468 return ret;
469}
470
471static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev,
472 struct amdgpu_irq_src *source,
473 unsigned int type,
474 enum amdgpu_interrupt_state state)
475{
476 return 0;
477}
478
479static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,
480 struct amdgpu_irq_src *source,
481 struct amdgpu_iv_entry *entry)
482{
483 DRM_DEBUG("IH: JPEG TRAP\n");
484
485 switch (entry->src_id) {
486 case VCN_4_0__SRCID__JPEG_DECODE:
487 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
488 break;
489 default:
490 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
491 entry->src_id, entry->src_data[0]);
492 break;
493 }
494
495 return 0;
496}
497
498static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
499 .name = "jpeg_v5_0_0",
500 .early_init = jpeg_v5_0_0_early_init,
501 .late_init = NULL,
502 .sw_init = jpeg_v5_0_0_sw_init,
503 .sw_fini = jpeg_v5_0_0_sw_fini,
504 .hw_init = jpeg_v5_0_0_hw_init,
505 .hw_fini = jpeg_v5_0_0_hw_fini,
506 .suspend = jpeg_v5_0_0_suspend,
507 .resume = jpeg_v5_0_0_resume,
508 .is_idle = jpeg_v5_0_0_is_idle,
509 .wait_for_idle = jpeg_v5_0_0_wait_for_idle,
510 .check_soft_reset = NULL,
511 .pre_soft_reset = NULL,
512 .soft_reset = NULL,
513 .post_soft_reset = NULL,
514 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
515 .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
516};
517
518static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
519 .type = AMDGPU_RING_TYPE_VCN_JPEG,
520 .align_mask = 0xf,
521 .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
522 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
523 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
524 .emit_frame_size =
525 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
526 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
527 8 + /* jpeg_v5_0_0_dec_ring_emit_vm_flush */
528 22 + 22 + /* jpeg_v5_0_0_dec_ring_emit_fence x2 vm fence */
529 8 + 16,
530 .emit_ib_size = 22, /* jpeg_v5_0_0_dec_ring_emit_ib */
531 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
532 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
533 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
534 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
535 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
536 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
537 .insert_start = jpeg_v4_0_3_dec_ring_insert_start,
538 .insert_end = jpeg_v4_0_3_dec_ring_insert_end,
539 .pad_ib = amdgpu_ring_generic_pad_ib,
540 .begin_use = amdgpu_jpeg_ring_begin_use,
541 .end_use = amdgpu_jpeg_ring_end_use,
542 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
543 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
544 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
545};
546
547static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
548{
549 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
550 DRM_DEV_INFO(adev->dev, "JPEG decode is enabled in VM mode\n");
551}
552
553static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
554 .set = jpeg_v5_0_0_set_interrupt_state,
555 .process = jpeg_v5_0_0_process_interrupt,
556};
557
558static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
559{
560 adev->jpeg.inst->irq.num_types = 1;
561 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;
562}
563
564const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = {
565 .type = AMD_IP_BLOCK_TYPE_JPEG,
566 .major = 5,
567 .minor = 0,
568 .rev = 0,
569 .funcs = &jpeg_v5_0_0_ip_funcs,
570};