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1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 *
24 */
25
26#include <drm/amdgpu_drm.h>
27#include "amdgpu.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_i2c.h"
31
32#define TARGET_HW_I2C_CLOCK 50
33
34/* these are a limitation of ProcessI2cChannelTransaction not the hw */
35#define ATOM_MAX_HW_I2C_WRITE 3
36#define ATOM_MAX_HW_I2C_READ 255
37
38static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
39 u8 slave_addr, u8 flags,
40 u8 *buf, u8 num)
41{
42 struct drm_device *dev = chan->dev;
43 struct amdgpu_device *adev = drm_to_adev(dev);
44 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
45 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
46 unsigned char *base;
47 u16 out = cpu_to_le16(0);
48 int r = 0;
49
50 memset(&args, 0, sizeof(args));
51
52 mutex_lock(&chan->mutex);
53
54 base = (unsigned char *)adev->mode_info.atom_context->scratch;
55
56 if (flags & HW_I2C_WRITE) {
57 if (num > ATOM_MAX_HW_I2C_WRITE) {
58 DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
59 r = -EINVAL;
60 goto done;
61 }
62 if (buf == NULL)
63 args.ucRegIndex = 0;
64 else
65 args.ucRegIndex = buf[0];
66 if (num)
67 num--;
68 if (num) {
69 if (buf) {
70 memcpy(&out, &buf[1], num);
71 } else {
72 DRM_ERROR("hw i2c: missing buf with num > 1\n");
73 r = -EINVAL;
74 goto done;
75 }
76 }
77 args.lpI2CDataOut = cpu_to_le16(out);
78 } else {
79 args.ucRegIndex = 0;
80 args.lpI2CDataOut = 0;
81 }
82
83 args.ucFlag = flags;
84 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
85 args.ucTransBytes = num;
86 args.ucSlaveAddr = slave_addr << 1;
87 args.ucLineNumber = chan->rec.i2c_id;
88
89 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
90
91 /* error */
92 if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
93 DRM_DEBUG_KMS("hw_i2c error\n");
94 r = -EIO;
95 goto done;
96 }
97
98 if (!(flags & HW_I2C_WRITE))
99 amdgpu_atombios_copy_swap(buf, base, num, false);
100
101done:
102 mutex_unlock(&chan->mutex);
103
104 return r;
105}
106
107int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
108 struct i2c_msg *msgs, int num)
109{
110 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
111 struct i2c_msg *p;
112 int i, remaining, current_count, buffer_offset, max_bytes, ret;
113 u8 flags;
114
115 /* check for bus probe */
116 p = &msgs[0];
117 if ((num == 1) && (p->len == 0)) {
118 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
119 p->addr, HW_I2C_WRITE,
120 NULL, 0);
121 if (ret)
122 return ret;
123 else
124 return num;
125 }
126
127 for (i = 0; i < num; i++) {
128 p = &msgs[i];
129 remaining = p->len;
130 buffer_offset = 0;
131 /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
132 if (p->flags & I2C_M_RD) {
133 max_bytes = ATOM_MAX_HW_I2C_READ;
134 flags = HW_I2C_READ;
135 } else {
136 max_bytes = ATOM_MAX_HW_I2C_WRITE;
137 flags = HW_I2C_WRITE;
138 }
139 while (remaining) {
140 if (remaining > max_bytes)
141 current_count = max_bytes;
142 else
143 current_count = remaining;
144 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
145 p->addr, flags,
146 &p->buf[buffer_offset], current_count);
147 if (ret)
148 return ret;
149 remaining -= current_count;
150 buffer_offset += current_count;
151 }
152 }
153
154 return num;
155}
156
157u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
158{
159 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
160}
161
162void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
163{
164 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
165 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
166
167 args.ucRegIndex = offset;
168 args.lpI2CDataOut = data;
169 args.ucFlag = 1;
170 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
171 args.ucTransBytes = 1;
172 args.ucSlaveAddr = slave_addr;
173 args.ucLineNumber = line_number;
174
175 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, sizeof(args));
176}
1/*
2 * Copyright 2011 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 *
24 */
25
26#include <drm/amdgpu_drm.h>
27#include "amdgpu.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_i2c.h"
31
32#define TARGET_HW_I2C_CLOCK 50
33
34/* these are a limitation of ProcessI2cChannelTransaction not the hw */
35#define ATOM_MAX_HW_I2C_WRITE 3
36#define ATOM_MAX_HW_I2C_READ 255
37
38static int amdgpu_atombios_i2c_process_i2c_ch(struct amdgpu_i2c_chan *chan,
39 u8 slave_addr, u8 flags,
40 u8 *buf, u8 num)
41{
42 struct drm_device *dev = chan->dev;
43 struct amdgpu_device *adev = drm_to_adev(dev);
44 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
45 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
46 unsigned char *base;
47 u16 out = cpu_to_le16(0);
48 int r = 0;
49
50 memset(&args, 0, sizeof(args));
51
52 mutex_lock(&chan->mutex);
53
54 base = (unsigned char *)adev->mode_info.atom_context->scratch;
55
56 if (flags & HW_I2C_WRITE) {
57 if (num > ATOM_MAX_HW_I2C_WRITE) {
58 DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
59 r = -EINVAL;
60 goto done;
61 }
62 if (buf == NULL)
63 args.ucRegIndex = 0;
64 else
65 args.ucRegIndex = buf[0];
66 if (num)
67 num--;
68 if (num) {
69 if (buf) {
70 memcpy(&out, &buf[1], num);
71 } else {
72 DRM_ERROR("hw i2c: missing buf with num > 1\n");
73 r = -EINVAL;
74 goto done;
75 }
76 }
77 args.lpI2CDataOut = cpu_to_le16(out);
78 } else {
79 args.ucRegIndex = 0;
80 args.lpI2CDataOut = 0;
81 }
82
83 args.ucFlag = flags;
84 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
85 args.ucTransBytes = num;
86 args.ucSlaveAddr = slave_addr << 1;
87 args.ucLineNumber = chan->rec.i2c_id;
88
89 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
90
91 /* error */
92 if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
93 DRM_DEBUG_KMS("hw_i2c error\n");
94 r = -EIO;
95 goto done;
96 }
97
98 if (!(flags & HW_I2C_WRITE))
99 amdgpu_atombios_copy_swap(buf, base, num, false);
100
101done:
102 mutex_unlock(&chan->mutex);
103
104 return r;
105}
106
107int amdgpu_atombios_i2c_xfer(struct i2c_adapter *i2c_adap,
108 struct i2c_msg *msgs, int num)
109{
110 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
111 struct i2c_msg *p;
112 int i, remaining, current_count, buffer_offset, max_bytes, ret;
113 u8 flags;
114
115 /* check for bus probe */
116 p = &msgs[0];
117 if ((num == 1) && (p->len == 0)) {
118 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
119 p->addr, HW_I2C_WRITE,
120 NULL, 0);
121 if (ret)
122 return ret;
123 else
124 return num;
125 }
126
127 for (i = 0; i < num; i++) {
128 p = &msgs[i];
129 remaining = p->len;
130 buffer_offset = 0;
131 /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
132 if (p->flags & I2C_M_RD) {
133 max_bytes = ATOM_MAX_HW_I2C_READ;
134 flags = HW_I2C_READ;
135 } else {
136 max_bytes = ATOM_MAX_HW_I2C_WRITE;
137 flags = HW_I2C_WRITE;
138 }
139 while (remaining) {
140 if (remaining > max_bytes)
141 current_count = max_bytes;
142 else
143 current_count = remaining;
144 ret = amdgpu_atombios_i2c_process_i2c_ch(i2c,
145 p->addr, flags,
146 &p->buf[buffer_offset], current_count);
147 if (ret)
148 return ret;
149 remaining -= current_count;
150 buffer_offset += current_count;
151 }
152 }
153
154 return num;
155}
156
157u32 amdgpu_atombios_i2c_func(struct i2c_adapter *adap)
158{
159 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
160}
161
162void amdgpu_atombios_i2c_channel_trans(struct amdgpu_device *adev, u8 slave_addr, u8 line_number, u8 offset, u8 data)
163{
164 PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
165 int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
166
167 args.ucRegIndex = offset;
168 args.lpI2CDataOut = data;
169 args.ucFlag = 1;
170 args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
171 args.ucTransBytes = 1;
172 args.ucSlaveAddr = slave_addr;
173 args.ucLineNumber = line_number;
174
175 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
176}