1/*
  2 * Copyright 2023 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#include "amdgpu.h"
 25#include "athub_v4_1_0.h"
 26#include "athub/athub_4_1_0_offset.h"
 27#include "athub/athub_4_1_0_sh_mask.h"
 28#include "soc15_common.h"
 29
 30static uint32_t athub_v4_1_0_get_cg_cntl(struct amdgpu_device *adev)
 31{
 32	uint32_t data;
 33
 34	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
 35	case IP_VERSION(4, 1, 0):
 36		data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
 37		break;
 38	default:
 39		data = 0;
 40		break;
 41	}
 42	return data;
 43}
 44
 45static void athub_v4_1_0_set_cg_cntl(struct amdgpu_device *adev, uint32_t data)
 46{
 47	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
 48	case IP_VERSION(4, 1, 0):
 49		WREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL, data);
 50		break;
 51	default:
 52		break;
 53	}
 54}
 55
 56static void
 57athub_v4_1_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 58					      bool enable)
 59{
 60	uint32_t def, data;
 61
 62	def = data = athub_v4_1_0_get_cg_cntl(adev);
 63
 64	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
 65		data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 66	else
 67		data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
 68
 69	if (def != data)
 70		athub_v4_1_0_set_cg_cntl(adev, data);
 71}
 72
 73static void
 74athub_v4_1_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 75					     bool enable)
 76{
 77	uint32_t def, data;
 78
 79	def = data = athub_v4_1_0_get_cg_cntl(adev);
 80
 81	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
 82		data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 83	else
 84		data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
 85
 86	if (def != data)
 87		athub_v4_1_0_set_cg_cntl(adev, data);
 88}
 89
 90int athub_v4_1_0_set_clockgating(struct amdgpu_device *adev,
 91				 enum amd_clockgating_state state)
 92{
 93	if (amdgpu_sriov_vf(adev))
 94		return 0;
 95
 96	switch (amdgpu_ip_version(adev, ATHUB_HWIP, 0)) {
 97	case IP_VERSION(4, 1, 0):
 98		athub_v4_1_0_update_medium_grain_clock_gating(adev,
 99				state == AMD_CG_STATE_GATE);
100		athub_v4_1_0_update_medium_grain_light_sleep(adev,
101				state == AMD_CG_STATE_GATE);
102		break;
103	default:
104		break;
105	}
106
107	return 0;
108}
109
110void athub_v4_1_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
111{
112	int data;
113
114	/* AMD_CG_SUPPORT_ATHUB_MGCG */
115	data = athub_v4_1_0_get_cg_cntl(adev);
116	if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
117		*flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
118
119	/* AMD_CG_SUPPORT_ATHUB_LS */
120	if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
121		*flags |= AMD_CG_SUPPORT_ATHUB_LS;
122}