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1/*
2 * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
3 *
4 * For licencing details see kernel-base/COPYING
5 */
6#include <linux/dmi.h>
7#include <linux/init.h>
8#include <linux/ioport.h>
9#include <linux/export.h>
10#include <linux/pci.h>
11
12#include <asm/acpi.h>
13#include <asm/bios_ebda.h>
14#include <asm/paravirt.h>
15#include <asm/pci_x86.h>
16#include <asm/mpspec.h>
17#include <asm/setup.h>
18#include <asm/apic.h>
19#include <asm/e820/api.h>
20#include <asm/time.h>
21#include <asm/irq.h>
22#include <asm/io_apic.h>
23#include <asm/hpet.h>
24#include <asm/memtype.h>
25#include <asm/tsc.h>
26#include <asm/iommu.h>
27#include <asm/mach_traps.h>
28#include <asm/irqdomain.h>
29#include <asm/realmode.h>
30
31void x86_init_noop(void) { }
32void __init x86_init_uint_noop(unsigned int unused) { }
33static int __init iommu_init_noop(void) { return 0; }
34static void iommu_shutdown_noop(void) { }
35bool __init bool_x86_init_noop(void) { return false; }
36void x86_op_int_noop(int cpu) { }
37int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
38void get_rtc_noop(struct timespec64 *now) { }
39
40static __initconst const struct of_device_id of_cmos_match[] = {
41 { .compatible = "motorola,mc146818" },
42 {}
43};
44
45/*
46 * Allow devicetree configured systems to disable the RTC by setting the
47 * corresponding DT node's status property to disabled. Code is optimized
48 * out for CONFIG_OF=n builds.
49 */
50static __init void x86_wallclock_init(void)
51{
52 struct device_node *node = of_find_matching_node(NULL, of_cmos_match);
53
54 if (node && !of_device_is_available(node)) {
55 x86_platform.get_wallclock = get_rtc_noop;
56 x86_platform.set_wallclock = set_rtc_noop;
57 }
58}
59
60/*
61 * The platform setup functions are preset with the default functions
62 * for standard PC hardware.
63 */
64struct x86_init_ops x86_init __initdata = {
65
66 .resources = {
67 .probe_roms = probe_roms,
68 .reserve_resources = reserve_standard_io_resources,
69 .memory_setup = e820__memory_setup_default,
70 .dmi_setup = dmi_setup,
71 },
72
73 .mpparse = {
74 .setup_ioapic_ids = x86_init_noop,
75 .find_mptable = mpparse_find_mptable,
76 .early_parse_smp_cfg = mpparse_parse_early_smp_config,
77 .parse_smp_cfg = mpparse_parse_smp_config,
78 },
79
80 .irqs = {
81 .pre_vector_init = init_ISA_irqs,
82 .intr_init = native_init_IRQ,
83 .intr_mode_select = apic_intr_mode_select,
84 .intr_mode_init = apic_intr_mode_init,
85 .create_pci_msi_domain = native_create_pci_msi_domain,
86 },
87
88 .oem = {
89 .arch_setup = x86_init_noop,
90 .banner = default_banner,
91 },
92
93 .paging = {
94 .pagetable_init = native_pagetable_init,
95 },
96
97 .timers = {
98 .setup_percpu_clockev = setup_boot_APIC_clock,
99 .timer_init = hpet_time_init,
100 .wallclock_init = x86_wallclock_init,
101 },
102
103 .iommu = {
104 .iommu_init = iommu_init_noop,
105 },
106
107 .pci = {
108 .init = x86_default_pci_init,
109 .init_irq = x86_default_pci_init_irq,
110 .fixup_irqs = x86_default_pci_fixup_irqs,
111 },
112
113 .hyper = {
114 .init_platform = x86_init_noop,
115 .guest_late_init = x86_init_noop,
116 .x2apic_available = bool_x86_init_noop,
117 .msi_ext_dest_id = bool_x86_init_noop,
118 .init_mem_mapping = x86_init_noop,
119 .init_after_bootmem = x86_init_noop,
120 },
121
122 .acpi = {
123 .set_root_pointer = x86_default_set_root_pointer,
124 .get_root_pointer = x86_default_get_root_pointer,
125 .reduced_hw_early_init = acpi_generic_reduced_hw_init,
126 },
127};
128
129struct x86_cpuinit_ops x86_cpuinit = {
130 .early_percpu_clock_init = x86_init_noop,
131 .setup_percpu_clockev = setup_secondary_APIC_clock,
132 .parallel_bringup = true,
133};
134
135static void default_nmi_init(void) { };
136
137static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { return true; }
138static bool enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return true; }
139static bool enc_tlb_flush_required_noop(bool enc) { return false; }
140static bool enc_cache_flush_required_noop(void) { return false; }
141static bool is_private_mmio_noop(u64 addr) {return false; }
142
143struct x86_platform_ops x86_platform __ro_after_init = {
144 .calibrate_cpu = native_calibrate_cpu_early,
145 .calibrate_tsc = native_calibrate_tsc,
146 .get_wallclock = mach_get_cmos_time,
147 .set_wallclock = mach_set_cmos_time,
148 .iommu_shutdown = iommu_shutdown_noop,
149 .is_untracked_pat_range = is_ISA_range,
150 .nmi_init = default_nmi_init,
151 .get_nmi_reason = default_get_nmi_reason,
152 .save_sched_clock_state = tsc_save_sched_clock_state,
153 .restore_sched_clock_state = tsc_restore_sched_clock_state,
154 .realmode_reserve = reserve_real_mode,
155 .realmode_init = init_real_mode,
156 .hyper.pin_vcpu = x86_op_int_noop,
157 .hyper.is_private_mmio = is_private_mmio_noop,
158
159 .guest = {
160 .enc_status_change_prepare = enc_status_change_prepare_noop,
161 .enc_status_change_finish = enc_status_change_finish_noop,
162 .enc_tlb_flush_required = enc_tlb_flush_required_noop,
163 .enc_cache_flush_required = enc_cache_flush_required_noop,
164 },
165};
166
167EXPORT_SYMBOL_GPL(x86_platform);
168
169struct x86_apic_ops x86_apic_ops __ro_after_init = {
170 .io_apic_read = native_io_apic_read,
171 .restore = native_restore_boot_irq_mode,
172};
1/*
2 * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
3 *
4 * For licencing details see kernel-base/COPYING
5 */
6#include <linux/init.h>
7#include <linux/ioport.h>
8#include <linux/export.h>
9#include <linux/pci.h>
10
11#include <asm/acpi.h>
12#include <asm/bios_ebda.h>
13#include <asm/paravirt.h>
14#include <asm/pci_x86.h>
15#include <asm/mpspec.h>
16#include <asm/setup.h>
17#include <asm/apic.h>
18#include <asm/e820/api.h>
19#include <asm/time.h>
20#include <asm/irq.h>
21#include <asm/io_apic.h>
22#include <asm/hpet.h>
23#include <asm/memtype.h>
24#include <asm/tsc.h>
25#include <asm/iommu.h>
26#include <asm/mach_traps.h>
27#include <asm/irqdomain.h>
28#include <asm/realmode.h>
29
30void x86_init_noop(void) { }
31void __init x86_init_uint_noop(unsigned int unused) { }
32static int __init iommu_init_noop(void) { return 0; }
33static void iommu_shutdown_noop(void) { }
34bool __init bool_x86_init_noop(void) { return false; }
35void x86_op_int_noop(int cpu) { }
36int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; }
37void get_rtc_noop(struct timespec64 *now) { }
38
39static __initconst const struct of_device_id of_cmos_match[] = {
40 { .compatible = "motorola,mc146818" },
41 {}
42};
43
44/*
45 * Allow devicetree configured systems to disable the RTC by setting the
46 * corresponding DT node's status property to disabled. Code is optimized
47 * out for CONFIG_OF=n builds.
48 */
49static __init void x86_wallclock_init(void)
50{
51 struct device_node *node = of_find_matching_node(NULL, of_cmos_match);
52
53 if (node && !of_device_is_available(node)) {
54 x86_platform.get_wallclock = get_rtc_noop;
55 x86_platform.set_wallclock = set_rtc_noop;
56 }
57}
58
59/*
60 * The platform setup functions are preset with the default functions
61 * for standard PC hardware.
62 */
63struct x86_init_ops x86_init __initdata = {
64
65 .resources = {
66 .probe_roms = probe_roms,
67 .reserve_resources = reserve_standard_io_resources,
68 .memory_setup = e820__memory_setup_default,
69 },
70
71 .mpparse = {
72 .setup_ioapic_ids = x86_init_noop,
73 .find_smp_config = default_find_smp_config,
74 .get_smp_config = default_get_smp_config,
75 },
76
77 .irqs = {
78 .pre_vector_init = init_ISA_irqs,
79 .intr_init = native_init_IRQ,
80 .intr_mode_select = apic_intr_mode_select,
81 .intr_mode_init = apic_intr_mode_init,
82 .create_pci_msi_domain = native_create_pci_msi_domain,
83 },
84
85 .oem = {
86 .arch_setup = x86_init_noop,
87 .banner = default_banner,
88 },
89
90 .paging = {
91 .pagetable_init = native_pagetable_init,
92 },
93
94 .timers = {
95 .setup_percpu_clockev = setup_boot_APIC_clock,
96 .timer_init = hpet_time_init,
97 .wallclock_init = x86_wallclock_init,
98 },
99
100 .iommu = {
101 .iommu_init = iommu_init_noop,
102 },
103
104 .pci = {
105 .init = x86_default_pci_init,
106 .init_irq = x86_default_pci_init_irq,
107 .fixup_irqs = x86_default_pci_fixup_irqs,
108 },
109
110 .hyper = {
111 .init_platform = x86_init_noop,
112 .guest_late_init = x86_init_noop,
113 .x2apic_available = bool_x86_init_noop,
114 .msi_ext_dest_id = bool_x86_init_noop,
115 .init_mem_mapping = x86_init_noop,
116 .init_after_bootmem = x86_init_noop,
117 },
118
119 .acpi = {
120 .set_root_pointer = x86_default_set_root_pointer,
121 .get_root_pointer = x86_default_get_root_pointer,
122 .reduced_hw_early_init = acpi_generic_reduced_hw_init,
123 },
124};
125
126struct x86_cpuinit_ops x86_cpuinit = {
127 .early_percpu_clock_init = x86_init_noop,
128 .setup_percpu_clockev = setup_secondary_APIC_clock,
129 .parallel_bringup = true,
130};
131
132static void default_nmi_init(void) { };
133
134static bool enc_status_change_prepare_noop(unsigned long vaddr, int npages, bool enc) { return true; }
135static bool enc_status_change_finish_noop(unsigned long vaddr, int npages, bool enc) { return true; }
136static bool enc_tlb_flush_required_noop(bool enc) { return false; }
137static bool enc_cache_flush_required_noop(void) { return false; }
138static bool is_private_mmio_noop(u64 addr) {return false; }
139
140struct x86_platform_ops x86_platform __ro_after_init = {
141 .calibrate_cpu = native_calibrate_cpu_early,
142 .calibrate_tsc = native_calibrate_tsc,
143 .get_wallclock = mach_get_cmos_time,
144 .set_wallclock = mach_set_cmos_time,
145 .iommu_shutdown = iommu_shutdown_noop,
146 .is_untracked_pat_range = is_ISA_range,
147 .nmi_init = default_nmi_init,
148 .get_nmi_reason = default_get_nmi_reason,
149 .save_sched_clock_state = tsc_save_sched_clock_state,
150 .restore_sched_clock_state = tsc_restore_sched_clock_state,
151 .realmode_reserve = reserve_real_mode,
152 .realmode_init = init_real_mode,
153 .hyper.pin_vcpu = x86_op_int_noop,
154 .hyper.is_private_mmio = is_private_mmio_noop,
155
156 .guest = {
157 .enc_status_change_prepare = enc_status_change_prepare_noop,
158 .enc_status_change_finish = enc_status_change_finish_noop,
159 .enc_tlb_flush_required = enc_tlb_flush_required_noop,
160 .enc_cache_flush_required = enc_cache_flush_required_noop,
161 },
162};
163
164EXPORT_SYMBOL_GPL(x86_platform);
165
166struct x86_apic_ops x86_apic_ops __ro_after_init = {
167 .io_apic_read = native_io_apic_read,
168 .restore = native_restore_boot_irq_mode,
169};