1// SPDX-License-Identifier: GPL-2.0
   2//
   3// mcp251xfd - Microchip MCP251xFD Family CAN controller driver
   4//
   5// Copyright (c) 2019, 2020, 2021 Pengutronix,
   6//               Marc Kleine-Budde <kernel@pengutronix.de>
   7//
   8// Based on:
   9//
  10// CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface
  11//
  12// Copyright (c) 2019 Martin Sperl <kernel@martin.sperl.org>
  13//
  14
  15#include <asm/unaligned.h>
  16#include <linux/bitfield.h>
  17#include <linux/clk.h>
  18#include <linux/device.h>
  19#include <linux/mod_devicetable.h>
  20#include <linux/module.h>
  21#include <linux/pm_runtime.h>
  22#include <linux/property.h>
  23
  24#include "mcp251xfd.h"
  25
  26#define DEVICE_NAME "mcp251xfd"
  27
  28static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2517fd = {
  29	.quirks = MCP251XFD_QUIRK_MAB_NO_WARN | MCP251XFD_QUIRK_CRC_REG |
  30		MCP251XFD_QUIRK_CRC_RX | MCP251XFD_QUIRK_CRC_TX |
  31		MCP251XFD_QUIRK_ECC,
  32	.model = MCP251XFD_MODEL_MCP2517FD,
  33};
  34
  35static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp2518fd = {
  36	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
  37		MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
  38	.model = MCP251XFD_MODEL_MCP2518FD,
  39};
  40
  41static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251863 = {
  42	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
  43		MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
  44	.model = MCP251XFD_MODEL_MCP251863,
  45};
  46
  47/* Autodetect model, start with CRC enabled. */
  48static const struct mcp251xfd_devtype_data mcp251xfd_devtype_data_mcp251xfd = {
  49	.quirks = MCP251XFD_QUIRK_CRC_REG | MCP251XFD_QUIRK_CRC_RX |
  50		MCP251XFD_QUIRK_CRC_TX | MCP251XFD_QUIRK_ECC,
  51	.model = MCP251XFD_MODEL_MCP251XFD,
  52};
  53
  54static const struct can_bittiming_const mcp251xfd_bittiming_const = {
  55	.name = DEVICE_NAME,
  56	.tseg1_min = 2,
  57	.tseg1_max = 256,
  58	.tseg2_min = 1,
  59	.tseg2_max = 128,
  60	.sjw_max = 128,
  61	.brp_min = 1,
  62	.brp_max = 256,
  63	.brp_inc = 1,
  64};
  65
  66static const struct can_bittiming_const mcp251xfd_data_bittiming_const = {
  67	.name = DEVICE_NAME,
  68	.tseg1_min = 1,
  69	.tseg1_max = 32,
  70	.tseg2_min = 1,
  71	.tseg2_max = 16,
  72	.sjw_max = 16,
  73	.brp_min = 1,
  74	.brp_max = 256,
  75	.brp_inc = 1,
  76};
  77
  78static const char *__mcp251xfd_get_model_str(enum mcp251xfd_model model)
  79{
  80	switch (model) {
  81	case MCP251XFD_MODEL_MCP2517FD:
  82		return "MCP2517FD";
  83	case MCP251XFD_MODEL_MCP2518FD:
  84		return "MCP2518FD";
  85	case MCP251XFD_MODEL_MCP251863:
  86		return "MCP251863";
  87	case MCP251XFD_MODEL_MCP251XFD:
  88		return "MCP251xFD";
  89	}
  90
  91	return "<unknown>";
  92}
  93
  94static inline const char *
  95mcp251xfd_get_model_str(const struct mcp251xfd_priv *priv)
  96{
  97	return __mcp251xfd_get_model_str(priv->devtype_data.model);
  98}
  99
 100static const char *mcp251xfd_get_mode_str(const u8 mode)
 101{
 102	switch (mode) {
 103	case MCP251XFD_REG_CON_MODE_MIXED:
 104		return "Mixed (CAN FD/CAN 2.0)";
 105	case MCP251XFD_REG_CON_MODE_SLEEP:
 106		return "Sleep";
 107	case MCP251XFD_REG_CON_MODE_INT_LOOPBACK:
 108		return "Internal Loopback";
 109	case MCP251XFD_REG_CON_MODE_LISTENONLY:
 110		return "Listen Only";
 111	case MCP251XFD_REG_CON_MODE_CONFIG:
 112		return "Configuration";
 113	case MCP251XFD_REG_CON_MODE_EXT_LOOPBACK:
 114		return "External Loopback";
 115	case MCP251XFD_REG_CON_MODE_CAN2_0:
 116		return "CAN 2.0";
 117	case MCP251XFD_REG_CON_MODE_RESTRICTED:
 118		return "Restricted Operation";
 119	}
 120
 121	return "<unknown>";
 122}
 123
 124static const char *
 125mcp251xfd_get_osc_str(const u32 osc, const u32 osc_reference)
 126{
 127	switch (~osc & osc_reference &
 128		(MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY)) {
 129	case MCP251XFD_REG_OSC_PLLRDY:
 130		return "PLL";
 131	case MCP251XFD_REG_OSC_OSCRDY:
 132		return "Oscillator";
 133	case MCP251XFD_REG_OSC_PLLRDY | MCP251XFD_REG_OSC_OSCRDY:
 134		return "Oscillator/PLL";
 135	}
 136
 137	return "<unknown>";
 138}
 139
 140static inline int mcp251xfd_vdd_enable(const struct mcp251xfd_priv *priv)
 141{
 142	if (!priv->reg_vdd)
 143		return 0;
 144
 145	return regulator_enable(priv->reg_vdd);
 146}
 147
 148static inline int mcp251xfd_vdd_disable(const struct mcp251xfd_priv *priv)
 149{
 150	if (!priv->reg_vdd)
 151		return 0;
 152
 153	return regulator_disable(priv->reg_vdd);
 154}
 155
 156static inline int
 157mcp251xfd_transceiver_enable(const struct mcp251xfd_priv *priv)
 158{
 159	if (!priv->reg_xceiver)
 160		return 0;
 161
 162	return regulator_enable(priv->reg_xceiver);
 163}
 164
 165static inline int
 166mcp251xfd_transceiver_disable(const struct mcp251xfd_priv *priv)
 167{
 168	if (!priv->reg_xceiver)
 169		return 0;
 170
 171	return regulator_disable(priv->reg_xceiver);
 172}
 173
 174static int mcp251xfd_clks_and_vdd_enable(const struct mcp251xfd_priv *priv)
 175{
 176	int err;
 177
 178	err = clk_prepare_enable(priv->clk);
 179	if (err)
 180		return err;
 181
 182	err = mcp251xfd_vdd_enable(priv);
 183	if (err)
 184		clk_disable_unprepare(priv->clk);
 185
 186	/* Wait for oscillator stabilisation time after power up */
 187	usleep_range(MCP251XFD_OSC_STAB_SLEEP_US,
 188		     2 * MCP251XFD_OSC_STAB_SLEEP_US);
 189
 190	return err;
 191}
 192
 193static int mcp251xfd_clks_and_vdd_disable(const struct mcp251xfd_priv *priv)
 194{
 195	int err;
 196
 197	err = mcp251xfd_vdd_disable(priv);
 198	if (err)
 199		return err;
 200
 201	clk_disable_unprepare(priv->clk);
 202
 203	return 0;
 204}
 205
 206static inline bool mcp251xfd_reg_invalid(u32 reg)
 207{
 208	return reg == 0x0 || reg == 0xffffffff;
 209}
 210
 211static inline int
 212mcp251xfd_chip_get_mode(const struct mcp251xfd_priv *priv, u8 *mode)
 213{
 214	u32 val;
 215	int err;
 216
 217	err = regmap_read(priv->map_reg, MCP251XFD_REG_CON, &val);
 218	if (err)
 219		return err;
 220
 221	*mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, val);
 222
 223	return 0;
 224}
 225
 226static int
 227__mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
 228			  const u8 mode_req, bool nowait)
 229{
 230	const struct can_bittiming *bt = &priv->can.bittiming;
 231	unsigned long timeout_us = MCP251XFD_POLL_TIMEOUT_US;
 232	u32 con = 0, con_reqop, osc = 0;
 233	u8 mode;
 234	int err;
 235
 236	con_reqop = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK, mode_req);
 237	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CON,
 238				 MCP251XFD_REG_CON_REQOP_MASK, con_reqop);
 239	if (err == -EBADMSG) {
 240		netdev_err(priv->ndev,
 241			   "Failed to set Requested Operation Mode.\n");
 242
 243		return -ENODEV;
 244	} else if (err) {
 245		return err;
 246	}
 247
 248	if (mode_req == MCP251XFD_REG_CON_MODE_SLEEP || nowait)
 249		return 0;
 250
 251	if (bt->bitrate)
 252		timeout_us = max_t(unsigned long, timeout_us,
 253				   MCP251XFD_FRAME_LEN_MAX_BITS * USEC_PER_SEC /
 254				   bt->bitrate);
 255
 256	err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_CON, con,
 257				       !mcp251xfd_reg_invalid(con) &&
 258				       FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK,
 259						 con) == mode_req,
 260				       MCP251XFD_POLL_SLEEP_US, timeout_us);
 261	if (err != -ETIMEDOUT && err != -EBADMSG)
 262		return err;
 263
 264	/* Ignore return value.
 265	 * Print below error messages, even if this fails.
 266	 */
 267	regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
 268
 269	if (mcp251xfd_reg_invalid(con)) {
 270		netdev_err(priv->ndev,
 271			   "Failed to read CAN Control Register (con=0x%08x, osc=0x%08x).\n",
 272			   con, osc);
 273
 274		return -ENODEV;
 275	}
 276
 277	mode = FIELD_GET(MCP251XFD_REG_CON_OPMOD_MASK, con);
 278	netdev_err(priv->ndev,
 279		   "Controller failed to enter mode %s Mode (%u) and stays in %s Mode (%u) (con=0x%08x, osc=0x%08x).\n",
 280		   mcp251xfd_get_mode_str(mode_req), mode_req,
 281		   mcp251xfd_get_mode_str(mode), mode,
 282		   con, osc);
 283
 284	return -ETIMEDOUT;
 285}
 286
 287static inline int
 288mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv,
 289			const u8 mode_req)
 290{
 291	return __mcp251xfd_chip_set_mode(priv, mode_req, false);
 292}
 293
 294static inline int __maybe_unused
 295mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv,
 296			       const u8 mode_req)
 297{
 298	return __mcp251xfd_chip_set_mode(priv, mode_req, true);
 299}
 300
 301static int
 302mcp251xfd_chip_wait_for_osc_ready(const struct mcp251xfd_priv *priv,
 303				  u32 osc_reference, u32 osc_mask)
 304{
 305	u32 osc;
 306	int err;
 307
 308	err = regmap_read_poll_timeout(priv->map_reg, MCP251XFD_REG_OSC, osc,
 309				       !mcp251xfd_reg_invalid(osc) &&
 310				       (osc & osc_mask) == osc_reference,
 311				       MCP251XFD_OSC_STAB_SLEEP_US,
 312				       MCP251XFD_OSC_STAB_TIMEOUT_US);
 313	if (err != -ETIMEDOUT)
 314		return err;
 315
 316	if (mcp251xfd_reg_invalid(osc)) {
 317		netdev_err(priv->ndev,
 318			   "Failed to read Oscillator Configuration Register (osc=0x%08x).\n",
 319			   osc);
 320		return -ENODEV;
 321	}
 322
 323	netdev_err(priv->ndev,
 324		   "Timeout waiting for %s ready (osc=0x%08x, osc_reference=0x%08x, osc_mask=0x%08x).\n",
 325		   mcp251xfd_get_osc_str(osc, osc_reference),
 326		   osc, osc_reference, osc_mask);
 327
 328	return -ETIMEDOUT;
 329}
 330
 331static int mcp251xfd_chip_wake(const struct mcp251xfd_priv *priv)
 332{
 333	u32 osc, osc_reference, osc_mask;
 334	int err;
 335
 336	/* For normal sleep on MCP2517FD and MCP2518FD, clearing
 337	 * "Oscillator Disable" will wake the chip. For low power mode
 338	 * on MCP2518FD, asserting the chip select will wake the
 339	 * chip. Writing to the Oscillator register will wake it in
 340	 * both cases.
 341	 */
 342	osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
 343			 MCP251XFD_REG_OSC_CLKODIV_10);
 344
 345	/* We cannot check for the PLL ready bit (either set or
 346	 * unset), as the PLL might be enabled. This can happen if the
 347	 * system reboots, while the mcp251xfd stays powered.
 348	 */
 349	osc_reference = MCP251XFD_REG_OSC_OSCRDY;
 350	osc_mask = MCP251XFD_REG_OSC_OSCRDY;
 351
 352	/* If the controller is in Sleep Mode the following write only
 353	 * removes the "Oscillator Disable" bit and powers it up. All
 354	 * other bits are unaffected.
 355	 */
 356	err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
 357	if (err)
 358		return err;
 359
 360	/* Sometimes the PLL is stuck enabled, the controller never
 361	 * sets the OSC Ready bit, and we get an -ETIMEDOUT. Our
 362	 * caller takes care of retry.
 363	 */
 364	return mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
 365}
 366
 367static inline int mcp251xfd_chip_sleep(const struct mcp251xfd_priv *priv)
 368{
 369	if (priv->pll_enable) {
 370		u32 osc;
 371		int err;
 372
 373		/* Turn off PLL */
 374		osc = FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
 375				 MCP251XFD_REG_OSC_CLKODIV_10);
 376		err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
 377		if (err)
 378			netdev_err(priv->ndev,
 379				   "Failed to disable PLL.\n");
 380
 381		priv->spi->max_speed_hz = priv->spi_max_speed_hz_slow;
 382	}
 383
 384	return mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_SLEEP);
 385}
 386
 387static int mcp251xfd_chip_softreset_do(const struct mcp251xfd_priv *priv)
 388{
 389	const __be16 cmd = mcp251xfd_cmd_reset();
 390	int err;
 391
 392	/* The Set Mode and SPI Reset command only works if the
 393	 * controller is not in Sleep Mode.
 394	 */
 395	err = mcp251xfd_chip_wake(priv);
 396	if (err)
 397		return err;
 398
 399	err = mcp251xfd_chip_set_mode(priv, MCP251XFD_REG_CON_MODE_CONFIG);
 400	if (err)
 401		return err;
 402
 403	/* spi_write_then_read() works with non DMA-safe buffers */
 404	return spi_write_then_read(priv->spi, &cmd, sizeof(cmd), NULL, 0);
 405}
 406
 407static int mcp251xfd_chip_softreset_check(const struct mcp251xfd_priv *priv)
 408{
 409	u32 osc_reference, osc_mask;
 410	u8 mode;
 411	int err;
 412
 413	/* Check for reset defaults of OSC reg.
 414	 * This will take care of stabilization period.
 415	 */
 416	osc_reference = MCP251XFD_REG_OSC_OSCRDY |
 417		FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
 418			   MCP251XFD_REG_OSC_CLKODIV_10);
 419	osc_mask = osc_reference | MCP251XFD_REG_OSC_PLLRDY;
 420	err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
 421	if (err)
 422		return err;
 423
 424	err = mcp251xfd_chip_get_mode(priv, &mode);
 425	if (err)
 426		return err;
 427
 428	if (mode != MCP251XFD_REG_CON_MODE_CONFIG) {
 429		netdev_info(priv->ndev,
 430			    "Controller not in Config Mode after reset, but in %s Mode (%u).\n",
 431			    mcp251xfd_get_mode_str(mode), mode);
 432		return -ETIMEDOUT;
 433	}
 434
 435	return 0;
 436}
 437
 438static int mcp251xfd_chip_softreset(const struct mcp251xfd_priv *priv)
 439{
 440	int err, i;
 441
 442	for (i = 0; i < MCP251XFD_SOFTRESET_RETRIES_MAX; i++) {
 443		if (i)
 444			netdev_info(priv->ndev,
 445				    "Retrying to reset controller.\n");
 446
 447		err = mcp251xfd_chip_softreset_do(priv);
 448		if (err == -ETIMEDOUT)
 449			continue;
 450		if (err)
 451			return err;
 452
 453		err = mcp251xfd_chip_softreset_check(priv);
 454		if (err == -ETIMEDOUT)
 455			continue;
 456		if (err)
 457			return err;
 458
 459		return 0;
 460	}
 461
 462	return err;
 463}
 464
 465static int mcp251xfd_chip_clock_init(const struct mcp251xfd_priv *priv)
 466{
 467	u32 osc, osc_reference, osc_mask;
 468	int err;
 469
 470	/* Activate Low Power Mode on Oscillator Disable. This only
 471	 * works on the MCP2518FD. The MCP2517FD will go into normal
 472	 * Sleep Mode instead.
 473	 */
 474	osc = MCP251XFD_REG_OSC_LPMEN |
 475		FIELD_PREP(MCP251XFD_REG_OSC_CLKODIV_MASK,
 476			   MCP251XFD_REG_OSC_CLKODIV_10);
 477	osc_reference = MCP251XFD_REG_OSC_OSCRDY;
 478	osc_mask = MCP251XFD_REG_OSC_OSCRDY | MCP251XFD_REG_OSC_PLLRDY;
 479
 480	if (priv->pll_enable) {
 481		osc |= MCP251XFD_REG_OSC_PLLEN;
 482		osc_reference |= MCP251XFD_REG_OSC_PLLRDY;
 483	}
 484
 485	err = regmap_write(priv->map_reg, MCP251XFD_REG_OSC, osc);
 486	if (err)
 487		return err;
 488
 489	err = mcp251xfd_chip_wait_for_osc_ready(priv, osc_reference, osc_mask);
 490	if (err)
 491		return err;
 492
 493	priv->spi->max_speed_hz = priv->spi_max_speed_hz_fast;
 494
 495	return 0;
 496}
 497
 498static int mcp251xfd_chip_timestamp_init(const struct mcp251xfd_priv *priv)
 499{
 500	/* Set Time Base Counter Prescaler to 1.
 501	 *
 502	 * This means an overflow of the 32 bit Time Base Counter
 503	 * register at 40 MHz every 107 seconds.
 504	 */
 505	return regmap_write(priv->map_reg, MCP251XFD_REG_TSCON,
 506			    MCP251XFD_REG_TSCON_TBCEN);
 507}
 508
 509static int mcp251xfd_set_bittiming(const struct mcp251xfd_priv *priv)
 510{
 511	const struct can_bittiming *bt = &priv->can.bittiming;
 512	const struct can_bittiming *dbt = &priv->can.data_bittiming;
 513	u32 val = 0;
 514	s8 tdco;
 515	int err;
 516
 517	/* CAN Control Register
 518	 *
 519	 * - no transmit bandwidth sharing
 520	 * - config mode
 521	 * - disable transmit queue
 522	 * - store in transmit FIFO event
 523	 * - transition to restricted operation mode on system error
 524	 * - ESI is transmitted recessive when ESI of message is high or
 525	 *   CAN controller error passive
 526	 * - restricted retransmission attempts,
 527	 *   use TQXCON_TXAT and FIFOCON_TXAT
 528	 * - wake-up filter bits T11FILTER
 529	 * - use CAN bus line filter for wakeup
 530	 * - protocol exception is treated as a form error
 531	 * - Do not compare data bytes
 532	 */
 533	val = FIELD_PREP(MCP251XFD_REG_CON_REQOP_MASK,
 534			 MCP251XFD_REG_CON_MODE_CONFIG) |
 535		MCP251XFD_REG_CON_STEF |
 536		MCP251XFD_REG_CON_ESIGM |
 537		MCP251XFD_REG_CON_RTXAT |
 538		FIELD_PREP(MCP251XFD_REG_CON_WFT_MASK,
 539			   MCP251XFD_REG_CON_WFT_T11FILTER) |
 540		MCP251XFD_REG_CON_WAKFIL |
 541		MCP251XFD_REG_CON_PXEDIS;
 542
 543	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO))
 544		val |= MCP251XFD_REG_CON_ISOCRCEN;
 545
 546	err = regmap_write(priv->map_reg, MCP251XFD_REG_CON, val);
 547	if (err)
 548		return err;
 549
 550	/* Nominal Bit Time */
 551	val = FIELD_PREP(MCP251XFD_REG_NBTCFG_BRP_MASK, bt->brp - 1) |
 552		FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG1_MASK,
 553			   bt->prop_seg + bt->phase_seg1 - 1) |
 554		FIELD_PREP(MCP251XFD_REG_NBTCFG_TSEG2_MASK,
 555			   bt->phase_seg2 - 1) |
 556		FIELD_PREP(MCP251XFD_REG_NBTCFG_SJW_MASK, bt->sjw - 1);
 557
 558	err = regmap_write(priv->map_reg, MCP251XFD_REG_NBTCFG, val);
 559	if (err)
 560		return err;
 561
 562	if (!(priv->can.ctrlmode & CAN_CTRLMODE_FD))
 563		return 0;
 564
 565	/* Data Bit Time */
 566	val = FIELD_PREP(MCP251XFD_REG_DBTCFG_BRP_MASK, dbt->brp - 1) |
 567		FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG1_MASK,
 568			   dbt->prop_seg + dbt->phase_seg1 - 1) |
 569		FIELD_PREP(MCP251XFD_REG_DBTCFG_TSEG2_MASK,
 570			   dbt->phase_seg2 - 1) |
 571		FIELD_PREP(MCP251XFD_REG_DBTCFG_SJW_MASK, dbt->sjw - 1);
 572
 573	err = regmap_write(priv->map_reg, MCP251XFD_REG_DBTCFG, val);
 574	if (err)
 575		return err;
 576
 577	/* Transmitter Delay Compensation */
 578	tdco = clamp_t(int, dbt->brp * (dbt->prop_seg + dbt->phase_seg1),
 579		       -64, 63);
 580	val = FIELD_PREP(MCP251XFD_REG_TDC_TDCMOD_MASK,
 581			 MCP251XFD_REG_TDC_TDCMOD_AUTO) |
 582		FIELD_PREP(MCP251XFD_REG_TDC_TDCO_MASK, tdco);
 583
 584	return regmap_write(priv->map_reg, MCP251XFD_REG_TDC, val);
 585}
 586
 587static int mcp251xfd_chip_rx_int_enable(const struct mcp251xfd_priv *priv)
 588{
 589	u32 val;
 590
 591	if (!priv->rx_int)
 592		return 0;
 593
 594	/* Configure GPIOs:
 595	 * - PIN0: GPIO Input
 596	 * - PIN1: GPIO Input/RX Interrupt
 597	 *
 598	 * PIN1 must be Input, otherwise there is a glitch on the
 599	 * rx-INT line. It happens between setting the PIN as output
 600	 * (in the first byte of the SPI transfer) and configuring the
 601	 * PIN as interrupt (in the last byte of the SPI transfer).
 602	 */
 603	val = MCP251XFD_REG_IOCON_PM0 | MCP251XFD_REG_IOCON_TRIS1 |
 604		MCP251XFD_REG_IOCON_TRIS0;
 605	return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
 606}
 607
 608static int mcp251xfd_chip_rx_int_disable(const struct mcp251xfd_priv *priv)
 609{
 610	u32 val;
 611
 612	if (!priv->rx_int)
 613		return 0;
 614
 615	/* Configure GPIOs:
 616	 * - PIN0: GPIO Input
 617	 * - PIN1: GPIO Input
 618	 */
 619	val = MCP251XFD_REG_IOCON_PM1 | MCP251XFD_REG_IOCON_PM0 |
 620		MCP251XFD_REG_IOCON_TRIS1 | MCP251XFD_REG_IOCON_TRIS0;
 621	return regmap_write(priv->map_reg, MCP251XFD_REG_IOCON, val);
 622}
 623
 624static int mcp251xfd_chip_ecc_init(struct mcp251xfd_priv *priv)
 625{
 626	struct mcp251xfd_ecc *ecc = &priv->ecc;
 627	void *ram;
 628	u32 val = 0;
 629	int err;
 630
 631	ecc->ecc_stat = 0;
 632
 633	if (priv->devtype_data.quirks & MCP251XFD_QUIRK_ECC)
 634		val = MCP251XFD_REG_ECCCON_ECCEN;
 635
 636	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
 637				 MCP251XFD_REG_ECCCON_ECCEN, val);
 638	if (err)
 639		return err;
 640
 641	ram = kzalloc(MCP251XFD_RAM_SIZE, GFP_KERNEL);
 642	if (!ram)
 643		return -ENOMEM;
 644
 645	err = regmap_raw_write(priv->map_reg, MCP251XFD_RAM_START, ram,
 646			       MCP251XFD_RAM_SIZE);
 647	kfree(ram);
 648
 649	return err;
 650}
 651
 652static u8 mcp251xfd_get_normal_mode(const struct mcp251xfd_priv *priv)
 653{
 654	u8 mode;
 655
 656	if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)
 657		mode = MCP251XFD_REG_CON_MODE_INT_LOOPBACK;
 658	else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
 659		mode = MCP251XFD_REG_CON_MODE_LISTENONLY;
 660	else if (priv->can.ctrlmode & CAN_CTRLMODE_FD)
 661		mode = MCP251XFD_REG_CON_MODE_MIXED;
 662	else
 663		mode = MCP251XFD_REG_CON_MODE_CAN2_0;
 664
 665	return mode;
 666}
 667
 668static int
 669__mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv,
 670				 bool nowait)
 671{
 672	u8 mode;
 673
 674	mode = mcp251xfd_get_normal_mode(priv);
 675
 676	return __mcp251xfd_chip_set_mode(priv, mode, nowait);
 677}
 678
 679static inline int
 680mcp251xfd_chip_set_normal_mode(const struct mcp251xfd_priv *priv)
 681{
 682	return __mcp251xfd_chip_set_normal_mode(priv, false);
 683}
 684
 685static inline int
 686mcp251xfd_chip_set_normal_mode_nowait(const struct mcp251xfd_priv *priv)
 687{
 688	return __mcp251xfd_chip_set_normal_mode(priv, true);
 689}
 690
 691static int mcp251xfd_chip_interrupts_enable(const struct mcp251xfd_priv *priv)
 692{
 693	u32 val;
 694	int err;
 695
 696	val = MCP251XFD_REG_CRC_FERRIE | MCP251XFD_REG_CRC_CRCERRIE;
 697	err = regmap_write(priv->map_reg, MCP251XFD_REG_CRC, val);
 698	if (err)
 699		return err;
 700
 701	val = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
 702	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON, val, val);
 703	if (err)
 704		return err;
 705
 706	val = MCP251XFD_REG_INT_CERRIE |
 707		MCP251XFD_REG_INT_SERRIE |
 708		MCP251XFD_REG_INT_RXOVIE |
 709		MCP251XFD_REG_INT_TXATIE |
 710		MCP251XFD_REG_INT_SPICRCIE |
 711		MCP251XFD_REG_INT_ECCIE |
 712		MCP251XFD_REG_INT_TEFIE |
 713		MCP251XFD_REG_INT_MODIE |
 714		MCP251XFD_REG_INT_RXIE;
 715
 716	if (priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)
 717		val |= MCP251XFD_REG_INT_IVMIE;
 718
 719	return regmap_write(priv->map_reg, MCP251XFD_REG_INT, val);
 720}
 721
 722static int mcp251xfd_chip_interrupts_disable(const struct mcp251xfd_priv *priv)
 723{
 724	int err;
 725	u32 mask;
 726
 727	err = regmap_write(priv->map_reg, MCP251XFD_REG_INT, 0);
 728	if (err)
 729		return err;
 730
 731	mask = MCP251XFD_REG_ECCCON_DEDIE | MCP251XFD_REG_ECCCON_SECIE;
 732	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCCON,
 733				 mask, 0x0);
 734	if (err)
 735		return err;
 736
 737	return regmap_write(priv->map_reg, MCP251XFD_REG_CRC, 0);
 738}
 739
 740static void mcp251xfd_chip_stop(struct mcp251xfd_priv *priv,
 741				const enum can_state state)
 742{
 743	priv->can.state = state;
 744
 745	mcp251xfd_chip_interrupts_disable(priv);
 746	mcp251xfd_chip_rx_int_disable(priv);
 747	mcp251xfd_chip_sleep(priv);
 748}
 749
 750static int mcp251xfd_chip_start(struct mcp251xfd_priv *priv)
 751{
 752	int err;
 753
 754	err = mcp251xfd_chip_softreset(priv);
 755	if (err)
 756		goto out_chip_stop;
 757
 758	err = mcp251xfd_chip_clock_init(priv);
 759	if (err)
 760		goto out_chip_stop;
 761
 762	err = mcp251xfd_chip_timestamp_init(priv);
 763	if (err)
 764		goto out_chip_stop;
 765
 766	err = mcp251xfd_set_bittiming(priv);
 767	if (err)
 768		goto out_chip_stop;
 769
 770	err = mcp251xfd_chip_rx_int_enable(priv);
 771	if (err)
 772		goto out_chip_stop;
 773
 774	err = mcp251xfd_chip_ecc_init(priv);
 775	if (err)
 776		goto out_chip_stop;
 777
 778	err = mcp251xfd_ring_init(priv);
 779	if (err)
 780		goto out_chip_stop;
 781
 782	err = mcp251xfd_chip_fifo_init(priv);
 783	if (err)
 784		goto out_chip_stop;
 785
 786	priv->can.state = CAN_STATE_ERROR_ACTIVE;
 787
 788	err = mcp251xfd_chip_set_normal_mode(priv);
 789	if (err)
 790		goto out_chip_stop;
 791
 792	return 0;
 793
 794 out_chip_stop:
 795	mcp251xfd_dump(priv);
 796	mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
 797
 798	return err;
 799}
 800
 801static int mcp251xfd_set_mode(struct net_device *ndev, enum can_mode mode)
 802{
 803	struct mcp251xfd_priv *priv = netdev_priv(ndev);
 804	int err;
 805
 806	switch (mode) {
 807	case CAN_MODE_START:
 808		err = mcp251xfd_chip_start(priv);
 809		if (err)
 810			return err;
 811
 812		err = mcp251xfd_chip_interrupts_enable(priv);
 813		if (err) {
 814			mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
 815			return err;
 816		}
 817
 818		netif_wake_queue(ndev);
 819		break;
 820
 821	default:
 822		return -EOPNOTSUPP;
 823	}
 824
 825	return 0;
 826}
 827
 828static int __mcp251xfd_get_berr_counter(const struct net_device *ndev,
 829					struct can_berr_counter *bec)
 830{
 831	const struct mcp251xfd_priv *priv = netdev_priv(ndev);
 832	u32 trec;
 833	int err;
 834
 835	err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
 836	if (err)
 837		return err;
 838
 839	if (trec & MCP251XFD_REG_TREC_TXBO)
 840		bec->txerr = CAN_BUS_OFF_THRESHOLD;
 841	else
 842		bec->txerr = FIELD_GET(MCP251XFD_REG_TREC_TEC_MASK, trec);
 843	bec->rxerr = FIELD_GET(MCP251XFD_REG_TREC_REC_MASK, trec);
 844
 845	return 0;
 846}
 847
 848static int mcp251xfd_get_berr_counter(const struct net_device *ndev,
 849				      struct can_berr_counter *bec)
 850{
 851	const struct mcp251xfd_priv *priv = netdev_priv(ndev);
 852
 853	/* Avoid waking up the controller if the interface is down */
 854	if (!(ndev->flags & IFF_UP))
 855		return 0;
 856
 857	/* The controller is powered down during Bus Off, use saved
 858	 * bec values.
 859	 */
 860	if (priv->can.state == CAN_STATE_BUS_OFF) {
 861		*bec = priv->bec;
 862		return 0;
 863	}
 864
 865	return __mcp251xfd_get_berr_counter(ndev, bec);
 866}
 867
 868static struct sk_buff *
 869mcp251xfd_alloc_can_err_skb(struct mcp251xfd_priv *priv,
 870			    struct can_frame **cf, u32 *timestamp)
 871{
 872	struct sk_buff *skb;
 873	int err;
 874
 875	err = mcp251xfd_get_timestamp(priv, timestamp);
 876	if (err)
 877		return NULL;
 878
 879	skb = alloc_can_err_skb(priv->ndev, cf);
 880	if (skb)
 881		mcp251xfd_skb_set_timestamp(priv, skb, *timestamp);
 882
 883	return skb;
 884}
 885
 886static int mcp251xfd_handle_rxovif(struct mcp251xfd_priv *priv)
 887{
 888	struct net_device_stats *stats = &priv->ndev->stats;
 889	struct mcp251xfd_rx_ring *ring;
 890	struct sk_buff *skb;
 891	struct can_frame *cf;
 892	u32 timestamp, rxovif;
 893	int err, i;
 894
 895	stats->rx_over_errors++;
 896	stats->rx_errors++;
 897
 898	err = regmap_read(priv->map_reg, MCP251XFD_REG_RXOVIF, &rxovif);
 899	if (err)
 900		return err;
 901
 902	mcp251xfd_for_each_rx_ring(priv, ring, i) {
 903		if (!(rxovif & BIT(ring->fifo_nr)))
 904			continue;
 905
 906		/* If SERRIF is active, there was a RX MAB overflow. */
 907		if (priv->regs_status.intf & MCP251XFD_REG_INT_SERRIF) {
 908			if (net_ratelimit())
 909				netdev_dbg(priv->ndev,
 910					   "RX-%d: MAB overflow detected.\n",
 911					   ring->nr);
 912		} else {
 913			if (net_ratelimit())
 914				netdev_dbg(priv->ndev,
 915					   "RX-%d: FIFO overflow.\n",
 916					   ring->nr);
 917		}
 918
 919		err = regmap_update_bits(priv->map_reg,
 920					 MCP251XFD_REG_FIFOSTA(ring->fifo_nr),
 921					 MCP251XFD_REG_FIFOSTA_RXOVIF,
 922					 0x0);
 923		if (err)
 924			return err;
 925	}
 926
 927	skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &timestamp);
 928	if (!skb)
 929		return 0;
 930
 931	cf->can_id |= CAN_ERR_CRTL;
 932	cf->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
 933
 934	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
 935	if (err)
 936		stats->rx_fifo_errors++;
 937
 938	return 0;
 939}
 940
 941static int mcp251xfd_handle_txatif(struct mcp251xfd_priv *priv)
 942{
 943	netdev_info(priv->ndev, "%s\n", __func__);
 944
 945	return 0;
 946}
 947
 948static int mcp251xfd_handle_ivmif(struct mcp251xfd_priv *priv)
 949{
 950	struct net_device_stats *stats = &priv->ndev->stats;
 951	u32 bdiag1, timestamp;
 952	struct sk_buff *skb;
 953	struct can_frame *cf = NULL;
 954	int err;
 955
 956	err = mcp251xfd_get_timestamp(priv, &timestamp);
 957	if (err)
 958		return err;
 959
 960	err = regmap_read(priv->map_reg, MCP251XFD_REG_BDIAG1, &bdiag1);
 961	if (err)
 962		return err;
 963
 964	/* Write 0s to clear error bits, don't write 1s to non active
 965	 * bits, as they will be set.
 966	 */
 967	err = regmap_write(priv->map_reg, MCP251XFD_REG_BDIAG1, 0x0);
 968	if (err)
 969		return err;
 970
 971	priv->can.can_stats.bus_error++;
 972
 973	skb = alloc_can_err_skb(priv->ndev, &cf);
 974	if (cf)
 975		cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
 976
 977	/* Controller misconfiguration */
 978	if (WARN_ON(bdiag1 & MCP251XFD_REG_BDIAG1_DLCMM))
 979		netdev_err(priv->ndev,
 980			   "recv'd DLC is larger than PLSIZE of FIFO element.");
 981
 982	/* RX errors */
 983	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DCRCERR |
 984		      MCP251XFD_REG_BDIAG1_NCRCERR)) {
 985		netdev_dbg(priv->ndev, "CRC error\n");
 986
 987		stats->rx_errors++;
 988		if (cf)
 989			cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
 990	}
 991	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DSTUFERR |
 992		      MCP251XFD_REG_BDIAG1_NSTUFERR)) {
 993		netdev_dbg(priv->ndev, "Stuff error\n");
 994
 995		stats->rx_errors++;
 996		if (cf)
 997			cf->data[2] |= CAN_ERR_PROT_STUFF;
 998	}
 999	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DFORMERR |
1000		      MCP251XFD_REG_BDIAG1_NFORMERR)) {
1001		netdev_dbg(priv->ndev, "Format error\n");
1002
1003		stats->rx_errors++;
1004		if (cf)
1005			cf->data[2] |= CAN_ERR_PROT_FORM;
1006	}
1007
1008	/* TX errors */
1009	if (bdiag1 & MCP251XFD_REG_BDIAG1_NACKERR) {
1010		netdev_dbg(priv->ndev, "NACK error\n");
1011
1012		stats->tx_errors++;
1013		if (cf) {
1014			cf->can_id |= CAN_ERR_ACK;
1015			cf->data[2] |= CAN_ERR_PROT_TX;
1016		}
1017	}
1018	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT1ERR |
1019		      MCP251XFD_REG_BDIAG1_NBIT1ERR)) {
1020		netdev_dbg(priv->ndev, "Bit1 error\n");
1021
1022		stats->tx_errors++;
1023		if (cf)
1024			cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT1;
1025	}
1026	if (bdiag1 & (MCP251XFD_REG_BDIAG1_DBIT0ERR |
1027		      MCP251XFD_REG_BDIAG1_NBIT0ERR)) {
1028		netdev_dbg(priv->ndev, "Bit0 error\n");
1029
1030		stats->tx_errors++;
1031		if (cf)
1032			cf->data[2] |= CAN_ERR_PROT_TX | CAN_ERR_PROT_BIT0;
1033	}
1034
1035	if (!cf)
1036		return 0;
1037
1038	mcp251xfd_skb_set_timestamp(priv, skb, timestamp);
1039	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1040	if (err)
1041		stats->rx_fifo_errors++;
1042
1043	return 0;
1044}
1045
1046static int mcp251xfd_handle_cerrif(struct mcp251xfd_priv *priv)
1047{
1048	struct net_device_stats *stats = &priv->ndev->stats;
1049	struct sk_buff *skb;
1050	struct can_frame *cf = NULL;
1051	enum can_state new_state, rx_state, tx_state;
1052	u32 trec, timestamp;
1053	int err;
1054
1055	err = regmap_read(priv->map_reg, MCP251XFD_REG_TREC, &trec);
1056	if (err)
1057		return err;
1058
1059	if (trec & MCP251XFD_REG_TREC_TXBO)
1060		tx_state = CAN_STATE_BUS_OFF;
1061	else if (trec & MCP251XFD_REG_TREC_TXBP)
1062		tx_state = CAN_STATE_ERROR_PASSIVE;
1063	else if (trec & MCP251XFD_REG_TREC_TXWARN)
1064		tx_state = CAN_STATE_ERROR_WARNING;
1065	else
1066		tx_state = CAN_STATE_ERROR_ACTIVE;
1067
1068	if (trec & MCP251XFD_REG_TREC_RXBP)
1069		rx_state = CAN_STATE_ERROR_PASSIVE;
1070	else if (trec & MCP251XFD_REG_TREC_RXWARN)
1071		rx_state = CAN_STATE_ERROR_WARNING;
1072	else
1073		rx_state = CAN_STATE_ERROR_ACTIVE;
1074
1075	new_state = max(tx_state, rx_state);
1076	if (new_state == priv->can.state)
1077		return 0;
1078
1079	/* The skb allocation might fail, but can_change_state()
1080	 * handles cf == NULL.
1081	 */
1082	skb = mcp251xfd_alloc_can_err_skb(priv, &cf, &timestamp);
1083	can_change_state(priv->ndev, cf, tx_state, rx_state);
1084
1085	if (new_state == CAN_STATE_BUS_OFF) {
1086		/* As we're going to switch off the chip now, let's
1087		 * save the error counters and return them to
1088		 * userspace, if do_get_berr_counter() is called while
1089		 * the chip is in Bus Off.
1090		 */
1091		err = __mcp251xfd_get_berr_counter(priv->ndev, &priv->bec);
1092		if (err)
1093			return err;
1094
1095		mcp251xfd_chip_stop(priv, CAN_STATE_BUS_OFF);
1096		can_bus_off(priv->ndev);
1097	}
1098
1099	if (!skb)
1100		return 0;
1101
1102	if (new_state != CAN_STATE_BUS_OFF) {
1103		struct can_berr_counter bec;
1104
1105		err = mcp251xfd_get_berr_counter(priv->ndev, &bec);
1106		if (err)
1107			return err;
1108		cf->can_id |= CAN_ERR_CNT;
1109		cf->data[6] = bec.txerr;
1110		cf->data[7] = bec.rxerr;
1111	}
1112
1113	err = can_rx_offload_queue_timestamp(&priv->offload, skb, timestamp);
1114	if (err)
1115		stats->rx_fifo_errors++;
1116
1117	return 0;
1118}
1119
1120static int
1121mcp251xfd_handle_modif(const struct mcp251xfd_priv *priv, bool *set_normal_mode)
1122{
1123	const u8 mode_reference = mcp251xfd_get_normal_mode(priv);
1124	u8 mode;
1125	int err;
1126
1127	err = mcp251xfd_chip_get_mode(priv, &mode);
1128	if (err)
1129		return err;
1130
1131	if (mode == mode_reference) {
1132		netdev_dbg(priv->ndev,
1133			   "Controller changed into %s Mode (%u).\n",
1134			   mcp251xfd_get_mode_str(mode), mode);
1135		return 0;
1136	}
1137
1138	/* According to MCP2517FD errata DS80000792B 1., during a TX
1139	 * MAB underflow, the controller will transition to Restricted
1140	 * Operation Mode or Listen Only Mode (depending on SERR2LOM).
1141	 *
1142	 * However this is not always the case. If SERR2LOM is
1143	 * configured for Restricted Operation Mode (SERR2LOM not set)
1144	 * the MCP2517FD will sometimes transition to Listen Only Mode
1145	 * first. When polling this bit we see that it will transition
1146	 * to Restricted Operation Mode shortly after.
1147	 */
1148	if ((priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN) &&
1149	    (mode == MCP251XFD_REG_CON_MODE_RESTRICTED ||
1150	     mode == MCP251XFD_REG_CON_MODE_LISTENONLY))
1151		netdev_dbg(priv->ndev,
1152			   "Controller changed into %s Mode (%u).\n",
1153			   mcp251xfd_get_mode_str(mode), mode);
1154	else
1155		netdev_err(priv->ndev,
1156			   "Controller changed into %s Mode (%u).\n",
1157			   mcp251xfd_get_mode_str(mode), mode);
1158
1159	/* After the application requests Normal mode, the controller
1160	 * will automatically attempt to retransmit the message that
1161	 * caused the TX MAB underflow.
1162	 *
1163	 * However, if there is an ECC error in the TX-RAM, we first
1164	 * have to reload the tx-object before requesting Normal
1165	 * mode. This is done later in mcp251xfd_handle_eccif().
1166	 */
1167	if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF) {
1168		*set_normal_mode = true;
1169		return 0;
1170	}
1171
1172	return mcp251xfd_chip_set_normal_mode_nowait(priv);
1173}
1174
1175static int mcp251xfd_handle_serrif(struct mcp251xfd_priv *priv)
1176{
1177	struct mcp251xfd_ecc *ecc = &priv->ecc;
1178	struct net_device_stats *stats = &priv->ndev->stats;
1179	bool handled = false;
1180
1181	/* TX MAB underflow
1182	 *
1183	 * According to MCP2517FD Errata DS80000792B 1. a TX MAB
1184	 * underflow is indicated by SERRIF and MODIF.
1185	 *
1186	 * In addition to the effects mentioned in the Errata, there
1187	 * are Bus Errors due to the aborted CAN frame, so a IVMIF
1188	 * will be seen as well.
1189	 *
1190	 * Sometimes there is an ECC error in the TX-RAM, which leads
1191	 * to a TX MAB underflow.
1192	 *
1193	 * However, probably due to a race condition, there is no
1194	 * associated MODIF pending.
1195	 *
1196	 * Further, there are situations, where the SERRIF is caused
1197	 * by an ECC error in the TX-RAM, but not even the ECCIF is
1198	 * set. This only seems to happen _after_ the first occurrence
1199	 * of a ECCIF (which is tracked in ecc->cnt).
1200	 *
1201	 * Treat all as a known system errors..
1202	 */
1203	if ((priv->regs_status.intf & MCP251XFD_REG_INT_MODIF &&
1204	     priv->regs_status.intf & MCP251XFD_REG_INT_IVMIF) ||
1205	    priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1206	    ecc->cnt) {
1207		const char *msg;
1208
1209		if (priv->regs_status.intf & MCP251XFD_REG_INT_ECCIF ||
1210		    ecc->cnt)
1211			msg = "TX MAB underflow due to ECC error detected.";
1212		else
1213			msg = "TX MAB underflow detected.";
1214
1215		if (priv->devtype_data.quirks & MCP251XFD_QUIRK_MAB_NO_WARN)
1216			netdev_dbg(priv->ndev, "%s\n", msg);
1217		else
1218			netdev_info(priv->ndev, "%s\n", msg);
1219
1220		stats->tx_aborted_errors++;
1221		stats->tx_errors++;
1222		handled = true;
1223	}
1224
1225	/* RX MAB overflow
1226	 *
1227	 * According to MCP2517FD Errata DS80000792B 1. a RX MAB
1228	 * overflow is indicated by SERRIF.
1229	 *
1230	 * In addition to the effects mentioned in the Errata, (most
1231	 * of the times) a RXOVIF is raised, if the FIFO that is being
1232	 * received into has the RXOVIE activated (and we have enabled
1233	 * RXOVIE on all FIFOs).
1234	 *
1235	 * Sometimes there is no RXOVIF just a RXIF is pending.
1236	 *
1237	 * Treat all as a known system errors..
1238	 */
1239	if (priv->regs_status.intf & MCP251XFD_REG_INT_RXOVIF ||
1240	    priv->regs_status.intf & MCP251XFD_REG_INT_RXIF) {
1241		stats->rx_dropped++;
1242		handled = true;
1243	}
1244
1245	if (!handled)
1246		netdev_err(priv->ndev,
1247			   "Unhandled System Error Interrupt (intf=0x%08x)!\n",
1248			   priv->regs_status.intf);
1249
1250	return 0;
1251}
1252
1253static int
1254mcp251xfd_handle_eccif_recover(struct mcp251xfd_priv *priv, u8 nr)
1255{
1256	struct mcp251xfd_tx_ring *tx_ring = priv->tx;
1257	struct mcp251xfd_ecc *ecc = &priv->ecc;
1258	struct mcp251xfd_tx_obj *tx_obj;
1259	u8 chip_tx_tail, tx_tail, offset;
1260	u16 addr;
1261	int err;
1262
1263	addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc->ecc_stat);
1264
1265	err = mcp251xfd_tx_tail_get_from_chip(priv, &chip_tx_tail);
1266	if (err)
1267		return err;
1268
1269	tx_tail = mcp251xfd_get_tx_tail(tx_ring);
1270	offset = (nr - chip_tx_tail) & (tx_ring->obj_num - 1);
1271
1272	/* Bail out if one of the following is met:
1273	 * - tx_tail information is inconsistent
1274	 * - for mcp2517fd: offset not 0
1275	 * - for mcp2518fd: offset not 0 or 1
1276	 */
1277	if (chip_tx_tail != tx_tail ||
1278	    !(offset == 0 || (offset == 1 && (mcp251xfd_is_2518FD(priv) ||
1279					      mcp251xfd_is_251863(priv))))) {
1280		netdev_err(priv->ndev,
1281			   "ECC Error information inconsistent (addr=0x%04x, nr=%d, tx_tail=0x%08x(%d), chip_tx_tail=%d, offset=%d).\n",
1282			   addr, nr, tx_ring->tail, tx_tail, chip_tx_tail,
1283			   offset);
1284		return -EINVAL;
1285	}
1286
1287	netdev_info(priv->ndev,
1288		    "Recovering %s ECC Error at address 0x%04x (in TX-RAM, tx_obj=%d, tx_tail=0x%08x(%d), offset=%d).\n",
1289		    ecc->ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF ?
1290		    "Single" : "Double",
1291		    addr, nr, tx_ring->tail, tx_tail, offset);
1292
1293	/* reload tx_obj into controller RAM ... */
1294	tx_obj = &tx_ring->obj[nr];
1295	err = spi_sync_transfer(priv->spi, tx_obj->xfer, 1);
1296	if (err)
1297		return err;
1298
1299	/* ... and trigger retransmit */
1300	return mcp251xfd_chip_set_normal_mode(priv);
1301}
1302
1303static int
1304mcp251xfd_handle_eccif(struct mcp251xfd_priv *priv, bool set_normal_mode)
1305{
1306	struct mcp251xfd_ecc *ecc = &priv->ecc;
1307	const char *msg;
1308	bool in_tx_ram;
1309	u32 ecc_stat;
1310	u16 addr;
1311	u8 nr;
1312	int err;
1313
1314	err = regmap_read(priv->map_reg, MCP251XFD_REG_ECCSTAT, &ecc_stat);
1315	if (err)
1316		return err;
1317
1318	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_ECCSTAT,
1319				 MCP251XFD_REG_ECCSTAT_IF_MASK, ~ecc_stat);
1320	if (err)
1321		return err;
1322
1323	/* Check if ECC error occurred in TX-RAM */
1324	addr = FIELD_GET(MCP251XFD_REG_ECCSTAT_ERRADDR_MASK, ecc_stat);
1325	err = mcp251xfd_get_tx_nr_by_addr(priv->tx, &nr, addr);
1326	if (!err)
1327		in_tx_ram = true;
1328	else if (err == -ENOENT)
1329		in_tx_ram = false;
1330	else
1331		return err;
1332
1333	/* Errata Reference:
1334	 * mcp2517fd: DS80000789B, mcp2518fd: DS80000792C 2.
1335	 *
1336	 * ECC single error correction does not work in all cases:
1337	 *
1338	 * Fix/Work Around:
1339	 * Enable single error correction and double error detection
1340	 * interrupts by setting SECIE and DEDIE. Handle SECIF as a
1341	 * detection interrupt and do not rely on the error
1342	 * correction. Instead, handle both interrupts as a
1343	 * notification that the RAM word at ERRADDR was corrupted.
1344	 */
1345	if (ecc_stat & MCP251XFD_REG_ECCSTAT_SECIF)
1346		msg = "Single ECC Error detected at address";
1347	else if (ecc_stat & MCP251XFD_REG_ECCSTAT_DEDIF)
1348		msg = "Double ECC Error detected at address";
1349	else
1350		return -EINVAL;
1351
1352	if (!in_tx_ram) {
1353		ecc->ecc_stat = 0;
1354
1355		netdev_notice(priv->ndev, "%s 0x%04x.\n", msg, addr);
1356	} else {
1357		/* Re-occurring error? */
1358		if (ecc->ecc_stat == ecc_stat) {
1359			ecc->cnt++;
1360		} else {
1361			ecc->ecc_stat = ecc_stat;
1362			ecc->cnt = 1;
1363		}
1364
1365		netdev_info(priv->ndev,
1366			    "%s 0x%04x (in TX-RAM, tx_obj=%d), occurred %d time%s.\n",
1367			    msg, addr, nr, ecc->cnt, ecc->cnt > 1 ? "s" : "");
1368
1369		if (ecc->cnt >= MCP251XFD_ECC_CNT_MAX)
1370			return mcp251xfd_handle_eccif_recover(priv, nr);
1371	}
1372
1373	if (set_normal_mode)
1374		return mcp251xfd_chip_set_normal_mode_nowait(priv);
1375
1376	return 0;
1377}
1378
1379static int mcp251xfd_handle_spicrcif(struct mcp251xfd_priv *priv)
1380{
1381	int err;
1382	u32 crc;
1383
1384	err = regmap_read(priv->map_reg, MCP251XFD_REG_CRC, &crc);
1385	if (err)
1386		return err;
1387
1388	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_CRC,
1389				 MCP251XFD_REG_CRC_IF_MASK,
1390				 ~crc);
1391	if (err)
1392		return err;
1393
1394	if (crc & MCP251XFD_REG_CRC_FERRIF)
1395		netdev_notice(priv->ndev, "CRC write command format error.\n");
1396	else if (crc & MCP251XFD_REG_CRC_CRCERRIF)
1397		netdev_notice(priv->ndev,
1398			      "CRC write error detected. CRC=0x%04lx.\n",
1399			      FIELD_GET(MCP251XFD_REG_CRC_MASK, crc));
1400
1401	return 0;
1402}
1403
1404static int mcp251xfd_read_regs_status(struct mcp251xfd_priv *priv)
1405{
1406	const int val_bytes = regmap_get_val_bytes(priv->map_reg);
1407	size_t len;
1408
1409	if (priv->rx_ring_num == 1)
1410		len = sizeof(priv->regs_status.intf);
1411	else
1412		len = sizeof(priv->regs_status);
1413
1414	return regmap_bulk_read(priv->map_reg, MCP251XFD_REG_INT,
1415				&priv->regs_status, len / val_bytes);
1416}
1417
1418#define mcp251xfd_handle(priv, irq, ...) \
1419({ \
1420	struct mcp251xfd_priv *_priv = (priv); \
1421	int err; \
1422\
1423	err = mcp251xfd_handle_##irq(_priv, ## __VA_ARGS__); \
1424	if (err) \
1425		netdev_err(_priv->ndev, \
1426			"IRQ handler mcp251xfd_handle_%s() returned %d.\n", \
1427			__stringify(irq), err); \
1428	err; \
1429})
1430
1431static irqreturn_t mcp251xfd_irq(int irq, void *dev_id)
1432{
1433	struct mcp251xfd_priv *priv = dev_id;
1434	irqreturn_t handled = IRQ_NONE;
1435	int err;
1436
1437	if (priv->rx_int)
1438		do {
1439			int rx_pending;
1440
1441			rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1442			if (!rx_pending)
1443				break;
1444
1445			/* Assume 1st RX-FIFO pending, if other FIFOs
1446			 * are pending the main IRQ handler will take
1447			 * care.
1448			 */
1449			priv->regs_status.rxif = BIT(priv->rx[0]->fifo_nr);
1450			err = mcp251xfd_handle(priv, rxif);
1451			if (err)
1452				goto out_fail;
1453
1454			handled = IRQ_HANDLED;
1455
1456			/* We don't know which RX-FIFO is pending, but only
1457			 * handle the 1st RX-FIFO. Leave loop here if we have
1458			 * more than 1 RX-FIFO to avoid starvation.
1459			 */
1460		} while (priv->rx_ring_num == 1);
1461
1462	do {
1463		u32 intf_pending, intf_pending_clearable;
1464		bool set_normal_mode = false;
1465
1466		err = mcp251xfd_read_regs_status(priv);
1467		if (err)
1468			goto out_fail;
1469
1470		intf_pending = FIELD_GET(MCP251XFD_REG_INT_IF_MASK,
1471					 priv->regs_status.intf) &
1472			FIELD_GET(MCP251XFD_REG_INT_IE_MASK,
1473				  priv->regs_status.intf);
1474
1475		if (!(intf_pending)) {
1476			can_rx_offload_threaded_irq_finish(&priv->offload);
1477			return handled;
1478		}
1479
1480		/* Some interrupts must be ACKed in the
1481		 * MCP251XFD_REG_INT register.
1482		 * - First ACK then handle, to avoid lost-IRQ race
1483		 *   condition on fast re-occurring interrupts.
1484		 * - Write "0" to clear active IRQs, "1" to all other,
1485		 *   to avoid r/m/w race condition on the
1486		 *   MCP251XFD_REG_INT register.
1487		 */
1488		intf_pending_clearable = intf_pending &
1489			MCP251XFD_REG_INT_IF_CLEARABLE_MASK;
1490		if (intf_pending_clearable) {
1491			err = regmap_update_bits(priv->map_reg,
1492						 MCP251XFD_REG_INT,
1493						 MCP251XFD_REG_INT_IF_MASK,
1494						 ~intf_pending_clearable);
1495			if (err)
1496				goto out_fail;
1497		}
1498
1499		if (intf_pending & MCP251XFD_REG_INT_MODIF) {
1500			err = mcp251xfd_handle(priv, modif, &set_normal_mode);
1501			if (err)
1502				goto out_fail;
1503		}
1504
1505		if (intf_pending & MCP251XFD_REG_INT_RXIF) {
1506			err = mcp251xfd_handle(priv, rxif);
1507			if (err)
1508				goto out_fail;
1509		}
1510
1511		if (intf_pending & MCP251XFD_REG_INT_TEFIF) {
1512			err = mcp251xfd_handle(priv, tefif);
1513			if (err)
1514				goto out_fail;
1515		}
1516
1517		if (intf_pending & MCP251XFD_REG_INT_RXOVIF) {
1518			err = mcp251xfd_handle(priv, rxovif);
1519			if (err)
1520				goto out_fail;
1521		}
1522
1523		if (intf_pending & MCP251XFD_REG_INT_TXATIF) {
1524			err = mcp251xfd_handle(priv, txatif);
1525			if (err)
1526				goto out_fail;
1527		}
1528
1529		if (intf_pending & MCP251XFD_REG_INT_IVMIF) {
1530			err = mcp251xfd_handle(priv, ivmif);
1531			if (err)
1532				goto out_fail;
1533		}
1534
1535		if (intf_pending & MCP251XFD_REG_INT_SERRIF) {
1536			err = mcp251xfd_handle(priv, serrif);
1537			if (err)
1538				goto out_fail;
1539		}
1540
1541		if (intf_pending & MCP251XFD_REG_INT_ECCIF) {
1542			err = mcp251xfd_handle(priv, eccif, set_normal_mode);
1543			if (err)
1544				goto out_fail;
1545		}
1546
1547		if (intf_pending & MCP251XFD_REG_INT_SPICRCIF) {
1548			err = mcp251xfd_handle(priv, spicrcif);
1549			if (err)
1550				goto out_fail;
1551		}
1552
1553		/* On the MCP2527FD and MCP2518FD, we don't get a
1554		 * CERRIF IRQ on the transition TX ERROR_WARNING -> TX
1555		 * ERROR_ACTIVE.
1556		 */
1557		if (intf_pending & MCP251XFD_REG_INT_CERRIF ||
1558		    priv->can.state > CAN_STATE_ERROR_ACTIVE) {
1559			err = mcp251xfd_handle(priv, cerrif);
1560			if (err)
1561				goto out_fail;
1562
1563			/* In Bus Off we completely shut down the
1564			 * controller. Every subsequent register read
1565			 * will read bogus data, and if
1566			 * MCP251XFD_QUIRK_CRC_REG is enabled the CRC
1567			 * check will fail, too. So leave IRQ handler
1568			 * directly.
1569			 */
1570			if (priv->can.state == CAN_STATE_BUS_OFF) {
1571				can_rx_offload_threaded_irq_finish(&priv->offload);
1572				return IRQ_HANDLED;
1573			}
1574		}
1575
1576		handled = IRQ_HANDLED;
1577	} while (1);
1578
1579 out_fail:
1580	can_rx_offload_threaded_irq_finish(&priv->offload);
1581
1582	netdev_err(priv->ndev, "IRQ handler returned %d (intf=0x%08x).\n",
1583		   err, priv->regs_status.intf);
1584	mcp251xfd_dump(priv);
1585	mcp251xfd_chip_interrupts_disable(priv);
1586	mcp251xfd_timestamp_stop(priv);
1587
1588	return handled;
1589}
1590
1591static int mcp251xfd_open(struct net_device *ndev)
1592{
1593	struct mcp251xfd_priv *priv = netdev_priv(ndev);
1594	const struct spi_device *spi = priv->spi;
1595	int err;
1596
1597	err = open_candev(ndev);
1598	if (err)
1599		return err;
1600
1601	err = pm_runtime_resume_and_get(ndev->dev.parent);
1602	if (err)
1603		goto out_close_candev;
1604
1605	err = mcp251xfd_ring_alloc(priv);
1606	if (err)
1607		goto out_pm_runtime_put;
1608
1609	err = mcp251xfd_transceiver_enable(priv);
1610	if (err)
1611		goto out_mcp251xfd_ring_free;
1612
1613	err = mcp251xfd_chip_start(priv);
1614	if (err)
1615		goto out_transceiver_disable;
1616
1617	mcp251xfd_timestamp_init(priv);
1618	clear_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1619	can_rx_offload_enable(&priv->offload);
1620
1621	err = request_threaded_irq(spi->irq, NULL, mcp251xfd_irq,
1622				   IRQF_SHARED | IRQF_ONESHOT,
1623				   dev_name(&spi->dev), priv);
1624	if (err)
1625		goto out_can_rx_offload_disable;
1626
1627	err = mcp251xfd_chip_interrupts_enable(priv);
1628	if (err)
1629		goto out_free_irq;
1630
1631	netif_start_queue(ndev);
1632
1633	return 0;
1634
1635 out_free_irq:
1636	free_irq(spi->irq, priv);
1637 out_can_rx_offload_disable:
1638	can_rx_offload_disable(&priv->offload);
1639	set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1640	mcp251xfd_timestamp_stop(priv);
1641 out_transceiver_disable:
1642	mcp251xfd_transceiver_disable(priv);
1643 out_mcp251xfd_ring_free:
1644	mcp251xfd_ring_free(priv);
1645 out_pm_runtime_put:
1646	mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1647	pm_runtime_put(ndev->dev.parent);
1648 out_close_candev:
1649	close_candev(ndev);
1650
1651	return err;
1652}
1653
1654static int mcp251xfd_stop(struct net_device *ndev)
1655{
1656	struct mcp251xfd_priv *priv = netdev_priv(ndev);
1657
1658	netif_stop_queue(ndev);
1659	set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
1660	hrtimer_cancel(&priv->rx_irq_timer);
1661	hrtimer_cancel(&priv->tx_irq_timer);
1662	mcp251xfd_chip_interrupts_disable(priv);
1663	free_irq(ndev->irq, priv);
1664	can_rx_offload_disable(&priv->offload);
1665	mcp251xfd_timestamp_stop(priv);
1666	mcp251xfd_chip_stop(priv, CAN_STATE_STOPPED);
1667	mcp251xfd_transceiver_disable(priv);
1668	mcp251xfd_ring_free(priv);
1669	close_candev(ndev);
1670
1671	pm_runtime_put(ndev->dev.parent);
1672
1673	return 0;
1674}
1675
1676static const struct net_device_ops mcp251xfd_netdev_ops = {
1677	.ndo_open = mcp251xfd_open,
1678	.ndo_stop = mcp251xfd_stop,
1679	.ndo_start_xmit	= mcp251xfd_start_xmit,
1680	.ndo_eth_ioctl = can_eth_ioctl_hwts,
1681	.ndo_change_mtu = can_change_mtu,
1682};
1683
1684static void
1685mcp251xfd_register_quirks(struct mcp251xfd_priv *priv)
1686{
1687	const struct spi_device *spi = priv->spi;
1688	const struct spi_controller *ctlr = spi->controller;
1689
1690	if (ctlr->flags & SPI_CONTROLLER_HALF_DUPLEX)
1691		priv->devtype_data.quirks |= MCP251XFD_QUIRK_HALF_DUPLEX;
1692}
1693
1694static int mcp251xfd_register_chip_detect(struct mcp251xfd_priv *priv)
1695{
1696	const struct net_device *ndev = priv->ndev;
1697	const struct mcp251xfd_devtype_data *devtype_data;
1698	u32 osc;
1699	int err;
1700
1701	/* The OSC_LPMEN is only supported on MCP2518FD and MCP251863,
1702	 * so use it to autodetect the model.
1703	 */
1704	err = regmap_update_bits(priv->map_reg, MCP251XFD_REG_OSC,
1705				 MCP251XFD_REG_OSC_LPMEN,
1706				 MCP251XFD_REG_OSC_LPMEN);
1707	if (err)
1708		return err;
1709
1710	err = regmap_read(priv->map_reg, MCP251XFD_REG_OSC, &osc);
1711	if (err)
1712		return err;
1713
1714	if (osc & MCP251XFD_REG_OSC_LPMEN) {
1715		/* We cannot distinguish between MCP2518FD and
1716		 * MCP251863. If firmware specifies MCP251863, keep
1717		 * it, otherwise set to MCP2518FD.
1718		 */
1719		if (mcp251xfd_is_251863(priv))
1720			devtype_data = &mcp251xfd_devtype_data_mcp251863;
1721		else
1722			devtype_data = &mcp251xfd_devtype_data_mcp2518fd;
1723	} else {
1724		devtype_data = &mcp251xfd_devtype_data_mcp2517fd;
1725	}
1726
1727	if (!mcp251xfd_is_251XFD(priv) &&
1728	    priv->devtype_data.model != devtype_data->model) {
1729		netdev_info(ndev,
1730			    "Detected %s, but firmware specifies a %s. Fixing up.\n",
1731			    __mcp251xfd_get_model_str(devtype_data->model),
1732			    mcp251xfd_get_model_str(priv));
1733	}
1734	priv->devtype_data = *devtype_data;
1735
1736	/* We need to preserve the Half Duplex Quirk. */
1737	mcp251xfd_register_quirks(priv);
1738
1739	/* Re-init regmap with quirks of detected model. */
1740	return mcp251xfd_regmap_init(priv);
1741}
1742
1743static int mcp251xfd_register_check_rx_int(struct mcp251xfd_priv *priv)
1744{
1745	int err, rx_pending;
1746
1747	if (!priv->rx_int)
1748		return 0;
1749
1750	err = mcp251xfd_chip_rx_int_enable(priv);
1751	if (err)
1752		return err;
1753
1754	/* Check if RX_INT is properly working. The RX_INT should not
1755	 * be active after a softreset.
1756	 */
1757	rx_pending = gpiod_get_value_cansleep(priv->rx_int);
1758
1759	err = mcp251xfd_chip_rx_int_disable(priv);
1760	if (err)
1761		return err;
1762
1763	if (!rx_pending)
1764		return 0;
1765
1766	netdev_info(priv->ndev,
1767		    "RX_INT active after softreset, disabling RX_INT support.\n");
1768	devm_gpiod_put(&priv->spi->dev, priv->rx_int);
1769	priv->rx_int = NULL;
1770
1771	return 0;
1772}
1773
1774static int
1775mcp251xfd_register_get_dev_id(const struct mcp251xfd_priv *priv, u32 *dev_id,
1776			      u32 *effective_speed_hz_slow,
1777			      u32 *effective_speed_hz_fast)
1778{
1779	struct mcp251xfd_map_buf_nocrc *buf_rx;
1780	struct mcp251xfd_map_buf_nocrc *buf_tx;
1781	struct spi_transfer xfer[2] = { };
1782	int err;
1783
1784	buf_rx = kzalloc(sizeof(*buf_rx), GFP_KERNEL);
1785	if (!buf_rx)
1786		return -ENOMEM;
1787
1788	buf_tx = kzalloc(sizeof(*buf_tx), GFP_KERNEL);
1789	if (!buf_tx) {
1790		err = -ENOMEM;
1791		goto out_kfree_buf_rx;
1792	}
1793
1794	xfer[0].tx_buf = buf_tx;
1795	xfer[0].len = sizeof(buf_tx->cmd);
1796	xfer[0].speed_hz = priv->spi_max_speed_hz_slow;
1797	xfer[1].rx_buf = buf_rx->data;
1798	xfer[1].len = sizeof(*dev_id);
1799	xfer[1].speed_hz = priv->spi_max_speed_hz_fast;
1800
1801	mcp251xfd_spi_cmd_read_nocrc(&buf_tx->cmd, MCP251XFD_REG_DEVID);
1802
1803	err = spi_sync_transfer(priv->spi, xfer, ARRAY_SIZE(xfer));
1804	if (err)
1805		goto out_kfree_buf_tx;
1806
1807	*dev_id = get_unaligned_le32(buf_rx->data);
1808	*effective_speed_hz_slow = xfer[0].effective_speed_hz;
1809	*effective_speed_hz_fast = xfer[1].effective_speed_hz;
1810
1811 out_kfree_buf_tx:
1812	kfree(buf_tx);
1813 out_kfree_buf_rx:
1814	kfree(buf_rx);
1815
1816	return err;
1817}
1818
1819#define MCP251XFD_QUIRK_ACTIVE(quirk) \
1820	(priv->devtype_data.quirks & MCP251XFD_QUIRK_##quirk ? '+' : '-')
1821
1822static int
1823mcp251xfd_register_done(const struct mcp251xfd_priv *priv)
1824{
1825	u32 dev_id, effective_speed_hz_slow, effective_speed_hz_fast;
1826	unsigned long clk_rate;
1827	int err;
1828
1829	err = mcp251xfd_register_get_dev_id(priv, &dev_id,
1830					    &effective_speed_hz_slow,
1831					    &effective_speed_hz_fast);
1832	if (err)
1833		return err;
1834
1835	clk_rate = clk_get_rate(priv->clk);
1836
1837	netdev_info(priv->ndev,
1838		    "%s rev%lu.%lu (%cRX_INT %cPLL %cMAB_NO_WARN %cCRC_REG %cCRC_RX %cCRC_TX %cECC %cHD o:%lu.%02luMHz c:%u.%02uMHz m:%u.%02uMHz rs:%u.%02uMHz es:%u.%02uMHz rf:%u.%02uMHz ef:%u.%02uMHz) successfully initialized.\n",
1839		    mcp251xfd_get_model_str(priv),
1840		    FIELD_GET(MCP251XFD_REG_DEVID_ID_MASK, dev_id),
1841		    FIELD_GET(MCP251XFD_REG_DEVID_REV_MASK, dev_id),
1842		    priv->rx_int ? '+' : '-',
1843		    priv->pll_enable ? '+' : '-',
1844		    MCP251XFD_QUIRK_ACTIVE(MAB_NO_WARN),
1845		    MCP251XFD_QUIRK_ACTIVE(CRC_REG),
1846		    MCP251XFD_QUIRK_ACTIVE(CRC_RX),
1847		    MCP251XFD_QUIRK_ACTIVE(CRC_TX),
1848		    MCP251XFD_QUIRK_ACTIVE(ECC),
1849		    MCP251XFD_QUIRK_ACTIVE(HALF_DUPLEX),
1850		    clk_rate / 1000000,
1851		    clk_rate % 1000000 / 1000 / 10,
1852		    priv->can.clock.freq / 1000000,
1853		    priv->can.clock.freq % 1000000 / 1000 / 10,
1854		    priv->spi_max_speed_hz_orig / 1000000,
1855		    priv->spi_max_speed_hz_orig % 1000000 / 1000 / 10,
1856		    priv->spi_max_speed_hz_slow / 1000000,
1857		    priv->spi_max_speed_hz_slow % 1000000 / 1000 / 10,
1858		    effective_speed_hz_slow / 1000000,
1859		    effective_speed_hz_slow % 1000000 / 1000 / 10,
1860		    priv->spi_max_speed_hz_fast / 1000000,
1861		    priv->spi_max_speed_hz_fast % 1000000 / 1000 / 10,
1862		    effective_speed_hz_fast / 1000000,
1863		    effective_speed_hz_fast % 1000000 / 1000 / 10);
1864
1865	return 0;
1866}
1867
1868static int mcp251xfd_register(struct mcp251xfd_priv *priv)
1869{
1870	struct net_device *ndev = priv->ndev;
1871	int err;
1872
1873	err = mcp251xfd_clks_and_vdd_enable(priv);
1874	if (err)
1875		return err;
1876
1877	pm_runtime_get_noresume(ndev->dev.parent);
1878	err = pm_runtime_set_active(ndev->dev.parent);
1879	if (err)
1880		goto out_runtime_put_noidle;
1881	pm_runtime_enable(ndev->dev.parent);
1882
1883	mcp251xfd_register_quirks(priv);
1884
1885	err = mcp251xfd_chip_softreset(priv);
1886	if (err == -ENODEV)
1887		goto out_runtime_disable;
1888	if (err)
1889		goto out_chip_sleep;
1890
1891	err = mcp251xfd_chip_clock_init(priv);
1892	if (err == -ENODEV)
1893		goto out_runtime_disable;
1894	if (err)
1895		goto out_chip_sleep;
1896
1897	err = mcp251xfd_register_chip_detect(priv);
1898	if (err)
1899		goto out_chip_sleep;
1900
1901	err = mcp251xfd_register_check_rx_int(priv);
1902	if (err)
1903		goto out_chip_sleep;
1904
1905	mcp251xfd_ethtool_init(priv);
1906
1907	err = register_candev(ndev);
1908	if (err)
1909		goto out_chip_sleep;
1910
1911	err = mcp251xfd_register_done(priv);
1912	if (err)
1913		goto out_unregister_candev;
1914
1915	/* Put controller into sleep mode and let pm_runtime_put()
1916	 * disable the clocks and vdd. If CONFIG_PM is not enabled,
1917	 * the clocks and vdd will stay powered.
1918	 */
1919	err = mcp251xfd_chip_sleep(priv);
1920	if (err)
1921		goto out_unregister_candev;
1922
1923	pm_runtime_put(ndev->dev.parent);
1924
1925	return 0;
1926
1927 out_unregister_candev:
1928	unregister_candev(ndev);
1929 out_chip_sleep:
1930	mcp251xfd_chip_sleep(priv);
1931 out_runtime_disable:
1932	pm_runtime_disable(ndev->dev.parent);
1933 out_runtime_put_noidle:
1934	pm_runtime_put_noidle(ndev->dev.parent);
1935	mcp251xfd_clks_and_vdd_disable(priv);
1936
1937	return err;
1938}
1939
1940static inline void mcp251xfd_unregister(struct mcp251xfd_priv *priv)
1941{
1942	struct net_device *ndev	= priv->ndev;
1943
1944	unregister_candev(ndev);
1945
1946	if (pm_runtime_enabled(ndev->dev.parent))
1947		pm_runtime_disable(ndev->dev.parent);
1948	else
1949		mcp251xfd_clks_and_vdd_disable(priv);
1950}
1951
1952static const struct of_device_id mcp251xfd_of_match[] = {
1953	{
1954		.compatible = "microchip,mcp2517fd",
1955		.data = &mcp251xfd_devtype_data_mcp2517fd,
1956	}, {
1957		.compatible = "microchip,mcp2518fd",
1958		.data = &mcp251xfd_devtype_data_mcp2518fd,
1959	}, {
1960		.compatible = "microchip,mcp251863",
1961		.data = &mcp251xfd_devtype_data_mcp251863,
1962	}, {
1963		.compatible = "microchip,mcp251xfd",
1964		.data = &mcp251xfd_devtype_data_mcp251xfd,
1965	}, {
1966		/* sentinel */
1967	},
1968};
1969MODULE_DEVICE_TABLE(of, mcp251xfd_of_match);
1970
1971static const struct spi_device_id mcp251xfd_id_table[] = {
1972	{
1973		.name = "mcp2517fd",
1974		.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2517fd,
1975	}, {
1976		.name = "mcp2518fd",
1977		.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp2518fd,
1978	}, {
1979		.name = "mcp251863",
1980		.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251863,
1981	}, {
1982		.name = "mcp251xfd",
1983		.driver_data = (kernel_ulong_t)&mcp251xfd_devtype_data_mcp251xfd,
1984	}, {
1985		/* sentinel */
1986	},
1987};
1988MODULE_DEVICE_TABLE(spi, mcp251xfd_id_table);
1989
1990static int mcp251xfd_probe(struct spi_device *spi)
1991{
1992	const void *match;
1993	struct net_device *ndev;
1994	struct mcp251xfd_priv *priv;
1995	struct gpio_desc *rx_int;
1996	struct regulator *reg_vdd, *reg_xceiver;
1997	struct clk *clk;
1998	bool pll_enable = false;
1999	u32 freq = 0;
2000	int err;
2001
2002	if (!spi->irq)
2003		return dev_err_probe(&spi->dev, -ENXIO,
2004				     "No IRQ specified (maybe node \"interrupts-extended\" in DT missing)!\n");
2005
2006	rx_int = devm_gpiod_get_optional(&spi->dev, "microchip,rx-int",
2007					 GPIOD_IN);
2008	if (IS_ERR(rx_int))
2009		return dev_err_probe(&spi->dev, PTR_ERR(rx_int),
2010				     "Failed to get RX-INT!\n");
2011
2012	reg_vdd = devm_regulator_get_optional(&spi->dev, "vdd");
2013	if (PTR_ERR(reg_vdd) == -ENODEV)
2014		reg_vdd = NULL;
2015	else if (IS_ERR(reg_vdd))
2016		return dev_err_probe(&spi->dev, PTR_ERR(reg_vdd),
2017				     "Failed to get VDD regulator!\n");
2018
2019	reg_xceiver = devm_regulator_get_optional(&spi->dev, "xceiver");
2020	if (PTR_ERR(reg_xceiver) == -ENODEV)
2021		reg_xceiver = NULL;
2022	else if (IS_ERR(reg_xceiver))
2023		return dev_err_probe(&spi->dev, PTR_ERR(reg_xceiver),
2024				     "Failed to get Transceiver regulator!\n");
2025
2026	clk = devm_clk_get_optional(&spi->dev, NULL);
2027	if (IS_ERR(clk))
2028		return dev_err_probe(&spi->dev, PTR_ERR(clk),
2029				     "Failed to get Oscillator (clock)!\n");
2030	if (clk) {
2031		freq = clk_get_rate(clk);
2032	} else {
2033		err = device_property_read_u32(&spi->dev, "clock-frequency",
2034					       &freq);
2035		if (err)
2036			return dev_err_probe(&spi->dev, err,
2037					     "Failed to get clock-frequency!\n");
2038	}
2039
2040	/* Sanity check */
2041	if (freq < MCP251XFD_SYSCLOCK_HZ_MIN ||
2042	    freq > MCP251XFD_SYSCLOCK_HZ_MAX) {
2043		dev_err(&spi->dev,
2044			"Oscillator frequency (%u Hz) is too low or high.\n",
2045			freq);
2046		return -ERANGE;
2047	}
2048
2049	if (freq <= MCP251XFD_SYSCLOCK_HZ_MAX / MCP251XFD_OSC_PLL_MULTIPLIER)
2050		pll_enable = true;
2051
2052	ndev = alloc_candev(sizeof(struct mcp251xfd_priv),
2053			    MCP251XFD_TX_OBJ_NUM_MAX);
2054	if (!ndev)
2055		return -ENOMEM;
2056
2057	SET_NETDEV_DEV(ndev, &spi->dev);
2058
2059	ndev->netdev_ops = &mcp251xfd_netdev_ops;
2060	ndev->irq = spi->irq;
2061	ndev->flags |= IFF_ECHO;
2062
2063	priv = netdev_priv(ndev);
2064	spi_set_drvdata(spi, priv);
2065	priv->can.clock.freq = freq;
2066	if (pll_enable)
2067		priv->can.clock.freq *= MCP251XFD_OSC_PLL_MULTIPLIER;
2068	priv->can.do_set_mode = mcp251xfd_set_mode;
2069	priv->can.do_get_berr_counter = mcp251xfd_get_berr_counter;
2070	priv->can.bittiming_const = &mcp251xfd_bittiming_const;
2071	priv->can.data_bittiming_const = &mcp251xfd_data_bittiming_const;
2072	priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
2073		CAN_CTRLMODE_LISTENONLY | CAN_CTRLMODE_BERR_REPORTING |
2074		CAN_CTRLMODE_FD | CAN_CTRLMODE_FD_NON_ISO |
2075		CAN_CTRLMODE_CC_LEN8_DLC;
2076	set_bit(MCP251XFD_FLAGS_DOWN, priv->flags);
2077	priv->ndev = ndev;
2078	priv->spi = spi;
2079	priv->rx_int = rx_int;
2080	priv->clk = clk;
2081	priv->pll_enable = pll_enable;
2082	priv->reg_vdd = reg_vdd;
2083	priv->reg_xceiver = reg_xceiver;
2084
2085	match = device_get_match_data(&spi->dev);
2086	if (match)
2087		priv->devtype_data = *(struct mcp251xfd_devtype_data *)match;
2088	else
2089		priv->devtype_data = *(struct mcp251xfd_devtype_data *)
2090			spi_get_device_id(spi)->driver_data;
2091
2092	/* Errata Reference:
2093	 * mcp2517fd: DS80000792C 5., mcp2518fd: DS80000789C 4.
2094	 *
2095	 * The SPI can write corrupted data to the RAM at fast SPI
2096	 * speeds:
2097	 *
2098	 * Simultaneous activity on the CAN bus while writing data to
2099	 * RAM via the SPI interface, with high SCK frequency, can
2100	 * lead to corrupted data being written to RAM.
2101	 *
2102	 * Fix/Work Around:
2103	 * Ensure that FSCK is less than or equal to 0.85 *
2104	 * (FSYSCLK/2).
2105	 *
2106	 * Known good combinations are:
2107	 *
2108	 * MCP	ext-clk	SoC			SPI			SPI-clk		max-clk	parent-clk	config
2109	 *
2110	 * 2518	20 MHz	allwinner,sun8i-h3	allwinner,sun8i-h3-spi	 8333333 Hz	 83.33%	600000000 Hz	assigned-clocks = <&ccu CLK_SPIx>
2111	 * 2518	40 MHz	allwinner,sun8i-h3	allwinner,sun8i-h3-spi	16666667 Hz	 83.33%	600000000 Hz	assigned-clocks = <&ccu CLK_SPIx>
2112	 * 2517	40 MHz	atmel,sama5d27		atmel,at91rm9200-spi	16400000 Hz	 82.00%	 82000000 Hz	default
2113	 * 2518	40 MHz	atmel,sama5d27		atmel,at91rm9200-spi	16400000 Hz	 82.00%	 82000000 Hz	default
2114	 * 2518	40 MHz	fsl,imx6dl		fsl,imx51-ecspi		15000000 Hz	 75.00%	 30000000 Hz	default
2115	 * 2517	20 MHz	fsl,imx8mm		fsl,imx51-ecspi		 8333333 Hz	 83.33%	 16666667 Hz	assigned-clocks = <&clk IMX8MM_CLK_ECSPIx_ROOT>
2116	 *
2117	 */
2118	priv->spi_max_speed_hz_orig = spi->max_speed_hz;
2119	priv->spi_max_speed_hz_slow = min(spi->max_speed_hz,
2120					  freq / 2 / 1000 * 850);
2121	if (priv->pll_enable)
2122		priv->spi_max_speed_hz_fast = min(spi->max_speed_hz,
2123						  freq *
2124						  MCP251XFD_OSC_PLL_MULTIPLIER /
2125						  2 / 1000 * 850);
2126	else
2127		priv->spi_max_speed_hz_fast = priv->spi_max_speed_hz_slow;
2128	spi->max_speed_hz = priv->spi_max_speed_hz_slow;
2129	spi->bits_per_word = 8;
2130	spi->rt = true;
2131	err = spi_setup(spi);
2132	if (err)
2133		goto out_free_candev;
2134
2135	err = mcp251xfd_regmap_init(priv);
2136	if (err)
2137		goto out_free_candev;
2138
2139	err = can_rx_offload_add_manual(ndev, &priv->offload,
2140					MCP251XFD_NAPI_WEIGHT);
2141	if (err)
2142		goto out_free_candev;
2143
2144	err = mcp251xfd_register(priv);
2145	if (err) {
2146		dev_err_probe(&spi->dev, err, "Failed to detect %s.\n",
2147			      mcp251xfd_get_model_str(priv));
2148		goto out_can_rx_offload_del;
2149	}
2150
2151	return 0;
2152
2153 out_can_rx_offload_del:
2154	can_rx_offload_del(&priv->offload);
2155 out_free_candev:
2156	spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2157
2158	free_candev(ndev);
2159
2160	return err;
2161}
2162
2163static void mcp251xfd_remove(struct spi_device *spi)
2164{
2165	struct mcp251xfd_priv *priv = spi_get_drvdata(spi);
2166	struct net_device *ndev = priv->ndev;
2167
2168	can_rx_offload_del(&priv->offload);
2169	mcp251xfd_unregister(priv);
2170	spi->max_speed_hz = priv->spi_max_speed_hz_orig;
2171	free_candev(ndev);
2172}
2173
2174static int __maybe_unused mcp251xfd_runtime_suspend(struct device *device)
2175{
2176	const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2177
2178	return mcp251xfd_clks_and_vdd_disable(priv);
2179}
2180
2181static int __maybe_unused mcp251xfd_runtime_resume(struct device *device)
2182{
2183	const struct mcp251xfd_priv *priv = dev_get_drvdata(device);
2184
2185	return mcp251xfd_clks_and_vdd_enable(priv);
2186}
2187
2188static const struct dev_pm_ops mcp251xfd_pm_ops = {
2189	SET_RUNTIME_PM_OPS(mcp251xfd_runtime_suspend,
2190			   mcp251xfd_runtime_resume, NULL)
2191};
2192
2193static struct spi_driver mcp251xfd_driver = {
2194	.driver = {
2195		.name = DEVICE_NAME,
2196		.pm = &mcp251xfd_pm_ops,
2197		.of_match_table = mcp251xfd_of_match,
2198	},
2199	.probe = mcp251xfd_probe,
2200	.remove = mcp251xfd_remove,
2201	.id_table = mcp251xfd_id_table,
2202};
2203module_spi_driver(mcp251xfd_driver);
2204
2205MODULE_AUTHOR("Marc Kleine-Budde <mkl@pengutronix.de>");
2206MODULE_DESCRIPTION("Microchip MCP251xFD Family CAN controller driver");
2207MODULE_LICENSE("GPL v2");