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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "hwmgr.h"
25#include "vega10_hwmgr.h"
26#include "vega10_smumgr.h"
27#include "vega10_powertune.h"
28#include "vega10_ppsmc.h"
29#include "vega10_inc.h"
30#include "pp_debug.h"
31#include "soc15_common.h"
32
33static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = {
34/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
35 * Offset Mask Shift Value
36 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37 */
38 /* DIDT_SQ */
39 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 },
40 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 },
41
42 /* DIDT_TD */
43 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde },
44 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde },
45
46 /* DIDT_TCP */
47 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
48 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
49
50 /* DIDT_DB */
51 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
52 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
53
54 { 0xFFFFFFFF } /* End of list */
55};
56
57static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = {
58/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
59 * Offset Mask Shift Value
60 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
61 */
62 /*DIDT_SQ_CTRL3 */
63 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
64 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
65 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
66 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
67 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
68 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
69 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
70 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
71 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
72 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
73 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
74 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
75
76 /*DIDT_TCP_CTRL3 */
77 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
78 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
79 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
80 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
81 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
82 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
83 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
84 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
85 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
86 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
87 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
88 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
89
90 /*DIDT_TD_CTRL3 */
91 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
92 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
93 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
94 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
95 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
96 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
97 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
98 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
99 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
100 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
101 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
102 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
103
104 /*DIDT_DB_CTRL3 */
105 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
106 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
107 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
108 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
109 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
110 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
111 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
112 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
113 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
114 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
115 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
116 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
117
118 { 0xFFFFFFFF } /* End of list */
119};
120
121static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = {
122/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
123 * Offset Mask Shift Value
124 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
125 */
126 /* DIDT_SQ */
127 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 },
128 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
129 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 },
130
131 /* DIDT_TD */
132 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff },
133 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
134 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
135
136 /* DIDT_TCP */
137 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
138 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
139 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
140
141 /* DIDT_DB */
142 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
143 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
144 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
145
146 { 0xFFFFFFFF } /* End of list */
147};
148
149static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = {
150/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
151 * Offset Mask Shift Value
152 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
153 */
154 /* DIDT_SQ */
155 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 },
156 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff },
157 /* DIDT_TD */
158 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 },
159 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff },
160 /* DIDT_TCP */
161 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 },
162 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff },
163 /* DIDT_DB */
164 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 },
165 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff },
166
167 { 0xFFFFFFFF } /* End of list */
168};
169
170
171static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = {
172/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
173 * Offset Mask Shift Value
174 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
175 */
176 /* DIDT_SQ */
177 { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A },
178 { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 },
179 { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 },
180
181 /* DIDT_TD */
182 { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F },
183 { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 },
184 { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
185
186 /* DIDT_TCP */
187 { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D },
188 { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 },
189 { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
190
191 /* DIDT_DB */
192 { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F },
193 { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 },
194 { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 },
195
196 { 0xFFFFFFFF } /* End of list */
197};
198
199static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = {
200/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
201 * Offset Mask Shift Value
202 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
203 */
204 /* DIDT_SQ */
205 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
206 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
207 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
208 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
209 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
210 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
211 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
212 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
213 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
214 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
215 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
216 /* DIDT_TD */
217 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
218 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
219 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
220 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
221 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
222 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
223 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
224 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
225 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
226 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
227 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
228 /* DIDT_TCP */
229 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
230 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
231 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
232 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
233 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
234 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
235 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
236 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
237 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
238 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
239 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
240 /* DIDT_DB */
241 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
242 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
243 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
244 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
245 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
246 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
247 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
248 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
249 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
250 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
251 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
252
253 { 0xFFFFFFFF } /* End of list */
254};
255
256
257static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = {
258/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
259 * Offset Mask Shift Value
260 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
261 */
262 /* DIDT_SQ */
263 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
264 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
265 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
266 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
267
268 /* DIDT_TD */
269 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
270 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
271 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
272 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
273
274 /* DIDT_TCP */
275 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
276 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
277 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
278 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
279
280 /* DIDT_DB */
281 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
282 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
283 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
284 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
285
286 { 0xFFFFFFFF } /* End of list */
287};
288
289static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = {
290/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
291 * Offset Mask Shift Value
292 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
293 */
294 /* DIDT_SQ_STALL_PATTERN_1_2 */
295 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
296 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
297
298 /* DIDT_SQ_STALL_PATTERN_3_4 */
299 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
300 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
301
302 /* DIDT_SQ_STALL_PATTERN_5_6 */
303 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
304 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
305
306 /* DIDT_SQ_STALL_PATTERN_7 */
307 { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
308
309 /* DIDT_TCP_STALL_PATTERN_1_2 */
310 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
311 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
312
313 /* DIDT_TCP_STALL_PATTERN_3_4 */
314 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
315 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
316
317 /* DIDT_TCP_STALL_PATTERN_5_6 */
318 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
319 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
320
321 /* DIDT_TCP_STALL_PATTERN_7 */
322 { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
323
324 /* DIDT_TD_STALL_PATTERN_1_2 */
325 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
326 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
327
328 /* DIDT_TD_STALL_PATTERN_3_4 */
329 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
330 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
331
332 /* DIDT_TD_STALL_PATTERN_5_6 */
333 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
334 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
335
336 /* DIDT_TD_STALL_PATTERN_7 */
337 { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
338
339 /* DIDT_DB_STALL_PATTERN_1_2 */
340 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
341 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
342
343 /* DIDT_DB_STALL_PATTERN_3_4 */
344 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
345 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
346
347 /* DIDT_DB_STALL_PATTERN_5_6 */
348 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
349 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
350
351 /* DIDT_DB_STALL_PATTERN_7 */
352 { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
353
354 { 0xFFFFFFFF } /* End of list */
355};
356
357static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = {
358/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
359 * Offset Mask Shift Value
360 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
361 */
362 /* SQ */
363 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 },
364 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 },
365 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 },
366 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 },
367 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 },
368 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 },
369 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 },
370 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 },
371 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 },
372 /* TD */
373 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 },
374 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 },
375 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 },
376 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 },
377 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 },
378 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 },
379 /* TCP */
380 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 },
381 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 },
382 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 },
383 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 },
384 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 },
385 /* DB */
386 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 },
387 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 },
388 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 },
389 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 },
390
391 { 0xFFFFFFFF } /* End of list */
392};
393
394
395static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = {
396/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
397 * Offset Mask Shift Value
398 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
399 */
400 /* SQ */
401 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 },
402 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 },
403 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F },
404 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F },
405 /* TD */
406 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
407 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
408 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
409 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
410 /* TCP */
411 { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
412 { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
413 { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
414 { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
415 /* DB */
416 { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
417 { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
418 { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
419 { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
420
421 { 0xFFFFFFFF } /* End of list */
422};
423
424static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = {
425/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
426 * Offset Mask Shift Value
427 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
428 */
429 /* SQ */
430 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
431 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
432 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
433 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
434 /* TD */
435 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
436 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
437 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
438 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
439
440 { 0xFFFFFFFF } /* End of list */
441};
442
443static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = {
444/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
445 * Offset Mask Shift Value
446 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
447 */
448 /* SQ */
449 { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
450 { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
451 { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
452 { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
453 /* TD */
454 { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
455 { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
456 { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
457 { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
458 /* TCP */
459 { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
460 { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
461 { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
462 { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
463 /* DB */
464 { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
465
466 { 0xFFFFFFFF } /* End of list */
467};
468
469static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = {
470/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
471 * Offset Mask Shift Value
472 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
473 */
474 { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E },
475 { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
476 { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
477 { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
478
479 { 0xFFFFFFFF } /* End of list */
480};
481
482static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = {
483/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
484 * Offset Mask Shift Value
485 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
486 */
487 /* SQ */
488 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
489 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
490 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
491 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
492 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
493 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
494 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
495 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
496 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
497 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
498 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
499
500 { 0xFFFFFFFF } /* End of list */
501};
502
503static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = {
504/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
505 * Offset Mask Shift Value
506 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
507 */
508 /* SQ */
509 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
510 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
511 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
512 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
513 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 },
514 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 },
515 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
516 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
517 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
518 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
519 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
520
521 { 0xFFFFFFFF } /* End of list */
522};
523
524static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = {
525/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
526 * Offset Mask Shift Value
527 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
528 */
529 /* SQ */
530 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
531 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
532 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
533 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
534 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
535 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C },
536 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
537 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
538 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
539 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
540 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
541
542 /* TD */
543 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
544 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
545 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
546 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
547 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
548 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
549 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
550 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
551 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
552 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
553 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
554
555 { 0xFFFFFFFF } /* End of list */
556};
557
558static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = {
559/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
560 * Offset Mask Shift Value
561 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
562 */
563 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 },
564 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 },
565 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 },
566 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 },
567 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 },
568
569 { 0xFFFFFFFF } /* End of list */
570};
571
572static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = {
573/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
574 * Offset Mask Shift Value
575 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
576 */
577 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
578 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
579 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 },
580 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
581 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
582 { 0xFFFFFFFF } /* End of list */
583};
584
585
586static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = {
587/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
588 * Offset Mask Shift Value
589 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
590 */
591 /* SQ EDC STALL PATTERNs */
592 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 },
593 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 },
594 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 },
595 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 },
596
597 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 },
598 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 },
599
600 { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 },
601
602 { 0xFFFFFFFF } /* End of list */
603};
604
605static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = {
606/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
607 * Offset Mask Shift Value
608 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
609 */
610 /* SQ EDC STALL DELAYs */
611 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 },
612 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 },
613 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 },
614 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 },
615
616 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 },
617 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 },
618 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 },
619 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 },
620
621 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 },
622 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 },
623 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
624 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
625
626 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
627 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
628 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
629 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
630
631 { 0xFFFFFFFF } /* End of list */
632};
633
634static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = {
635/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
636 * Offset Mask Shift Value
637 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
638 */
639 /* SQ EDC CTRL */
640 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
641 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
642 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
643 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
644 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
645 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
646 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
647 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
648 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
649 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
650 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
651
652 { 0xFFFFFFFF } /* End of list */
653};
654
655static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = {
656/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
657 * Offset Mask Shift Value
658 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
659 */
660 /* SQ EDC CTRL */
661 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
662 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
663 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
664 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
665 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
666 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
667 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
668 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 },
669 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 },
670 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
671 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
672
673 { 0xFFFFFFFF } /* End of list */
674};
675
676static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = {
677/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
678 * Offset Mask Shift Value
679 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
680 */
681 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 },
682 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 },
683 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 },
684 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 },
685 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 },
686
687 { 0xFFFFFFFF } /* End of list */
688};
689
690static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = {
691/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
692 * Offset Mask Shift Value
693 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
694 */
695 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
696 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
697 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
698 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
699 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
700 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
701
702 { 0xFFFFFFFF } /* End of list */
703};
704
705static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = {
706/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
707 * Offset Mask Shift Value
708 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
709 */
710 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
711 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
712 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
713 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
714 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
715 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
716
717 { 0xFFFFFFFF } /* End of list */
718};
719
720static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[] = {
721/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
722 * Offset Mask Shift Value
723 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
724 */
725 { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F },
726 { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 },
727 { 0x16A06, 0x00000001, 0x0, 0x02000000 },
728 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
729
730 { 0xFFFFFFFF } /* End of list */
731};
732
733static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = {
734/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
735 * Offset Mask Shift Value
736 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
737 */
738 { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 },
739 { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 },
740 { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 },
741 { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 },
742 { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 },
743 { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 },
744 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
745
746 { 0xFFFFFFFF } /* End of list */
747};
748
749static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
750{
751 uint32_t data;
752
753 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
754
755 while (config_regs->offset != 0xFFFFFFFF) {
756 switch (reg_type) {
757 case VEGA10_CONFIGREG_DIDT:
758 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
759 data &= ~config_regs->mask;
760 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
761 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
762 break;
763 case VEGA10_CONFIGREG_GCCAC:
764 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
765 data &= ~config_regs->mask;
766 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
767 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
768 break;
769 case VEGA10_CONFIGREG_SECAC:
770 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
771 data &= ~config_regs->mask;
772 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
773 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
774 break;
775 default:
776 return -EINVAL;
777 }
778
779 config_regs++;
780 }
781
782 return 0;
783}
784
785static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
786{
787 uint32_t data;
788
789 while (config_regs->offset != 0xFFFFFFFF) {
790 data = cgs_read_register(hwmgr->device, config_regs->offset);
791 data &= ~config_regs->mask;
792 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
793 cgs_write_register(hwmgr->device, config_regs->offset, data);
794 config_regs++;
795 }
796
797 return 0;
798}
799
800static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
801{
802 uint32_t data;
803 uint32_t en = (enable ? 1 : 0);
804 uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
805
806 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
807 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
808 DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
809 didt_block_info &= ~SQ_Enable_MASK;
810 didt_block_info |= en << SQ_Enable_SHIFT;
811 }
812
813 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
814 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
815 DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
816 didt_block_info &= ~DB_Enable_MASK;
817 didt_block_info |= en << DB_Enable_SHIFT;
818 }
819
820 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
821 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
822 DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
823 didt_block_info &= ~TD_Enable_MASK;
824 didt_block_info |= en << TD_Enable_SHIFT;
825 }
826
827 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
828 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
829 DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
830 didt_block_info &= ~TCP_Enable_MASK;
831 didt_block_info |= en << TCP_Enable_SHIFT;
832 }
833
834 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
835 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
836 DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
837 }
838
839 if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
840 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
841 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
842 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
843 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
844 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
845 }
846
847 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
848 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
849 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
850 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
851 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
852 }
853
854 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
855 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
856 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
857 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
858 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
859 }
860
861 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
862 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
863 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
864 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
865 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
866 }
867
868 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
869 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
870 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
871 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
872 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
873 }
874 }
875
876 /* For Vega10, SMC does not support any mask yet. */
877 if (enable)
878 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info,
879 NULL);
880
881}
882
883static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
884{
885 struct amdgpu_device *adev = hwmgr->adev;
886 int result;
887 uint32_t num_se = 0, count, data;
888
889 num_se = adev->gfx.config.max_shader_engines;
890
891 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
892
893 mutex_lock(&adev->grbm_idx_mutex);
894 for (count = 0; count < num_se; count++) {
895 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
896 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
897
898 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
899 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
900 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
901 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
902 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
903 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
904 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
905 result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
906 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
907
908 if (0 != result)
909 break;
910 }
911 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
912 mutex_unlock(&adev->grbm_idx_mutex);
913
914 vega10_didt_set_mask(hwmgr, true);
915
916 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
917
918 return 0;
919}
920
921static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
922{
923 struct amdgpu_device *adev = hwmgr->adev;
924
925 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
926
927 vega10_didt_set_mask(hwmgr, false);
928
929 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
930
931 return 0;
932}
933
934static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
935{
936 struct amdgpu_device *adev = hwmgr->adev;
937 int result;
938 uint32_t num_se = 0, count, data;
939
940 num_se = adev->gfx.config.max_shader_engines;
941
942 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
943
944 mutex_lock(&adev->grbm_idx_mutex);
945 for (count = 0; count < num_se; count++) {
946 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
947 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
948
949 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
950 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
951 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
952 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
953 if (0 != result)
954 break;
955 }
956 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
957 mutex_unlock(&adev->grbm_idx_mutex);
958
959 vega10_didt_set_mask(hwmgr, true);
960
961 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
962
963 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
964 if (PP_CAP(PHM_PlatformCaps_GCEDC))
965 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
966
967 if (PP_CAP(PHM_PlatformCaps_PSM))
968 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
969
970 return 0;
971}
972
973static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
974{
975 struct amdgpu_device *adev = hwmgr->adev;
976 uint32_t data;
977
978 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
979
980 vega10_didt_set_mask(hwmgr, false);
981
982 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
983
984 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
985 data = 0x00000000;
986 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
987 }
988
989 if (PP_CAP(PHM_PlatformCaps_PSM))
990 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
991
992 return 0;
993}
994
995static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
996{
997 struct amdgpu_device *adev = hwmgr->adev;
998 int result;
999 uint32_t num_se = 0, count, data;
1000
1001 num_se = adev->gfx.config.max_shader_engines;
1002
1003 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1004
1005 mutex_lock(&adev->grbm_idx_mutex);
1006 for (count = 0; count < num_se; count++) {
1007 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1008 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1009 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1010 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1011 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1012 result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1013 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1014 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1015
1016 if (0 != result)
1017 break;
1018 }
1019 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1020 mutex_unlock(&adev->grbm_idx_mutex);
1021
1022 vega10_didt_set_mask(hwmgr, true);
1023
1024 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1025
1026 return 0;
1027}
1028
1029static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1030{
1031 struct amdgpu_device *adev = hwmgr->adev;
1032
1033 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1034
1035 vega10_didt_set_mask(hwmgr, false);
1036
1037 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1038
1039 return 0;
1040}
1041
1042static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1043{
1044 struct amdgpu_device *adev = hwmgr->adev;
1045 int result = 0;
1046 uint32_t num_se = 0;
1047 uint32_t count, data;
1048
1049 num_se = adev->gfx.config.max_shader_engines;
1050
1051 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1052
1053 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1054
1055 mutex_lock(&adev->grbm_idx_mutex);
1056 for (count = 0; count < num_se; count++) {
1057 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1058 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1059 result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1060 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1061 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1062 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1063
1064 if (0 != result)
1065 break;
1066 }
1067 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1068 mutex_unlock(&adev->grbm_idx_mutex);
1069
1070 vega10_didt_set_mask(hwmgr, true);
1071
1072 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1073
1074 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1075
1076 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1077 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1078 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1079 }
1080
1081 if (PP_CAP(PHM_PlatformCaps_PSM))
1082 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
1083
1084 return 0;
1085}
1086
1087static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1088{
1089 struct amdgpu_device *adev = hwmgr->adev;
1090 uint32_t data;
1091
1092 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1093
1094 vega10_didt_set_mask(hwmgr, false);
1095
1096 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1097
1098 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1099 data = 0x00000000;
1100 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1101 }
1102
1103 if (PP_CAP(PHM_PlatformCaps_PSM))
1104 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1105
1106 return 0;
1107}
1108
1109static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1110{
1111 struct amdgpu_device *adev = hwmgr->adev;
1112 int result;
1113
1114 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1115
1116 mutex_lock(&adev->grbm_idx_mutex);
1117 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1118 mutex_unlock(&adev->grbm_idx_mutex);
1119
1120 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1121 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1122 if (0 != result)
1123 return result;
1124
1125 vega10_didt_set_mask(hwmgr, false);
1126
1127 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1128
1129 return 0;
1130}
1131
1132static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1133{
1134 int result;
1135
1136 result = vega10_disable_se_edc_config(hwmgr);
1137 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1138
1139 return 0;
1140}
1141
1142int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1143{
1144 int result = 0;
1145 struct vega10_hwmgr *data = hwmgr->backend;
1146
1147 if (data->smu_features[GNLD_DIDT].supported) {
1148 if (data->smu_features[GNLD_DIDT].enabled)
1149 PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1150
1151 switch (data->registry_data.didt_mode) {
1152 case 0:
1153 result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1154 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1155 break;
1156 case 2:
1157 result = vega10_enable_psm_gc_didt_config(hwmgr);
1158 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1159 break;
1160 case 3:
1161 result = vega10_enable_se_edc_config(hwmgr);
1162 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1163 break;
1164 case 1:
1165 case 4:
1166 case 5:
1167 result = vega10_enable_psm_gc_edc_config(hwmgr);
1168 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1169 break;
1170 case 6:
1171 result = vega10_enable_se_edc_force_stall_config(hwmgr);
1172 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1173 break;
1174 default:
1175 result = -EINVAL;
1176 break;
1177 }
1178
1179 if (0 == result) {
1180 result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1181 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1182 data->smu_features[GNLD_DIDT].enabled = true;
1183 }
1184 }
1185
1186 return result;
1187}
1188
1189int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1190{
1191 int result = 0;
1192 struct vega10_hwmgr *data = hwmgr->backend;
1193
1194 if (data->smu_features[GNLD_DIDT].supported) {
1195 if (!data->smu_features[GNLD_DIDT].enabled)
1196 PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1197
1198 switch (data->registry_data.didt_mode) {
1199 case 0:
1200 result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1201 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1202 break;
1203 case 2:
1204 result = vega10_disable_psm_gc_didt_config(hwmgr);
1205 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1206 break;
1207 case 3:
1208 result = vega10_disable_se_edc_config(hwmgr);
1209 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1210 break;
1211 case 1:
1212 case 4:
1213 case 5:
1214 result = vega10_disable_psm_gc_edc_config(hwmgr);
1215 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1216 break;
1217 case 6:
1218 result = vega10_disable_se_edc_force_stall_config(hwmgr);
1219 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1220 break;
1221 default:
1222 result = -EINVAL;
1223 break;
1224 }
1225
1226 if (0 == result) {
1227 result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1228 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1229 data->smu_features[GNLD_DIDT].enabled = false;
1230 }
1231 }
1232
1233 return result;
1234}
1235
1236void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1237{
1238 struct vega10_hwmgr *data = hwmgr->backend;
1239 struct phm_ppt_v2_information *table_info =
1240 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1241 struct phm_tdp_table *tdp_table = table_info->tdp_table;
1242 PPTable_t *table = &(data->smc_state_table.pp_table);
1243
1244 table->SocketPowerLimit = cpu_to_le16(
1245 tdp_table->usMaximumPowerDeliveryLimit);
1246 table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1247 table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1248 table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1249 table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1250 table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1251 table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1252 table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1253 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1254 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1255 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1256 table->LoadLineResistance =
1257 hwmgr->platform_descriptor.LoadLineSlope * 256;
1258 table->FitLimit = 0; /* Not used for Vega10 */
1259
1260 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1261 table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1262 table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1263 table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1264
1265 table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1266 table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1267
1268 table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1269 table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1270
1271 table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1272 table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1273}
1274
1275int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1276{
1277 struct vega10_hwmgr *data = hwmgr->backend;
1278
1279 if (data->registry_data.enable_pkg_pwr_tracking_feature)
1280 smum_send_msg_to_smc_with_parameter(hwmgr,
1281 PPSMC_MSG_SetPptLimit, n,
1282 NULL);
1283
1284 return 0;
1285}
1286
1287int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1288{
1289 struct vega10_hwmgr *data = hwmgr->backend;
1290 struct phm_ppt_v2_information *table_info =
1291 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1292 struct phm_tdp_table *tdp_table = table_info->tdp_table;
1293 int result = 0;
1294
1295 hwmgr->default_power_limit = hwmgr->power_limit =
1296 (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1297
1298 if (!hwmgr->not_vf)
1299 return 0;
1300
1301 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1302 if (data->smu_features[GNLD_PPT].supported)
1303 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1304 true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1305 "Attempt to enable PPT feature Failed!",
1306 data->smu_features[GNLD_PPT].supported = false);
1307
1308 if (data->smu_features[GNLD_TDC].supported)
1309 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1310 true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1311 "Attempt to enable PPT feature Failed!",
1312 data->smu_features[GNLD_TDC].supported = false);
1313
1314 result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1315 PP_ASSERT_WITH_CODE(!result,
1316 "Failed to set Default Power Limit in SMC!",
1317 return result);
1318 }
1319
1320 return result;
1321}
1322
1323int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1324{
1325 struct vega10_hwmgr *data = hwmgr->backend;
1326
1327 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1328 if (data->smu_features[GNLD_PPT].supported)
1329 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1330 false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1331 "Attempt to disable PPT feature Failed!",
1332 data->smu_features[GNLD_PPT].supported = false);
1333
1334 if (data->smu_features[GNLD_TDC].supported)
1335 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1336 false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1337 "Attempt to disable PPT feature Failed!",
1338 data->smu_features[GNLD_TDC].supported = false);
1339 }
1340
1341 return 0;
1342}
1343
1344static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1345 uint32_t adjust_percent)
1346{
1347 smum_send_msg_to_smc_with_parameter(hwmgr,
1348 PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
1349 NULL);
1350}
1351
1352int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1353{
1354 int adjust_percent;
1355
1356 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1357 adjust_percent =
1358 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1359 hwmgr->platform_descriptor.TDPAdjustment :
1360 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1361 vega10_set_overdrive_target_percentage(hwmgr,
1362 (uint32_t)adjust_percent);
1363 }
1364 return 0;
1365}
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "hwmgr.h"
25#include "vega10_hwmgr.h"
26#include "vega10_smumgr.h"
27#include "vega10_powertune.h"
28#include "vega10_ppsmc.h"
29#include "vega10_inc.h"
30#include "pp_debug.h"
31#include "soc15_common.h"
32
33static const struct vega10_didt_config_reg SEDiDtTuningCtrlConfig_Vega10[] = {
34/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
35 * Offset Mask Shift Value
36 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
37 */
38 /* DIDT_SQ */
39 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3853 },
40 { ixDIDT_SQ_TUNING_CTRL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3153 },
41
42 /* DIDT_TD */
43 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x0dde },
44 { ixDIDT_TD_TUNING_CTRL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x0dde },
45
46 /* DIDT_TCP */
47 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
48 { ixDIDT_TCP_TUNING_CTRL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
49
50 /* DIDT_DB */
51 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT, 0x3dde },
52 { ixDIDT_DB_TUNING_CTRL, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK, DIDT_DB_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT, 0x3dde },
53
54 { 0xFFFFFFFF } /* End of list */
55};
56
57static const struct vega10_didt_config_reg SEDiDtCtrl3Config_vega10[] = {
58/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
59 * Offset Mask Shift Value
60 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
61 */
62 /*DIDT_SQ_CTRL3 */
63 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_SQ_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
64 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
65 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__THROTTLE_POLICY_MASK, DIDT_SQ_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
66 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
67 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_SQ_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
68 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
69 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
70 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_SQ_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
71 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_SQ_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
72 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_SEL_MASK, DIDT_SQ_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
73 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_SQ_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
74 { ixDIDT_SQ_CTRL3, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_SQ_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
75
76 /*DIDT_TCP_CTRL3 */
77 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TCP_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
78 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
79 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__THROTTLE_POLICY_MASK, DIDT_TCP_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
80 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
81 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TCP_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
82 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TCP_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
83 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
84 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TCP_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
85 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TCP_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
86 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TCP_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
87 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TCP_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
88 { ixDIDT_TCP_CTRL3, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TCP_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
89
90 /*DIDT_TD_CTRL3 */
91 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_TD_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
92 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
93 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__THROTTLE_POLICY_MASK, DIDT_TD_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
94 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
95 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_TD_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
96 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
97 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
98 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_TD_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
99 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_TD_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
100 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_SEL_MASK, DIDT_TD_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
101 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_TD_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
102 { ixDIDT_TD_CTRL3, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_TD_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
103
104 /*DIDT_DB_CTRL3 */
105 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_ENABLE_MASK, DIDT_DB_CTRL3__GC_DIDT_ENABLE__SHIFT, 0x0000 },
106 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL3__GC_DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
107 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__THROTTLE_POLICY_MASK, DIDT_DB_CTRL3__THROTTLE_POLICY__SHIFT, 0x0003 },
108 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
109 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT_MASK, DIDT_DB_CTRL3__DIDT_POWER_LEVEL_LOWBIT__SHIFT, 0x0000 },
110 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS_MASK, DIDT_DB_CTRL3__DIDT_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0003 },
111 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__GC_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
112 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN_MASK, DIDT_DB_CTRL3__SE_DIDT_LEVEL_COMB_EN__SHIFT, 0x0000 },
113 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__QUALIFY_STALL_EN_MASK, DIDT_DB_CTRL3__QUALIFY_STALL_EN__SHIFT, 0x0000 },
114 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_SEL_MASK, DIDT_DB_CTRL3__DIDT_STALL_SEL__SHIFT, 0x0000 },
115 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_FORCE_STALL_MASK, DIDT_DB_CTRL3__DIDT_FORCE_STALL__SHIFT, 0x0000 },
116 { ixDIDT_DB_CTRL3, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN_MASK, DIDT_DB_CTRL3__DIDT_STALL_DELAY_EN__SHIFT, 0x0000 },
117
118 { 0xFFFFFFFF } /* End of list */
119};
120
121static const struct vega10_didt_config_reg SEDiDtCtrl2Config_Vega10[] = {
122/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
123 * Offset Mask Shift Value
124 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
125 */
126 /* DIDT_SQ */
127 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3853 },
128 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
129 { ixDIDT_SQ_CTRL2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000 },
130
131 /* DIDT_TD */
132 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff },
133 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
134 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
135
136 /* DIDT_TCP */
137 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
138 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
139 { ixDIDT_TCP_CTRL2, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
140
141 /* DIDT_DB */
142 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__MAX_POWER_DELTA_MASK, DIDT_DB_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3dde },
143 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_DB_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
144 { ixDIDT_DB_CTRL2, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_DB_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
145
146 { 0xFFFFFFFF } /* End of list */
147};
148
149static const struct vega10_didt_config_reg SEDiDtCtrl1Config_Vega10[] = {
150/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
151 * Offset Mask Shift Value
152 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
153 */
154 /* DIDT_SQ */
155 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MIN_POWER_MASK, DIDT_SQ_CTRL1__MIN_POWER__SHIFT, 0x0000 },
156 { ixDIDT_SQ_CTRL1, DIDT_SQ_CTRL1__MAX_POWER_MASK, DIDT_SQ_CTRL1__MAX_POWER__SHIFT, 0xffff },
157 /* DIDT_TD */
158 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MIN_POWER_MASK, DIDT_TD_CTRL1__MIN_POWER__SHIFT, 0x0000 },
159 { ixDIDT_TD_CTRL1, DIDT_TD_CTRL1__MAX_POWER_MASK, DIDT_TD_CTRL1__MAX_POWER__SHIFT, 0xffff },
160 /* DIDT_TCP */
161 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MIN_POWER_MASK, DIDT_TCP_CTRL1__MIN_POWER__SHIFT, 0x0000 },
162 { ixDIDT_TCP_CTRL1, DIDT_TCP_CTRL1__MAX_POWER_MASK, DIDT_TCP_CTRL1__MAX_POWER__SHIFT, 0xffff },
163 /* DIDT_DB */
164 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MIN_POWER_MASK, DIDT_DB_CTRL1__MIN_POWER__SHIFT, 0x0000 },
165 { ixDIDT_DB_CTRL1, DIDT_DB_CTRL1__MAX_POWER_MASK, DIDT_DB_CTRL1__MAX_POWER__SHIFT, 0xffff },
166
167 { 0xFFFFFFFF } /* End of list */
168};
169
170
171static const struct vega10_didt_config_reg SEDiDtWeightConfig_Vega10[] = {
172/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
173 * Offset Mask Shift Value
174 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
175 */
176 /* DIDT_SQ */
177 { ixDIDT_SQ_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B363B1A },
178 { ixDIDT_SQ_WEIGHT4_7, 0xFFFFFFFF, 0, 0x270B2432 },
179 { ixDIDT_SQ_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000018 },
180
181 /* DIDT_TD */
182 { ixDIDT_TD_WEIGHT0_3, 0xFFFFFFFF, 0, 0x2B1D220F },
183 { ixDIDT_TD_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00007558 },
184 { ixDIDT_TD_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
185
186 /* DIDT_TCP */
187 { ixDIDT_TCP_WEIGHT0_3, 0xFFFFFFFF, 0, 0x5ACE160D },
188 { ixDIDT_TCP_WEIGHT4_7, 0xFFFFFFFF, 0, 0x00000000 },
189 { ixDIDT_TCP_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000000 },
190
191 /* DIDT_DB */
192 { ixDIDT_DB_WEIGHT0_3, 0xFFFFFFFF, 0, 0x0E152A0F },
193 { ixDIDT_DB_WEIGHT4_7, 0xFFFFFFFF, 0, 0x09061813 },
194 { ixDIDT_DB_WEIGHT8_11, 0xFFFFFFFF, 0, 0x00000013 },
195
196 { 0xFFFFFFFF } /* End of list */
197};
198
199static const struct vega10_didt_config_reg SEDiDtCtrl0Config_Vega10[] = {
200/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
201 * Offset Mask Shift Value
202 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
203 */
204 /* DIDT_SQ */
205 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
206 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
207 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
208 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
209 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
210 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_SQ_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
211 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
212 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_SQ_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
213 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_SQ_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
214 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
215 { ixDIDT_SQ_CTRL0, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_SQ_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
216 /* DIDT_TD */
217 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
218 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__PHASE_OFFSET_MASK, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
219 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
220 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
221 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
222 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TD_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
223 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
224 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TD_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
225 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TD_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
226 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
227 { ixDIDT_TD_CTRL0, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TD_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
228 /* DIDT_TCP */
229 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
230 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
231 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
232 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
233 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
234 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_TCP_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
235 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
236 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_TCP_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
237 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_TCP_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
238 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
239 { ixDIDT_TCP_CTRL0, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_TCP_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
240 /* DIDT_DB */
241 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
242 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__PHASE_OFFSET_MASK, DIDT_DB_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
243 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CTRL_RST_MASK, DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT, 0x0000 },
244 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
245 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_CTRL_EN__SHIFT, 0x0001 },
246 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN_MASK, DIDT_DB_CTRL0__DIDT_TUNING_CTRL_EN__SHIFT, 0x0001 },
247 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_AUTO_RELEASE_EN__SHIFT, 0x0001 },
248 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD_MASK, DIDT_DB_CTRL0__DIDT_HI_POWER_THRESHOLD__SHIFT, 0xffff },
249 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN_MASK, DIDT_DB_CTRL0__DIDT_AUTO_MPD_EN__SHIFT, 0x0000 },
250 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_EN__SHIFT, 0x0000 },
251 { ixDIDT_DB_CTRL0, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR_MASK, DIDT_DB_CTRL0__DIDT_STALL_EVENT_COUNTER_CLEAR__SHIFT, 0x0000 },
252
253 { 0xFFFFFFFF } /* End of list */
254};
255
256
257static const struct vega10_didt_config_reg SEDiDtStallCtrlConfig_vega10[] = {
258/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
259 * Offset Mask Shift Value
260 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
261 */
262 /* DIDT_SQ */
263 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
264 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
265 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
266 { ixDIDT_SQ_STALL_CTRL, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_SQ_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
267
268 /* DIDT_TD */
269 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
270 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
271 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
272 { ixDIDT_TD_STALL_CTRL, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TD_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
273
274 /* DIDT_TCP */
275 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0001 },
276 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0001 },
277 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
278 { ixDIDT_TCP_STALL_CTRL, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_TCP_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
279
280 /* DIDT_DB */
281 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT, 0x0004 },
282 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT, 0x0004 },
283 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT, 0x000a },
284 { ixDIDT_DB_STALL_CTRL, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO_MASK, DIDT_DB_STALL_CTRL__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT, 0x000a },
285
286 { 0xFFFFFFFF } /* End of list */
287};
288
289static const struct vega10_didt_config_reg SEDiDtStallPatternConfig_vega10[] = {
290/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
291 * Offset Mask Shift Value
292 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
293 */
294 /* DIDT_SQ_STALL_PATTERN_1_2 */
295 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
296 { ixDIDT_SQ_STALL_PATTERN_1_2, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_SQ_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
297
298 /* DIDT_SQ_STALL_PATTERN_3_4 */
299 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
300 { ixDIDT_SQ_STALL_PATTERN_3_4, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_SQ_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
301
302 /* DIDT_SQ_STALL_PATTERN_5_6 */
303 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
304 { ixDIDT_SQ_STALL_PATTERN_5_6, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_SQ_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
305
306 /* DIDT_SQ_STALL_PATTERN_7 */
307 { ixDIDT_SQ_STALL_PATTERN_7, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_SQ_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
308
309 /* DIDT_TCP_STALL_PATTERN_1_2 */
310 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
311 { ixDIDT_TCP_STALL_PATTERN_1_2, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TCP_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
312
313 /* DIDT_TCP_STALL_PATTERN_3_4 */
314 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
315 { ixDIDT_TCP_STALL_PATTERN_3_4, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TCP_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
316
317 /* DIDT_TCP_STALL_PATTERN_5_6 */
318 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
319 { ixDIDT_TCP_STALL_PATTERN_5_6, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TCP_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
320
321 /* DIDT_TCP_STALL_PATTERN_7 */
322 { ixDIDT_TCP_STALL_PATTERN_7, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TCP_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
323
324 /* DIDT_TD_STALL_PATTERN_1_2 */
325 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
326 { ixDIDT_TD_STALL_PATTERN_1_2, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_TD_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
327
328 /* DIDT_TD_STALL_PATTERN_3_4 */
329 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
330 { ixDIDT_TD_STALL_PATTERN_3_4, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_TD_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
331
332 /* DIDT_TD_STALL_PATTERN_5_6 */
333 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
334 { ixDIDT_TD_STALL_PATTERN_5_6, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_TD_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
335
336 /* DIDT_TD_STALL_PATTERN_7 */
337 { ixDIDT_TD_STALL_PATTERN_7, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_TD_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
338
339 /* DIDT_DB_STALL_PATTERN_1_2 */
340 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_1__SHIFT, 0x0001 },
341 { ixDIDT_DB_STALL_PATTERN_1_2, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2_MASK, DIDT_DB_STALL_PATTERN_1_2__DIDT_STALL_PATTERN_2__SHIFT, 0x0001 },
342
343 /* DIDT_DB_STALL_PATTERN_3_4 */
344 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_3__SHIFT, 0x0001 },
345 { ixDIDT_DB_STALL_PATTERN_3_4, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4_MASK, DIDT_DB_STALL_PATTERN_3_4__DIDT_STALL_PATTERN_4__SHIFT, 0x0001 },
346
347 /* DIDT_DB_STALL_PATTERN_5_6 */
348 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_5__SHIFT, 0x0000 },
349 { ixDIDT_DB_STALL_PATTERN_5_6, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6_MASK, DIDT_DB_STALL_PATTERN_5_6__DIDT_STALL_PATTERN_6__SHIFT, 0x0000 },
350
351 /* DIDT_DB_STALL_PATTERN_7 */
352 { ixDIDT_DB_STALL_PATTERN_7, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7_MASK, DIDT_DB_STALL_PATTERN_7__DIDT_STALL_PATTERN_7__SHIFT, 0x0000 },
353
354 { 0xFFFFFFFF } /* End of list */
355};
356
357static const struct vega10_didt_config_reg SELCacConfig_Vega10[] = {
358/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
359 * Offset Mask Shift Value
360 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
361 */
362 /* SQ */
363 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00060021 },
364 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00860021 },
365 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01060021 },
366 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01860021 },
367 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02060021 },
368 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x02860021 },
369 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03060021 },
370 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x03860021 },
371 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x04060021 },
372 /* TD */
373 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x000E0020 },
374 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x008E0020 },
375 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x010E0020 },
376 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x018E0020 },
377 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x020E0020 },
378 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x028E0020 },
379 /* TCP */
380 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x001c0020 },
381 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x009c0020 },
382 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x011c0020 },
383 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x019c0020 },
384 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x021c0020 },
385 /* DB */
386 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00200008 },
387 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x00820008 },
388 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01020008 },
389 { ixSE_CAC_CNTL, 0xFFFFFFFF, 0, 0x01820008 },
390
391 { 0xFFFFFFFF } /* End of list */
392};
393
394
395static const struct vega10_didt_config_reg SEEDCStallPatternConfig_Vega10[] = {
396/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
397 * Offset Mask Shift Value
398 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
399 */
400 /* SQ */
401 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00030001 },
402 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x000F0007 },
403 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x003F001F },
404 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x0000007F },
405 /* TD */
406 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
407 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
408 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
409 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
410 /* TCP */
411 { ixDIDT_TCP_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
412 { ixDIDT_TCP_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
413 { ixDIDT_TCP_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
414 { ixDIDT_TCP_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
415 /* DB */
416 { ixDIDT_DB_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000000 },
417 { ixDIDT_DB_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
418 { ixDIDT_DB_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
419 { ixDIDT_DB_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
420
421 { 0xFFFFFFFF } /* End of list */
422};
423
424static const struct vega10_didt_config_reg SEEDCForceStallPatternConfig_Vega10[] = {
425/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
426 * Offset Mask Shift Value
427 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
428 */
429 /* SQ */
430 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
431 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
432 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
433 { ixDIDT_SQ_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
434 /* TD */
435 { ixDIDT_TD_EDC_STALL_PATTERN_1_2, 0xFFFFFFFF, 0, 0x00000015 },
436 { ixDIDT_TD_EDC_STALL_PATTERN_3_4, 0xFFFFFFFF, 0, 0x00000000 },
437 { ixDIDT_TD_EDC_STALL_PATTERN_5_6, 0xFFFFFFFF, 0, 0x00000000 },
438 { ixDIDT_TD_EDC_STALL_PATTERN_7, 0xFFFFFFFF, 0, 0x00000000 },
439
440 { 0xFFFFFFFF } /* End of list */
441};
442
443static const struct vega10_didt_config_reg SEEDCStallDelayConfig_Vega10[] = {
444/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
445 * Offset Mask Shift Value
446 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
447 */
448 /* SQ */
449 { ixDIDT_SQ_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
450 { ixDIDT_SQ_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
451 { ixDIDT_SQ_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
452 { ixDIDT_SQ_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
453 /* TD */
454 { ixDIDT_TD_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
455 { ixDIDT_TD_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
456 { ixDIDT_TD_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
457 { ixDIDT_TD_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
458 /* TCP */
459 { ixDIDT_TCP_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
460 { ixDIDT_TCP_EDC_STALL_DELAY_2, 0xFFFFFFFF, 0, 0x00000000 },
461 { ixDIDT_TCP_EDC_STALL_DELAY_3, 0xFFFFFFFF, 0, 0x00000000 },
462 { ixDIDT_TCP_EDC_STALL_DELAY_4, 0xFFFFFFFF, 0, 0x00000000 },
463 /* DB */
464 { ixDIDT_DB_EDC_STALL_DELAY_1, 0xFFFFFFFF, 0, 0x00000000 },
465
466 { 0xFFFFFFFF } /* End of list */
467};
468
469static const struct vega10_didt_config_reg SEEDCThresholdConfig_Vega10[] = {
470/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
471 * Offset Mask Shift Value
472 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
473 */
474 { ixDIDT_SQ_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0x0000010E },
475 { ixDIDT_TD_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
476 { ixDIDT_TCP_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
477 { ixDIDT_DB_EDC_THRESHOLD, 0xFFFFFFFF, 0, 0xFFFFFFFF },
478
479 { 0xFFFFFFFF } /* End of list */
480};
481
482static const struct vega10_didt_config_reg SEEDCCtrlResetConfig_Vega10[] = {
483/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
484 * Offset Mask Shift Value
485 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
486 */
487 /* SQ */
488 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
489 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
490 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
491 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
492 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
493 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
494 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
495 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
496 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
497 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
498 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
499
500 { 0xFFFFFFFF } /* End of list */
501};
502
503static const struct vega10_didt_config_reg SEEDCCtrlConfig_Vega10[] = {
504/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
505 * Offset Mask Shift Value
506 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
507 */
508 /* SQ */
509 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
510 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
511 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
512 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
513 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0004 },
514 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0006 },
515 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
516 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
517 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
518 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
519 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
520
521 { 0xFFFFFFFF } /* End of list */
522};
523
524static const struct vega10_didt_config_reg SEEDCCtrlForceStallConfig_Vega10[] = {
525/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
526 * Offset Mask Shift Value
527 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
528 */
529 /* SQ */
530 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
531 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
532 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
533 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
534 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
535 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000C },
536 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
537 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
538 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
539 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
540 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
541
542 /* TD */
543 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_EN_MASK, DIDT_TD_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
544 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_SW_RST_MASK, DIDT_TD_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
545 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_TD_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
546 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_TD_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0001 },
547 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_TD_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0001 },
548 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_TD_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
549 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_TD_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
550 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
551 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_TD_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
552 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
553 { ixDIDT_TD_EDC_CTRL, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_TD_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
554
555 { 0xFFFFFFFF } /* End of list */
556};
557
558static const struct vega10_didt_config_reg GCDiDtDroopCtrlConfig_vega10[] = {
559/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
560 * Offset Mask Shift Value
561 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
562 */
563 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_EN__SHIFT, 0x0000 },
564 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_THRESHOLD__SHIFT, 0x0000 },
565 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_INDEX__SHIFT, 0x0000 },
566 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL_MASK, GC_DIDT_DROOP_CTRL__DIDT_LEVEL_SEL__SHIFT, 0x0000 },
567 { mmGC_DIDT_DROOP_CTRL, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW_MASK, GC_DIDT_DROOP_CTRL__DIDT_DROOP_LEVEL_OVERFLOW__SHIFT, 0x0000 },
568
569 { 0xFFFFFFFF } /* End of list */
570};
571
572static const struct vega10_didt_config_reg GCDiDtCtrl0Config_vega10[] = {
573/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
574 * Offset Mask Shift Value
575 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
576 */
577 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CTRL_EN_MASK, GC_DIDT_CTRL0__DIDT_CTRL_EN__SHIFT, 0x0000 },
578 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__PHASE_OFFSET_MASK, GC_DIDT_CTRL0__PHASE_OFFSET__SHIFT, 0x0000 },
579 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_SW_RST_MASK, GC_DIDT_CTRL0__DIDT_SW_RST__SHIFT, 0x0000 },
580 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK, GC_DIDT_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
581 { mmGC_DIDT_CTRL0, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT_MASK, GC_DIDT_CTRL0__DIDT_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
582 { 0xFFFFFFFF } /* End of list */
583};
584
585
586static const struct vega10_didt_config_reg PSMSEEDCStallPatternConfig_Vega10[] = {
587/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
588 * Offset Mask Shift Value
589 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
590 */
591 /* SQ EDC STALL PATTERNs */
592 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_1__SHIFT, 0x0101 },
593 { ixDIDT_SQ_EDC_STALL_PATTERN_1_2, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2_MASK, DIDT_SQ_EDC_STALL_PATTERN_1_2__EDC_STALL_PATTERN_2__SHIFT, 0x0101 },
594 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_3__SHIFT, 0x1111 },
595 { ixDIDT_SQ_EDC_STALL_PATTERN_3_4, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4_MASK, DIDT_SQ_EDC_STALL_PATTERN_3_4__EDC_STALL_PATTERN_4__SHIFT, 0x1111 },
596
597 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_5__SHIFT, 0x1515 },
598 { ixDIDT_SQ_EDC_STALL_PATTERN_5_6, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6_MASK, DIDT_SQ_EDC_STALL_PATTERN_5_6__EDC_STALL_PATTERN_6__SHIFT, 0x1515 },
599
600 { ixDIDT_SQ_EDC_STALL_PATTERN_7, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7_MASK, DIDT_SQ_EDC_STALL_PATTERN_7__EDC_STALL_PATTERN_7__SHIFT, 0x5555 },
601
602 { 0xFFFFFFFF } /* End of list */
603};
604
605static const struct vega10_didt_config_reg PSMSEEDCStallDelayConfig_Vega10[] = {
606/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
607 * Offset Mask Shift Value
608 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
609 */
610 /* SQ EDC STALL DELAYs */
611 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ0__SHIFT, 0x0000 },
612 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ1__SHIFT, 0x0000 },
613 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ2__SHIFT, 0x0000 },
614 { ixDIDT_SQ_EDC_STALL_DELAY_1, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3_MASK, DIDT_SQ_EDC_STALL_DELAY_1__EDC_STALL_DELAY_SQ3__SHIFT, 0x0000 },
615
616 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ4__SHIFT, 0x0000 },
617 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ5__SHIFT, 0x0000 },
618 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ6__SHIFT, 0x0000 },
619 { ixDIDT_SQ_EDC_STALL_DELAY_2, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7_MASK, DIDT_SQ_EDC_STALL_DELAY_2__EDC_STALL_DELAY_SQ7__SHIFT, 0x0000 },
620
621 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ8__SHIFT, 0x0000 },
622 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ9__SHIFT, 0x0000 },
623 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ10__SHIFT, 0x0000 },
624 { ixDIDT_SQ_EDC_STALL_DELAY_3, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11_MASK, DIDT_SQ_EDC_STALL_DELAY_3__EDC_STALL_DELAY_SQ11__SHIFT, 0x0000 },
625
626 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12__SHIFT, 0x0000 },
627 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ12_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ13__SHIFT, 0x0000 },
628 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ14__SHIFT, 0x0000 },
629 { ixDIDT_SQ_EDC_STALL_DELAY_4, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15_MASK, DIDT_SQ_EDC_STALL_DELAY_4__EDC_STALL_DELAY_SQ15__SHIFT, 0x0000 },
630
631 { 0xFFFFFFFF } /* End of list */
632};
633
634static const struct vega10_didt_config_reg PSMSEEDCCtrlResetConfig_Vega10[] = {
635/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
636 * Offset Mask Shift Value
637 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
638 */
639 /* SQ EDC CTRL */
640 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
641 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
642 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
643 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
644 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
645 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x0000 },
646 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
647 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0000 },
648 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0000 },
649 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
650 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
651
652 { 0xFFFFFFFF } /* End of list */
653};
654
655static const struct vega10_didt_config_reg PSMSEEDCCtrlConfig_Vega10[] = {
656/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
657 * Offset Mask Shift Value
658 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
659 */
660 /* SQ EDC CTRL */
661 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_EN_MASK, DIDT_SQ_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
662 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_SW_RST_MASK, DIDT_SQ_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
663 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, DIDT_SQ_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
664 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL_MASK, DIDT_SQ_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
665 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, DIDT_SQ_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
666 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS_MASK, DIDT_SQ_EDC_CTRL__EDC_STALL_PATTERN_BIT_NUMS__SHIFT, 0x000E },
667 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, DIDT_SQ_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
668 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_EN__SHIFT, 0x0001 },
669 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_STALL_POLICY__SHIFT, 0x0003 },
670 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__GC_EDC_LEVEL_COMB_EN__SHIFT, 0x0001 },
671 { ixDIDT_SQ_EDC_CTRL, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN_MASK, DIDT_SQ_EDC_CTRL__SE_EDC_LEVEL_COMB_EN__SHIFT, 0x0000 },
672
673 { 0xFFFFFFFF } /* End of list */
674};
675
676static const struct vega10_didt_config_reg PSMGCEDCDroopCtrlConfig_vega10[] = {
677/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
678 * Offset Mask Shift Value
679 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
680 */
681 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_EN__SHIFT, 0x0001 },
682 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_THRESHOLD__SHIFT, 0x0384 },
683 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX_MASK, GC_EDC_DROOP_CTRL__EDC_DROOP_LEVEL_INDEX__SHIFT, 0x0001 },
684 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__AVG_PSM_SEL_MASK, GC_EDC_DROOP_CTRL__AVG_PSM_SEL__SHIFT, 0x0001 },
685 { mmGC_EDC_DROOP_CTRL, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL_MASK, GC_EDC_DROOP_CTRL__EDC_LEVEL_SEL__SHIFT, 0x0001 },
686
687 { 0xFFFFFFFF } /* End of list */
688};
689
690static const struct vega10_didt_config_reg PSMGCEDCCtrlResetConfig_vega10[] = {
691/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
692 * Offset Mask Shift Value
693 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
694 */
695 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0000 },
696 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0001 },
697 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
698 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
699 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
700 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
701
702 { 0xFFFFFFFF } /* End of list */
703};
704
705static const struct vega10_didt_config_reg PSMGCEDCCtrlConfig_vega10[] = {
706/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
707 * Offset Mask Shift Value
708 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
709 */
710 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_EN_MASK, GC_EDC_CTRL__EDC_EN__SHIFT, 0x0001 },
711 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_SW_RST_MASK, GC_EDC_CTRL__EDC_SW_RST__SHIFT, 0x0000 },
712 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE_MASK, GC_EDC_CTRL__EDC_CLK_EN_OVERRIDE__SHIFT, 0x0000 },
713 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_FORCE_STALL_MASK, GC_EDC_CTRL__EDC_FORCE_STALL__SHIFT, 0x0000 },
714 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT_MASK, GC_EDC_CTRL__EDC_TRIGGER_THROTTLE_LOWBIT__SHIFT, 0x0000 },
715 { mmGC_EDC_CTRL, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA_MASK, GC_EDC_CTRL__EDC_ALLOW_WRITE_PWRDELTA__SHIFT, 0x0000 },
716
717 { 0xFFFFFFFF } /* End of list */
718};
719
720static const struct vega10_didt_config_reg AvfsPSMResetConfig_vega10[] = {
721/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
722 * Offset Mask Shift Value
723 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
724 */
725 { 0x16A02, 0xFFFFFFFF, 0x0, 0x0000005F },
726 { 0x16A05, 0xFFFFFFFF, 0x0, 0x00000001 },
727 { 0x16A06, 0x00000001, 0x0, 0x02000000 },
728 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
729
730 { 0xFFFFFFFF } /* End of list */
731};
732
733static const struct vega10_didt_config_reg AvfsPSMInitConfig_vega10[] = {
734/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
735 * Offset Mask Shift Value
736 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
737 */
738 { 0x16A05, 0xFFFFFFFF, 0x18, 0x00000001 },
739 { 0x16A05, 0xFFFFFFFF, 0x8, 0x00000003 },
740 { 0x16A05, 0xFFFFFFFF, 0xa, 0x00000006 },
741 { 0x16A05, 0xFFFFFFFF, 0x7, 0x00000000 },
742 { 0x16A06, 0xFFFFFFFF, 0x18, 0x00000001 },
743 { 0x16A06, 0xFFFFFFFF, 0x19, 0x00000001 },
744 { 0x16A01, 0xFFFFFFFF, 0x0, 0x00003027 },
745
746 { 0xFFFFFFFF } /* End of list */
747};
748
749static int vega10_program_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs, enum vega10_didt_config_reg_type reg_type)
750{
751 uint32_t data;
752
753 PP_ASSERT_WITH_CODE((config_regs != NULL), "[vega10_program_didt_config_registers] Invalid config register table!", return -EINVAL);
754
755 while (config_regs->offset != 0xFFFFFFFF) {
756 switch (reg_type) {
757 case VEGA10_CONFIGREG_DIDT:
758 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset);
759 data &= ~config_regs->mask;
760 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
761 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data);
762 break;
763 case VEGA10_CONFIGREG_GCCAC:
764 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset);
765 data &= ~config_regs->mask;
766 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
767 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data);
768 break;
769 case VEGA10_CONFIGREG_SECAC:
770 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset);
771 data &= ~config_regs->mask;
772 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
773 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_SE_CAC, config_regs->offset, data);
774 break;
775 default:
776 return -EINVAL;
777 }
778
779 config_regs++;
780 }
781
782 return 0;
783}
784
785static int vega10_program_gc_didt_config_registers(struct pp_hwmgr *hwmgr, const struct vega10_didt_config_reg *config_regs)
786{
787 uint32_t data;
788
789 while (config_regs->offset != 0xFFFFFFFF) {
790 data = cgs_read_register(hwmgr->device, config_regs->offset);
791 data &= ~config_regs->mask;
792 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
793 cgs_write_register(hwmgr->device, config_regs->offset, data);
794 config_regs++;
795 }
796
797 return 0;
798}
799
800static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable)
801{
802 uint32_t data;
803 uint32_t en = (enable ? 1 : 0);
804 uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
805
806 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
807 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
808 DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
809 didt_block_info &= ~SQ_Enable_MASK;
810 didt_block_info |= en << SQ_Enable_SHIFT;
811 }
812
813 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
814 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
815 DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
816 didt_block_info &= ~DB_Enable_MASK;
817 didt_block_info |= en << DB_Enable_SHIFT;
818 }
819
820 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
821 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
822 DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
823 didt_block_info &= ~TD_Enable_MASK;
824 didt_block_info |= en << TD_Enable_SHIFT;
825 }
826
827 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
828 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
829 DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
830 didt_block_info &= ~TCP_Enable_MASK;
831 didt_block_info |= en << TCP_Enable_SHIFT;
832 }
833
834 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
835 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,
836 DIDT_DBR_CTRL0, DIDT_CTRL_EN, en);
837 }
838
839 if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
840 if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
841 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
842 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
843 data = REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
844 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
845 }
846
847 if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
848 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
849 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
850 data = REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
851 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
852 }
853
854 if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
855 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
856 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
857 data = REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
858 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
859 }
860
861 if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
862 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
863 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
864 data = REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
865 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
866 }
867
868 if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
869 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
870 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
871 data = REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
872 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
873 }
874 }
875
876 /* For Vega10, SMC does not support any mask yet. */
877 if (enable)
878 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info,
879 NULL);
880
881}
882
883static int vega10_enable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
884{
885 struct amdgpu_device *adev = hwmgr->adev;
886 int result;
887 uint32_t num_se = 0, count, data;
888
889 num_se = adev->gfx.config.max_shader_engines;
890
891 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
892
893 mutex_lock(&adev->grbm_idx_mutex);
894 for (count = 0; count < num_se; count++) {
895 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
896 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
897
898 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
899 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
900 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
901 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl1Config_Vega10, VEGA10_CONFIGREG_DIDT);
902 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl2Config_Vega10, VEGA10_CONFIGREG_DIDT);
903 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
904 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtTuningCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
905 result |= vega10_program_didt_config_registers(hwmgr, SELCacConfig_Vega10, VEGA10_CONFIGREG_SECAC);
906 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
907
908 if (0 != result)
909 break;
910 }
911 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
912 mutex_unlock(&adev->grbm_idx_mutex);
913
914 vega10_didt_set_mask(hwmgr, true);
915
916 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
917
918 return 0;
919}
920
921static int vega10_disable_cac_driving_se_didt_config(struct pp_hwmgr *hwmgr)
922{
923 struct amdgpu_device *adev = hwmgr->adev;
924
925 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
926
927 vega10_didt_set_mask(hwmgr, false);
928
929 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
930
931 return 0;
932}
933
934static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
935{
936 struct amdgpu_device *adev = hwmgr->adev;
937 int result;
938 uint32_t num_se = 0, count, data;
939
940 num_se = adev->gfx.config.max_shader_engines;
941
942 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
943
944 mutex_lock(&adev->grbm_idx_mutex);
945 for (count = 0; count < num_se; count++) {
946 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
947 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
948
949 result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
950 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
951 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
952 result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
953 if (0 != result)
954 break;
955 }
956 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
957 mutex_unlock(&adev->grbm_idx_mutex);
958
959 vega10_didt_set_mask(hwmgr, true);
960
961 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
962
963 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
964 if (PP_CAP(PHM_PlatformCaps_GCEDC))
965 vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
966
967 if (PP_CAP(PHM_PlatformCaps_PSM))
968 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
969
970 return 0;
971}
972
973static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr)
974{
975 struct amdgpu_device *adev = hwmgr->adev;
976 uint32_t data;
977
978 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
979
980 vega10_didt_set_mask(hwmgr, false);
981
982 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
983
984 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
985 data = 0x00000000;
986 cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
987 }
988
989 if (PP_CAP(PHM_PlatformCaps_PSM))
990 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
991
992 return 0;
993}
994
995static int vega10_enable_se_edc_config(struct pp_hwmgr *hwmgr)
996{
997 struct amdgpu_device *adev = hwmgr->adev;
998 int result;
999 uint32_t num_se = 0, count, data;
1000
1001 num_se = adev->gfx.config.max_shader_engines;
1002
1003 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1004
1005 mutex_lock(&adev->grbm_idx_mutex);
1006 for (count = 0; count < num_se; count++) {
1007 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1008 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1009 result = vega10_program_didt_config_registers(hwmgr, SEDiDtWeightConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1010 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1011 result |= vega10_program_didt_config_registers(hwmgr, SEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1012 result |= vega10_program_didt_config_registers(hwmgr, SEEDCThresholdConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1013 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1014 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1015
1016 if (0 != result)
1017 break;
1018 }
1019 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1020 mutex_unlock(&adev->grbm_idx_mutex);
1021
1022 vega10_didt_set_mask(hwmgr, true);
1023
1024 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1025
1026 return 0;
1027}
1028
1029static int vega10_disable_se_edc_config(struct pp_hwmgr *hwmgr)
1030{
1031 struct amdgpu_device *adev = hwmgr->adev;
1032
1033 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1034
1035 vega10_didt_set_mask(hwmgr, false);
1036
1037 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1038
1039 return 0;
1040}
1041
1042static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1043{
1044 struct amdgpu_device *adev = hwmgr->adev;
1045 int result = 0;
1046 uint32_t num_se = 0;
1047 uint32_t count, data;
1048
1049 num_se = adev->gfx.config.max_shader_engines;
1050
1051 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1052
1053 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1054
1055 mutex_lock(&adev->grbm_idx_mutex);
1056 for (count = 0; count < num_se; count++) {
1057 data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1058 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1059 result = vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1060 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1061 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1062 result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1063
1064 if (0 != result)
1065 break;
1066 }
1067 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1068 mutex_unlock(&adev->grbm_idx_mutex);
1069
1070 vega10_didt_set_mask(hwmgr, true);
1071
1072 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1073
1074 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
1075
1076 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1077 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
1078 vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
1079 }
1080
1081 if (PP_CAP(PHM_PlatformCaps_PSM))
1082 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
1083
1084 return 0;
1085}
1086
1087static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr)
1088{
1089 struct amdgpu_device *adev = hwmgr->adev;
1090 uint32_t data;
1091
1092 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1093
1094 vega10_didt_set_mask(hwmgr, false);
1095
1096 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1097
1098 if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
1099 data = 0x00000000;
1100 cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
1101 }
1102
1103 if (PP_CAP(PHM_PlatformCaps_PSM))
1104 vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
1105
1106 return 0;
1107}
1108
1109static int vega10_enable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1110{
1111 struct amdgpu_device *adev = hwmgr->adev;
1112 int result;
1113
1114 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
1115
1116 mutex_lock(&adev->grbm_idx_mutex);
1117 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000);
1118 mutex_unlock(&adev->grbm_idx_mutex);
1119
1120 result = vega10_program_didt_config_registers(hwmgr, SEEDCForceStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1121 result |= vega10_program_didt_config_registers(hwmgr, SEEDCCtrlForceStallConfig_Vega10, VEGA10_CONFIGREG_DIDT);
1122 if (0 != result)
1123 return result;
1124
1125 vega10_didt_set_mask(hwmgr, false);
1126
1127 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
1128
1129 return 0;
1130}
1131
1132static int vega10_disable_se_edc_force_stall_config(struct pp_hwmgr *hwmgr)
1133{
1134 int result;
1135
1136 result = vega10_disable_se_edc_config(hwmgr);
1137 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Pre DIDT disable clock gating failed!", return result);
1138
1139 return 0;
1140}
1141
1142int vega10_enable_didt_config(struct pp_hwmgr *hwmgr)
1143{
1144 int result = 0;
1145 struct vega10_hwmgr *data = hwmgr->backend;
1146
1147 if (data->smu_features[GNLD_DIDT].supported) {
1148 if (data->smu_features[GNLD_DIDT].enabled)
1149 PP_DBG_LOG("[EnableDiDtConfig] Feature DiDt Already enabled!\n");
1150
1151 switch (data->registry_data.didt_mode) {
1152 case 0:
1153 result = vega10_enable_cac_driving_se_didt_config(hwmgr);
1154 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 0 Failed!", return result);
1155 break;
1156 case 2:
1157 result = vega10_enable_psm_gc_didt_config(hwmgr);
1158 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 2 Failed!", return result);
1159 break;
1160 case 3:
1161 result = vega10_enable_se_edc_config(hwmgr);
1162 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 3 Failed!", return result);
1163 break;
1164 case 1:
1165 case 4:
1166 case 5:
1167 result = vega10_enable_psm_gc_edc_config(hwmgr);
1168 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 5 Failed!", return result);
1169 break;
1170 case 6:
1171 result = vega10_enable_se_edc_force_stall_config(hwmgr);
1172 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDt] Attempt to enable DiDt Mode 6 Failed!", return result);
1173 break;
1174 default:
1175 result = -EINVAL;
1176 break;
1177 }
1178
1179 if (0 == result) {
1180 result = vega10_enable_smc_features(hwmgr, true, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1181 PP_ASSERT_WITH_CODE((0 == result), "[EnableDiDtConfig] Attempt to Enable DiDt feature Failed!", return result);
1182 data->smu_features[GNLD_DIDT].enabled = true;
1183 }
1184 }
1185
1186 return result;
1187}
1188
1189int vega10_disable_didt_config(struct pp_hwmgr *hwmgr)
1190{
1191 int result = 0;
1192 struct vega10_hwmgr *data = hwmgr->backend;
1193
1194 if (data->smu_features[GNLD_DIDT].supported) {
1195 if (!data->smu_features[GNLD_DIDT].enabled)
1196 PP_DBG_LOG("[DisableDiDtConfig] Feature DiDt Already Disabled!\n");
1197
1198 switch (data->registry_data.didt_mode) {
1199 case 0:
1200 result = vega10_disable_cac_driving_se_didt_config(hwmgr);
1201 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 0 Failed!", return result);
1202 break;
1203 case 2:
1204 result = vega10_disable_psm_gc_didt_config(hwmgr);
1205 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 2 Failed!", return result);
1206 break;
1207 case 3:
1208 result = vega10_disable_se_edc_config(hwmgr);
1209 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 3 Failed!", return result);
1210 break;
1211 case 1:
1212 case 4:
1213 case 5:
1214 result = vega10_disable_psm_gc_edc_config(hwmgr);
1215 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 5 Failed!", return result);
1216 break;
1217 case 6:
1218 result = vega10_disable_se_edc_force_stall_config(hwmgr);
1219 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDt] Attempt to disable DiDt Mode 6 Failed!", return result);
1220 break;
1221 default:
1222 result = -EINVAL;
1223 break;
1224 }
1225
1226 if (0 == result) {
1227 result = vega10_enable_smc_features(hwmgr, false, data->smu_features[GNLD_DIDT].smu_feature_bitmap);
1228 PP_ASSERT_WITH_CODE((0 == result), "[DisableDiDtConfig] Attempt to Disable DiDt feature Failed!", return result);
1229 data->smu_features[GNLD_DIDT].enabled = false;
1230 }
1231 }
1232
1233 return result;
1234}
1235
1236void vega10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1237{
1238 struct vega10_hwmgr *data = hwmgr->backend;
1239 struct phm_ppt_v2_information *table_info =
1240 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1241 struct phm_tdp_table *tdp_table = table_info->tdp_table;
1242 PPTable_t *table = &(data->smc_state_table.pp_table);
1243
1244 table->SocketPowerLimit = cpu_to_le16(
1245 tdp_table->usMaximumPowerDeliveryLimit);
1246 table->TdcLimit = cpu_to_le16(tdp_table->usTDC);
1247 table->EdcLimit = cpu_to_le16(tdp_table->usEDCLimit);
1248 table->TedgeLimit = cpu_to_le16(tdp_table->usTemperatureLimitTedge);
1249 table->ThotspotLimit = cpu_to_le16(tdp_table->usTemperatureLimitHotspot);
1250 table->ThbmLimit = cpu_to_le16(tdp_table->usTemperatureLimitHBM);
1251 table->Tvr_socLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrVddc);
1252 table->Tvr_memLimit = cpu_to_le16(tdp_table->usTemperatureLimitVrMvdd);
1253 table->Tliquid1Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid1);
1254 table->Tliquid2Limit = cpu_to_le16(tdp_table->usTemperatureLimitLiquid2);
1255 table->TplxLimit = cpu_to_le16(tdp_table->usTemperatureLimitPlx);
1256 table->LoadLineResistance =
1257 hwmgr->platform_descriptor.LoadLineSlope * 256;
1258 table->FitLimit = 0; /* Not used for Vega10 */
1259
1260 table->Liquid1_I2C_address = tdp_table->ucLiquid1_I2C_address;
1261 table->Liquid2_I2C_address = tdp_table->ucLiquid2_I2C_address;
1262 table->Vr_I2C_address = tdp_table->ucVr_I2C_address;
1263 table->Plx_I2C_address = tdp_table->ucPlx_I2C_address;
1264
1265 table->Liquid_I2C_LineSCL = tdp_table->ucLiquid_I2C_Line;
1266 table->Liquid_I2C_LineSDA = tdp_table->ucLiquid_I2C_LineSDA;
1267
1268 table->Vr_I2C_LineSCL = tdp_table->ucVr_I2C_Line;
1269 table->Vr_I2C_LineSDA = tdp_table->ucVr_I2C_LineSDA;
1270
1271 table->Plx_I2C_LineSCL = tdp_table->ucPlx_I2C_Line;
1272 table->Plx_I2C_LineSDA = tdp_table->ucPlx_I2C_LineSDA;
1273}
1274
1275int vega10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1276{
1277 struct vega10_hwmgr *data = hwmgr->backend;
1278
1279 if (data->registry_data.enable_pkg_pwr_tracking_feature)
1280 smum_send_msg_to_smc_with_parameter(hwmgr,
1281 PPSMC_MSG_SetPptLimit, n,
1282 NULL);
1283
1284 return 0;
1285}
1286
1287int vega10_enable_power_containment(struct pp_hwmgr *hwmgr)
1288{
1289 struct vega10_hwmgr *data = hwmgr->backend;
1290 struct phm_ppt_v2_information *table_info =
1291 (struct phm_ppt_v2_information *)(hwmgr->pptable);
1292 struct phm_tdp_table *tdp_table = table_info->tdp_table;
1293 int result = 0;
1294
1295 hwmgr->default_power_limit = hwmgr->power_limit =
1296 (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
1297
1298 if (!hwmgr->not_vf)
1299 return 0;
1300
1301 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1302 if (data->smu_features[GNLD_PPT].supported)
1303 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1304 true, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1305 "Attempt to enable PPT feature Failed!",
1306 data->smu_features[GNLD_PPT].supported = false);
1307
1308 if (data->smu_features[GNLD_TDC].supported)
1309 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1310 true, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1311 "Attempt to enable PPT feature Failed!",
1312 data->smu_features[GNLD_TDC].supported = false);
1313
1314 result = vega10_set_power_limit(hwmgr, hwmgr->power_limit);
1315 PP_ASSERT_WITH_CODE(!result,
1316 "Failed to set Default Power Limit in SMC!",
1317 return result);
1318 }
1319
1320 return result;
1321}
1322
1323int vega10_disable_power_containment(struct pp_hwmgr *hwmgr)
1324{
1325 struct vega10_hwmgr *data = hwmgr->backend;
1326
1327 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1328 if (data->smu_features[GNLD_PPT].supported)
1329 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1330 false, data->smu_features[GNLD_PPT].smu_feature_bitmap),
1331 "Attempt to disable PPT feature Failed!",
1332 data->smu_features[GNLD_PPT].supported = false);
1333
1334 if (data->smu_features[GNLD_TDC].supported)
1335 PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
1336 false, data->smu_features[GNLD_TDC].smu_feature_bitmap),
1337 "Attempt to disable PPT feature Failed!",
1338 data->smu_features[GNLD_TDC].supported = false);
1339 }
1340
1341 return 0;
1342}
1343
1344static void vega10_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
1345 uint32_t adjust_percent)
1346{
1347 smum_send_msg_to_smc_with_parameter(hwmgr,
1348 PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
1349 NULL);
1350}
1351
1352int vega10_power_control_set_level(struct pp_hwmgr *hwmgr)
1353{
1354 int adjust_percent;
1355
1356 if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
1357 adjust_percent =
1358 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1359 hwmgr->platform_descriptor.TDPAdjustment :
1360 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1361 vega10_set_overdrive_target_percentage(hwmgr,
1362 (uint32_t)adjust_percent);
1363 }
1364 return 0;
1365}