Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/fault-inject.h>
10#include <linux/of_address.h>
11#include <linux/uaccess.h>
12
13#include <drm/drm_drv.h>
14#include <drm/drm_file.h>
15#include <drm/drm_ioctl.h>
16#include <drm/drm_of.h>
17
18#include "msm_drv.h"
19#include "msm_debugfs.h"
20#include "msm_kms.h"
21#include "adreno/adreno_gpu.h"
22
23/*
24 * MSM driver version:
25 * - 1.0.0 - initial interface
26 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
27 * - 1.2.0 - adds explicit fence support for submit ioctl
28 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
29 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
30 * MSM_GEM_INFO ioctl.
31 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
32 * GEM object's debug name
33 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
34 * - 1.6.0 - Syncobj support
35 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
36 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
37 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
38 * - 1.10.0 - Add MSM_SUBMIT_BO_NO_IMPLICIT
39 * - 1.11.0 - Add wait boost (MSM_WAIT_FENCE_BOOST, MSM_PREP_BOOST)
40 * - 1.12.0 - Add MSM_INFO_SET_METADATA and MSM_INFO_GET_METADATA
41 */
42#define MSM_VERSION_MAJOR 1
43#define MSM_VERSION_MINOR 12
44#define MSM_VERSION_PATCHLEVEL 0
45
46static void msm_deinit_vram(struct drm_device *ddev);
47
48static char *vram = "16m";
49MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
50module_param(vram, charp, 0);
51
52bool dumpstate;
53MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
54module_param(dumpstate, bool, 0600);
55
56static bool modeset = true;
57MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
58module_param(modeset, bool, 0600);
59
60#ifdef CONFIG_FAULT_INJECTION
61DECLARE_FAULT_ATTR(fail_gem_alloc);
62DECLARE_FAULT_ATTR(fail_gem_iova);
63#endif
64
65static int msm_drm_uninit(struct device *dev)
66{
67 struct platform_device *pdev = to_platform_device(dev);
68 struct msm_drm_private *priv = platform_get_drvdata(pdev);
69 struct drm_device *ddev = priv->dev;
70
71 /*
72 * Shutdown the hw if we're far enough along where things might be on.
73 * If we run this too early, we'll end up panicking in any variety of
74 * places. Since we don't register the drm device until late in
75 * msm_drm_init, drm_dev->registered is used as an indicator that the
76 * shutdown will be successful.
77 */
78 if (ddev->registered) {
79 drm_dev_unregister(ddev);
80 if (priv->kms)
81 drm_atomic_helper_shutdown(ddev);
82 }
83
84 /* We must cancel and cleanup any pending vblank enable/disable
85 * work before msm_irq_uninstall() to avoid work re-enabling an
86 * irq after uninstall has disabled it.
87 */
88
89 flush_workqueue(priv->wq);
90
91 msm_gem_shrinker_cleanup(ddev);
92
93 msm_perf_debugfs_cleanup(priv);
94 msm_rd_debugfs_cleanup(priv);
95
96 if (priv->kms)
97 msm_drm_kms_uninit(dev);
98
99 msm_deinit_vram(ddev);
100
101 component_unbind_all(dev, ddev);
102
103 ddev->dev_private = NULL;
104 drm_dev_put(ddev);
105
106 destroy_workqueue(priv->wq);
107
108 return 0;
109}
110
111bool msm_use_mmu(struct drm_device *dev)
112{
113 struct msm_drm_private *priv = dev->dev_private;
114
115 /*
116 * a2xx comes with its own MMU
117 * On other platforms IOMMU can be declared specified either for the
118 * MDP/DPU device or for its parent, MDSS device.
119 */
120 return priv->is_a2xx ||
121 device_iommu_mapped(dev->dev) ||
122 device_iommu_mapped(dev->dev->parent);
123}
124
125static int msm_init_vram(struct drm_device *dev)
126{
127 struct msm_drm_private *priv = dev->dev_private;
128 struct device_node *node;
129 unsigned long size = 0;
130 int ret = 0;
131
132 /* In the device-tree world, we could have a 'memory-region'
133 * phandle, which gives us a link to our "vram". Allocating
134 * is all nicely abstracted behind the dma api, but we need
135 * to know the entire size to allocate it all in one go. There
136 * are two cases:
137 * 1) device with no IOMMU, in which case we need exclusive
138 * access to a VRAM carveout big enough for all gpu
139 * buffers
140 * 2) device with IOMMU, but where the bootloader puts up
141 * a splash screen. In this case, the VRAM carveout
142 * need only be large enough for fbdev fb. But we need
143 * exclusive access to the buffer to avoid the kernel
144 * using those pages for other purposes (which appears
145 * as corruption on screen before we have a chance to
146 * load and do initial modeset)
147 */
148
149 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
150 if (node) {
151 struct resource r;
152 ret = of_address_to_resource(node, 0, &r);
153 of_node_put(node);
154 if (ret)
155 return ret;
156 size = r.end - r.start + 1;
157 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
158
159 /* if we have no IOMMU, then we need to use carveout allocator.
160 * Grab the entire DMA chunk carved out in early startup in
161 * mach-msm:
162 */
163 } else if (!msm_use_mmu(dev)) {
164 DRM_INFO("using %s VRAM carveout\n", vram);
165 size = memparse(vram, NULL);
166 }
167
168 if (size) {
169 unsigned long attrs = 0;
170 void *p;
171
172 priv->vram.size = size;
173
174 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
175 spin_lock_init(&priv->vram.lock);
176
177 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
178 attrs |= DMA_ATTR_WRITE_COMBINE;
179
180 /* note that for no-kernel-mapping, the vaddr returned
181 * is bogus, but non-null if allocation succeeded:
182 */
183 p = dma_alloc_attrs(dev->dev, size,
184 &priv->vram.paddr, GFP_KERNEL, attrs);
185 if (!p) {
186 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
187 priv->vram.paddr = 0;
188 return -ENOMEM;
189 }
190
191 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
192 (uint32_t)priv->vram.paddr,
193 (uint32_t)(priv->vram.paddr + size));
194 }
195
196 return ret;
197}
198
199static void msm_deinit_vram(struct drm_device *ddev)
200{
201 struct msm_drm_private *priv = ddev->dev_private;
202 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
203
204 if (!priv->vram.paddr)
205 return;
206
207 drm_mm_takedown(&priv->vram.mm);
208 dma_free_attrs(ddev->dev, priv->vram.size, NULL, priv->vram.paddr,
209 attrs);
210}
211
212static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
213{
214 struct msm_drm_private *priv = dev_get_drvdata(dev);
215 struct drm_device *ddev;
216 int ret;
217
218 if (drm_firmware_drivers_only())
219 return -ENODEV;
220
221 ddev = drm_dev_alloc(drv, dev);
222 if (IS_ERR(ddev)) {
223 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
224 return PTR_ERR(ddev);
225 }
226 ddev->dev_private = priv;
227 priv->dev = ddev;
228
229 priv->wq = alloc_ordered_workqueue("msm", 0);
230 if (!priv->wq) {
231 ret = -ENOMEM;
232 goto err_put_dev;
233 }
234
235 INIT_LIST_HEAD(&priv->objects);
236 mutex_init(&priv->obj_lock);
237
238 /*
239 * Initialize the LRUs:
240 */
241 mutex_init(&priv->lru.lock);
242 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
243 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
244 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
245 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
246
247 /* Teach lockdep about lock ordering wrt. shrinker: */
248 fs_reclaim_acquire(GFP_KERNEL);
249 might_lock(&priv->lru.lock);
250 fs_reclaim_release(GFP_KERNEL);
251
252 if (priv->kms_init) {
253 ret = drmm_mode_config_init(ddev);
254 if (ret)
255 goto err_destroy_wq;
256 }
257
258 ret = msm_init_vram(ddev);
259 if (ret)
260 goto err_destroy_wq;
261
262 dma_set_max_seg_size(dev, UINT_MAX);
263
264 /* Bind all our sub-components: */
265 ret = component_bind_all(dev, ddev);
266 if (ret)
267 goto err_deinit_vram;
268
269 ret = msm_gem_shrinker_init(ddev);
270 if (ret)
271 goto err_msm_uninit;
272
273 if (priv->kms_init) {
274 ret = msm_drm_kms_init(dev, drv);
275 if (ret)
276 goto err_msm_uninit;
277 } else {
278 /* valid only for the dummy headless case, where of_node=NULL */
279 WARN_ON(dev->of_node);
280 ddev->driver_features &= ~DRIVER_MODESET;
281 ddev->driver_features &= ~DRIVER_ATOMIC;
282 }
283
284 ret = drm_dev_register(ddev, 0);
285 if (ret)
286 goto err_msm_uninit;
287
288 ret = msm_debugfs_late_init(ddev);
289 if (ret)
290 goto err_msm_uninit;
291
292 if (priv->kms_init) {
293 drm_kms_helper_poll_init(ddev);
294 msm_fbdev_setup(ddev);
295 }
296
297 return 0;
298
299err_msm_uninit:
300 msm_drm_uninit(dev);
301
302 return ret;
303
304err_deinit_vram:
305 msm_deinit_vram(ddev);
306err_destroy_wq:
307 destroy_workqueue(priv->wq);
308err_put_dev:
309 drm_dev_put(ddev);
310
311 return ret;
312}
313
314/*
315 * DRM operations:
316 */
317
318static void load_gpu(struct drm_device *dev)
319{
320 static DEFINE_MUTEX(init_lock);
321 struct msm_drm_private *priv = dev->dev_private;
322
323 mutex_lock(&init_lock);
324
325 if (!priv->gpu)
326 priv->gpu = adreno_load_gpu(dev);
327
328 mutex_unlock(&init_lock);
329}
330
331static int context_init(struct drm_device *dev, struct drm_file *file)
332{
333 static atomic_t ident = ATOMIC_INIT(0);
334 struct msm_drm_private *priv = dev->dev_private;
335 struct msm_file_private *ctx;
336
337 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
338 if (!ctx)
339 return -ENOMEM;
340
341 INIT_LIST_HEAD(&ctx->submitqueues);
342 rwlock_init(&ctx->queuelock);
343
344 kref_init(&ctx->ref);
345 msm_submitqueue_init(dev, ctx);
346
347 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
348 file->driver_priv = ctx;
349
350 ctx->seqno = atomic_inc_return(&ident);
351
352 return 0;
353}
354
355static int msm_open(struct drm_device *dev, struct drm_file *file)
356{
357 /* For now, load gpu on open.. to avoid the requirement of having
358 * firmware in the initrd.
359 */
360 load_gpu(dev);
361
362 return context_init(dev, file);
363}
364
365static void context_close(struct msm_file_private *ctx)
366{
367 msm_submitqueue_close(ctx);
368 msm_file_private_put(ctx);
369}
370
371static void msm_postclose(struct drm_device *dev, struct drm_file *file)
372{
373 struct msm_drm_private *priv = dev->dev_private;
374 struct msm_file_private *ctx = file->driver_priv;
375
376 /*
377 * It is not possible to set sysprof param to non-zero if gpu
378 * is not initialized:
379 */
380 if (priv->gpu)
381 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
382
383 context_close(ctx);
384}
385
386/*
387 * DRM ioctls:
388 */
389
390static int msm_ioctl_get_param(struct drm_device *dev, void *data,
391 struct drm_file *file)
392{
393 struct msm_drm_private *priv = dev->dev_private;
394 struct drm_msm_param *args = data;
395 struct msm_gpu *gpu;
396
397 /* for now, we just have 3d pipe.. eventually this would need to
398 * be more clever to dispatch to appropriate gpu module:
399 */
400 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
401 return -EINVAL;
402
403 gpu = priv->gpu;
404
405 if (!gpu)
406 return -ENXIO;
407
408 return gpu->funcs->get_param(gpu, file->driver_priv,
409 args->param, &args->value, &args->len);
410}
411
412static int msm_ioctl_set_param(struct drm_device *dev, void *data,
413 struct drm_file *file)
414{
415 struct msm_drm_private *priv = dev->dev_private;
416 struct drm_msm_param *args = data;
417 struct msm_gpu *gpu;
418
419 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
420 return -EINVAL;
421
422 gpu = priv->gpu;
423
424 if (!gpu)
425 return -ENXIO;
426
427 return gpu->funcs->set_param(gpu, file->driver_priv,
428 args->param, args->value, args->len);
429}
430
431static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
432 struct drm_file *file)
433{
434 struct drm_msm_gem_new *args = data;
435 uint32_t flags = args->flags;
436
437 if (args->flags & ~MSM_BO_FLAGS) {
438 DRM_ERROR("invalid flags: %08x\n", args->flags);
439 return -EINVAL;
440 }
441
442 /*
443 * Uncached CPU mappings are deprecated, as of:
444 *
445 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
446 *
447 * So promote them to WC.
448 */
449 if (flags & MSM_BO_UNCACHED) {
450 flags &= ~MSM_BO_CACHED;
451 flags |= MSM_BO_WC;
452 }
453
454 if (should_fail(&fail_gem_alloc, args->size))
455 return -ENOMEM;
456
457 return msm_gem_new_handle(dev, file, args->size,
458 args->flags, &args->handle, NULL);
459}
460
461static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
462{
463 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
464}
465
466static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
467 struct drm_file *file)
468{
469 struct drm_msm_gem_cpu_prep *args = data;
470 struct drm_gem_object *obj;
471 ktime_t timeout = to_ktime(args->timeout);
472 int ret;
473
474 if (args->op & ~MSM_PREP_FLAGS) {
475 DRM_ERROR("invalid op: %08x\n", args->op);
476 return -EINVAL;
477 }
478
479 obj = drm_gem_object_lookup(file, args->handle);
480 if (!obj)
481 return -ENOENT;
482
483 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
484
485 drm_gem_object_put(obj);
486
487 return ret;
488}
489
490static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
491 struct drm_file *file)
492{
493 struct drm_msm_gem_cpu_fini *args = data;
494 struct drm_gem_object *obj;
495 int ret;
496
497 obj = drm_gem_object_lookup(file, args->handle);
498 if (!obj)
499 return -ENOENT;
500
501 ret = msm_gem_cpu_fini(obj);
502
503 drm_gem_object_put(obj);
504
505 return ret;
506}
507
508static int msm_ioctl_gem_info_iova(struct drm_device *dev,
509 struct drm_file *file, struct drm_gem_object *obj,
510 uint64_t *iova)
511{
512 struct msm_drm_private *priv = dev->dev_private;
513 struct msm_file_private *ctx = file->driver_priv;
514
515 if (!priv->gpu)
516 return -EINVAL;
517
518 if (should_fail(&fail_gem_iova, obj->size))
519 return -ENOMEM;
520
521 /*
522 * Don't pin the memory here - just get an address so that userspace can
523 * be productive
524 */
525 return msm_gem_get_iova(obj, ctx->aspace, iova);
526}
527
528static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
529 struct drm_file *file, struct drm_gem_object *obj,
530 uint64_t iova)
531{
532 struct msm_drm_private *priv = dev->dev_private;
533 struct msm_file_private *ctx = file->driver_priv;
534
535 if (!priv->gpu)
536 return -EINVAL;
537
538 /* Only supported if per-process address space is supported: */
539 if (priv->gpu->aspace == ctx->aspace)
540 return -EOPNOTSUPP;
541
542 if (should_fail(&fail_gem_iova, obj->size))
543 return -ENOMEM;
544
545 return msm_gem_set_iova(obj, ctx->aspace, iova);
546}
547
548static int msm_ioctl_gem_info_set_metadata(struct drm_gem_object *obj,
549 __user void *metadata,
550 u32 metadata_size)
551{
552 struct msm_gem_object *msm_obj = to_msm_bo(obj);
553 void *buf;
554 int ret;
555
556 /* Impose a moderate upper bound on metadata size: */
557 if (metadata_size > 128) {
558 return -EOVERFLOW;
559 }
560
561 /* Use a temporary buf to keep copy_from_user() outside of gem obj lock: */
562 buf = memdup_user(metadata, metadata_size);
563 if (IS_ERR(buf))
564 return PTR_ERR(buf);
565
566 ret = msm_gem_lock_interruptible(obj);
567 if (ret)
568 goto out;
569
570 msm_obj->metadata =
571 krealloc(msm_obj->metadata, metadata_size, GFP_KERNEL);
572 msm_obj->metadata_size = metadata_size;
573 memcpy(msm_obj->metadata, buf, metadata_size);
574
575 msm_gem_unlock(obj);
576
577out:
578 kfree(buf);
579
580 return ret;
581}
582
583static int msm_ioctl_gem_info_get_metadata(struct drm_gem_object *obj,
584 __user void *metadata,
585 u32 *metadata_size)
586{
587 struct msm_gem_object *msm_obj = to_msm_bo(obj);
588 void *buf;
589 int ret, len;
590
591 if (!metadata) {
592 /*
593 * Querying the size is inherently racey, but
594 * EXT_external_objects expects the app to confirm
595 * via device and driver UUIDs that the exporter and
596 * importer versions match. All we can do from the
597 * kernel side is check the length under obj lock
598 * when userspace tries to retrieve the metadata
599 */
600 *metadata_size = msm_obj->metadata_size;
601 return 0;
602 }
603
604 ret = msm_gem_lock_interruptible(obj);
605 if (ret)
606 return ret;
607
608 /* Avoid copy_to_user() under gem obj lock: */
609 len = msm_obj->metadata_size;
610 buf = kmemdup(msm_obj->metadata, len, GFP_KERNEL);
611
612 msm_gem_unlock(obj);
613
614 if (*metadata_size < len) {
615 ret = -ETOOSMALL;
616 } else if (copy_to_user(metadata, buf, len)) {
617 ret = -EFAULT;
618 } else {
619 *metadata_size = len;
620 }
621
622 kfree(buf);
623
624 return 0;
625}
626
627static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
628 struct drm_file *file)
629{
630 struct drm_msm_gem_info *args = data;
631 struct drm_gem_object *obj;
632 struct msm_gem_object *msm_obj;
633 int i, ret = 0;
634
635 if (args->pad)
636 return -EINVAL;
637
638 switch (args->info) {
639 case MSM_INFO_GET_OFFSET:
640 case MSM_INFO_GET_IOVA:
641 case MSM_INFO_SET_IOVA:
642 case MSM_INFO_GET_FLAGS:
643 /* value returned as immediate, not pointer, so len==0: */
644 if (args->len)
645 return -EINVAL;
646 break;
647 case MSM_INFO_SET_NAME:
648 case MSM_INFO_GET_NAME:
649 case MSM_INFO_SET_METADATA:
650 case MSM_INFO_GET_METADATA:
651 break;
652 default:
653 return -EINVAL;
654 }
655
656 obj = drm_gem_object_lookup(file, args->handle);
657 if (!obj)
658 return -ENOENT;
659
660 msm_obj = to_msm_bo(obj);
661
662 switch (args->info) {
663 case MSM_INFO_GET_OFFSET:
664 args->value = msm_gem_mmap_offset(obj);
665 break;
666 case MSM_INFO_GET_IOVA:
667 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
668 break;
669 case MSM_INFO_SET_IOVA:
670 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
671 break;
672 case MSM_INFO_GET_FLAGS:
673 if (obj->import_attach) {
674 ret = -EINVAL;
675 break;
676 }
677 /* Hide internal kernel-only flags: */
678 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
679 ret = 0;
680 break;
681 case MSM_INFO_SET_NAME:
682 /* length check should leave room for terminating null: */
683 if (args->len >= sizeof(msm_obj->name)) {
684 ret = -EINVAL;
685 break;
686 }
687 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
688 args->len)) {
689 msm_obj->name[0] = '\0';
690 ret = -EFAULT;
691 break;
692 }
693 msm_obj->name[args->len] = '\0';
694 for (i = 0; i < args->len; i++) {
695 if (!isprint(msm_obj->name[i])) {
696 msm_obj->name[i] = '\0';
697 break;
698 }
699 }
700 break;
701 case MSM_INFO_GET_NAME:
702 if (args->value && (args->len < strlen(msm_obj->name))) {
703 ret = -ETOOSMALL;
704 break;
705 }
706 args->len = strlen(msm_obj->name);
707 if (args->value) {
708 if (copy_to_user(u64_to_user_ptr(args->value),
709 msm_obj->name, args->len))
710 ret = -EFAULT;
711 }
712 break;
713 case MSM_INFO_SET_METADATA:
714 ret = msm_ioctl_gem_info_set_metadata(
715 obj, u64_to_user_ptr(args->value), args->len);
716 break;
717 case MSM_INFO_GET_METADATA:
718 ret = msm_ioctl_gem_info_get_metadata(
719 obj, u64_to_user_ptr(args->value), &args->len);
720 break;
721 }
722
723 drm_gem_object_put(obj);
724
725 return ret;
726}
727
728static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
729 ktime_t timeout, uint32_t flags)
730{
731 struct dma_fence *fence;
732 int ret;
733
734 if (fence_after(fence_id, queue->last_fence)) {
735 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
736 fence_id, queue->last_fence);
737 return -EINVAL;
738 }
739
740 /*
741 * Map submitqueue scoped "seqno" (which is actually an idr key)
742 * back to underlying dma-fence
743 *
744 * The fence is removed from the fence_idr when the submit is
745 * retired, so if the fence is not found it means there is nothing
746 * to wait for
747 */
748 spin_lock(&queue->idr_lock);
749 fence = idr_find(&queue->fence_idr, fence_id);
750 if (fence)
751 fence = dma_fence_get_rcu(fence);
752 spin_unlock(&queue->idr_lock);
753
754 if (!fence)
755 return 0;
756
757 if (flags & MSM_WAIT_FENCE_BOOST)
758 dma_fence_set_deadline(fence, ktime_get());
759
760 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
761 if (ret == 0) {
762 ret = -ETIMEDOUT;
763 } else if (ret != -ERESTARTSYS) {
764 ret = 0;
765 }
766
767 dma_fence_put(fence);
768
769 return ret;
770}
771
772static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
773 struct drm_file *file)
774{
775 struct msm_drm_private *priv = dev->dev_private;
776 struct drm_msm_wait_fence *args = data;
777 struct msm_gpu_submitqueue *queue;
778 int ret;
779
780 if (args->flags & ~MSM_WAIT_FENCE_FLAGS) {
781 DRM_ERROR("invalid flags: %08x\n", args->flags);
782 return -EINVAL;
783 }
784
785 if (!priv->gpu)
786 return 0;
787
788 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
789 if (!queue)
790 return -ENOENT;
791
792 ret = wait_fence(queue, args->fence, to_ktime(args->timeout), args->flags);
793
794 msm_submitqueue_put(queue);
795
796 return ret;
797}
798
799static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
800 struct drm_file *file)
801{
802 struct drm_msm_gem_madvise *args = data;
803 struct drm_gem_object *obj;
804 int ret;
805
806 switch (args->madv) {
807 case MSM_MADV_DONTNEED:
808 case MSM_MADV_WILLNEED:
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 obj = drm_gem_object_lookup(file, args->handle);
815 if (!obj) {
816 return -ENOENT;
817 }
818
819 ret = msm_gem_madvise(obj, args->madv);
820 if (ret >= 0) {
821 args->retained = ret;
822 ret = 0;
823 }
824
825 drm_gem_object_put(obj);
826
827 return ret;
828}
829
830
831static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
832 struct drm_file *file)
833{
834 struct drm_msm_submitqueue *args = data;
835
836 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
837 return -EINVAL;
838
839 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
840 args->flags, &args->id);
841}
842
843static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
844 struct drm_file *file)
845{
846 return msm_submitqueue_query(dev, file->driver_priv, data);
847}
848
849static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
850 struct drm_file *file)
851{
852 u32 id = *(u32 *) data;
853
854 return msm_submitqueue_remove(file->driver_priv, id);
855}
856
857static const struct drm_ioctl_desc msm_ioctls[] = {
858 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
859 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
860 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
861 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
862 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
863 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
864 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
865 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
866 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
867 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
868 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
869 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
870};
871
872static void msm_show_fdinfo(struct drm_printer *p, struct drm_file *file)
873{
874 struct drm_device *dev = file->minor->dev;
875 struct msm_drm_private *priv = dev->dev_private;
876
877 if (!priv->gpu)
878 return;
879
880 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, p);
881
882 drm_show_memory_stats(p, file);
883}
884
885static const struct file_operations fops = {
886 .owner = THIS_MODULE,
887 DRM_GEM_FOPS,
888 .show_fdinfo = drm_show_fdinfo,
889};
890
891static const struct drm_driver msm_driver = {
892 .driver_features = DRIVER_GEM |
893 DRIVER_RENDER |
894 DRIVER_ATOMIC |
895 DRIVER_MODESET |
896 DRIVER_SYNCOBJ,
897 .open = msm_open,
898 .postclose = msm_postclose,
899 .dumb_create = msm_gem_dumb_create,
900 .dumb_map_offset = msm_gem_dumb_map_offset,
901 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
902#ifdef CONFIG_DEBUG_FS
903 .debugfs_init = msm_debugfs_init,
904#endif
905 .show_fdinfo = msm_show_fdinfo,
906 .ioctls = msm_ioctls,
907 .num_ioctls = ARRAY_SIZE(msm_ioctls),
908 .fops = &fops,
909 .name = "msm",
910 .desc = "MSM Snapdragon DRM",
911 .date = "20130625",
912 .major = MSM_VERSION_MAJOR,
913 .minor = MSM_VERSION_MINOR,
914 .patchlevel = MSM_VERSION_PATCHLEVEL,
915};
916
917/*
918 * Componentized driver support:
919 */
920
921/*
922 * Identify what components need to be added by parsing what remote-endpoints
923 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
924 * is no external component that we need to add since LVDS is within MDP4
925 * itself.
926 */
927static int add_components_mdp(struct device *master_dev,
928 struct component_match **matchptr)
929{
930 struct device_node *np = master_dev->of_node;
931 struct device_node *ep_node;
932
933 for_each_endpoint_of_node(np, ep_node) {
934 struct device_node *intf;
935 struct of_endpoint ep;
936 int ret;
937
938 ret = of_graph_parse_endpoint(ep_node, &ep);
939 if (ret) {
940 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
941 of_node_put(ep_node);
942 return ret;
943 }
944
945 /*
946 * The LCDC/LVDS port on MDP4 is a speacial case where the
947 * remote-endpoint isn't a component that we need to add
948 */
949 if (of_device_is_compatible(np, "qcom,mdp4") &&
950 ep.port == 0)
951 continue;
952
953 /*
954 * It's okay if some of the ports don't have a remote endpoint
955 * specified. It just means that the port isn't connected to
956 * any external interface.
957 */
958 intf = of_graph_get_remote_port_parent(ep_node);
959 if (!intf)
960 continue;
961
962 if (of_device_is_available(intf))
963 drm_of_component_match_add(master_dev, matchptr,
964 component_compare_of, intf);
965
966 of_node_put(intf);
967 }
968
969 return 0;
970}
971
972#if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU)
973bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
974{
975 /* If just a single driver is enabled, use it no matter what */
976 return true;
977}
978#else
979
980static bool prefer_mdp5 = true;
981MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred");
982module_param(prefer_mdp5, bool, 0444);
983
984/* list all platforms supported by both mdp5 and dpu drivers */
985static const char *const msm_mdp5_dpu_migration[] = {
986 "qcom,sdm630-mdp5",
987 "qcom,sdm660-mdp5",
988 NULL,
989};
990
991bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver)
992{
993 /* If it is not an MDP5 device, do not try MDP5 driver */
994 if (!of_device_is_compatible(dev->of_node, "qcom,mdp5"))
995 return dpu_driver;
996
997 /* If it is not in the migration list, use MDP5 */
998 if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration))
999 return !dpu_driver;
1000
1001 return prefer_mdp5 ? !dpu_driver : dpu_driver;
1002}
1003#endif
1004
1005/*
1006 * We don't know what's the best binding to link the gpu with the drm device.
1007 * Fow now, we just hunt for all the possible gpus that we support, and add them
1008 * as components.
1009 */
1010static const struct of_device_id msm_gpu_match[] = {
1011 { .compatible = "qcom,adreno" },
1012 { .compatible = "qcom,adreno-3xx" },
1013 { .compatible = "amd,imageon" },
1014 { .compatible = "qcom,kgsl-3d0" },
1015 { },
1016};
1017
1018static int add_gpu_components(struct device *dev,
1019 struct component_match **matchptr)
1020{
1021 struct device_node *np;
1022
1023 np = of_find_matching_node(NULL, msm_gpu_match);
1024 if (!np)
1025 return 0;
1026
1027 if (of_device_is_available(np))
1028 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1029
1030 of_node_put(np);
1031
1032 return 0;
1033}
1034
1035static int msm_drm_bind(struct device *dev)
1036{
1037 return msm_drm_init(dev, &msm_driver);
1038}
1039
1040static void msm_drm_unbind(struct device *dev)
1041{
1042 msm_drm_uninit(dev);
1043}
1044
1045const struct component_master_ops msm_drm_ops = {
1046 .bind = msm_drm_bind,
1047 .unbind = msm_drm_unbind,
1048};
1049
1050int msm_drv_probe(struct device *master_dev,
1051 int (*kms_init)(struct drm_device *dev),
1052 struct msm_kms *kms)
1053{
1054 struct msm_drm_private *priv;
1055 struct component_match *match = NULL;
1056 int ret;
1057
1058 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1059 if (!priv)
1060 return -ENOMEM;
1061
1062 priv->kms = kms;
1063 priv->kms_init = kms_init;
1064 dev_set_drvdata(master_dev, priv);
1065
1066 /* Add mdp components if we have KMS. */
1067 if (kms_init) {
1068 ret = add_components_mdp(master_dev, &match);
1069 if (ret)
1070 return ret;
1071 }
1072
1073 ret = add_gpu_components(master_dev, &match);
1074 if (ret)
1075 return ret;
1076
1077 /* on all devices that I am aware of, iommu's which can map
1078 * any address the cpu can see are used:
1079 */
1080 ret = dma_set_mask_and_coherent(master_dev, ~0);
1081 if (ret)
1082 return ret;
1083
1084 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1085 if (ret)
1086 return ret;
1087
1088 return 0;
1089}
1090
1091/*
1092 * Platform driver:
1093 * Used only for headlesss GPU instances
1094 */
1095
1096static int msm_pdev_probe(struct platform_device *pdev)
1097{
1098 return msm_drv_probe(&pdev->dev, NULL, NULL);
1099}
1100
1101static void msm_pdev_remove(struct platform_device *pdev)
1102{
1103 component_master_del(&pdev->dev, &msm_drm_ops);
1104}
1105
1106static struct platform_driver msm_platform_driver = {
1107 .probe = msm_pdev_probe,
1108 .remove_new = msm_pdev_remove,
1109 .driver = {
1110 .name = "msm",
1111 },
1112};
1113
1114static int __init msm_drm_register(void)
1115{
1116 if (!modeset)
1117 return -EINVAL;
1118
1119 DBG("init");
1120 msm_mdp_register();
1121 msm_dpu_register();
1122 msm_dsi_register();
1123 msm_hdmi_register();
1124 msm_dp_register();
1125 adreno_register();
1126 msm_mdp4_register();
1127 msm_mdss_register();
1128 return platform_driver_register(&msm_platform_driver);
1129}
1130
1131static void __exit msm_drm_unregister(void)
1132{
1133 DBG("fini");
1134 platform_driver_unregister(&msm_platform_driver);
1135 msm_mdss_unregister();
1136 msm_mdp4_unregister();
1137 msm_dp_unregister();
1138 msm_hdmi_unregister();
1139 adreno_unregister();
1140 msm_dsi_unregister();
1141 msm_mdp_unregister();
1142 msm_dpu_unregister();
1143}
1144
1145module_init(msm_drm_register);
1146module_exit(msm_drm_unregister);
1147
1148MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1149MODULE_DESCRIPTION("MSM DRM Driver");
1150MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8#include <linux/dma-mapping.h>
9#include <linux/fault-inject.h>
10#include <linux/kthread.h>
11#include <linux/sched/mm.h>
12#include <linux/uaccess.h>
13#include <uapi/linux/sched/types.h>
14
15#include <drm/drm_bridge.h>
16#include <drm/drm_drv.h>
17#include <drm/drm_file.h>
18#include <drm/drm_ioctl.h>
19#include <drm/drm_prime.h>
20#include <drm/drm_of.h>
21#include <drm/drm_vblank.h>
22
23#include "disp/msm_disp_snapshot.h"
24#include "msm_drv.h"
25#include "msm_debugfs.h"
26#include "msm_fence.h"
27#include "msm_gem.h"
28#include "msm_gpu.h"
29#include "msm_kms.h"
30#include "msm_mmu.h"
31#include "adreno/adreno_gpu.h"
32
33/*
34 * MSM driver version:
35 * - 1.0.0 - initial interface
36 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
37 * - 1.2.0 - adds explicit fence support for submit ioctl
38 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
39 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
40 * MSM_GEM_INFO ioctl.
41 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
42 * GEM object's debug name
43 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
44 * - 1.6.0 - Syncobj support
45 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
46 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
47 * - 1.9.0 - Add MSM_SUBMIT_FENCE_SN_IN
48 */
49#define MSM_VERSION_MAJOR 1
50#define MSM_VERSION_MINOR 9
51#define MSM_VERSION_PATCHLEVEL 0
52
53static const struct drm_mode_config_funcs mode_config_funcs = {
54 .fb_create = msm_framebuffer_create,
55 .output_poll_changed = drm_fb_helper_output_poll_changed,
56 .atomic_check = drm_atomic_helper_check,
57 .atomic_commit = drm_atomic_helper_commit,
58};
59
60static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
61 .atomic_commit_tail = msm_atomic_commit_tail,
62};
63
64#ifdef CONFIG_DRM_FBDEV_EMULATION
65static bool fbdev = true;
66MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
67module_param(fbdev, bool, 0600);
68#endif
69
70static char *vram = "16m";
71MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
72module_param(vram, charp, 0);
73
74bool dumpstate;
75MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
76module_param(dumpstate, bool, 0600);
77
78static bool modeset = true;
79MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
80module_param(modeset, bool, 0600);
81
82#ifdef CONFIG_FAULT_INJECTION
83DECLARE_FAULT_ATTR(fail_gem_alloc);
84DECLARE_FAULT_ATTR(fail_gem_iova);
85#endif
86
87static irqreturn_t msm_irq(int irq, void *arg)
88{
89 struct drm_device *dev = arg;
90 struct msm_drm_private *priv = dev->dev_private;
91 struct msm_kms *kms = priv->kms;
92
93 BUG_ON(!kms);
94
95 return kms->funcs->irq(kms);
96}
97
98static void msm_irq_preinstall(struct drm_device *dev)
99{
100 struct msm_drm_private *priv = dev->dev_private;
101 struct msm_kms *kms = priv->kms;
102
103 BUG_ON(!kms);
104
105 kms->funcs->irq_preinstall(kms);
106}
107
108static int msm_irq_postinstall(struct drm_device *dev)
109{
110 struct msm_drm_private *priv = dev->dev_private;
111 struct msm_kms *kms = priv->kms;
112
113 BUG_ON(!kms);
114
115 if (kms->funcs->irq_postinstall)
116 return kms->funcs->irq_postinstall(kms);
117
118 return 0;
119}
120
121static int msm_irq_install(struct drm_device *dev, unsigned int irq)
122{
123 struct msm_drm_private *priv = dev->dev_private;
124 struct msm_kms *kms = priv->kms;
125 int ret;
126
127 if (irq == IRQ_NOTCONNECTED)
128 return -ENOTCONN;
129
130 msm_irq_preinstall(dev);
131
132 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
133 if (ret)
134 return ret;
135
136 kms->irq_requested = true;
137
138 ret = msm_irq_postinstall(dev);
139 if (ret) {
140 free_irq(irq, dev);
141 return ret;
142 }
143
144 return 0;
145}
146
147static void msm_irq_uninstall(struct drm_device *dev)
148{
149 struct msm_drm_private *priv = dev->dev_private;
150 struct msm_kms *kms = priv->kms;
151
152 kms->funcs->irq_uninstall(kms);
153 if (kms->irq_requested)
154 free_irq(kms->irq, dev);
155}
156
157struct msm_vblank_work {
158 struct work_struct work;
159 int crtc_id;
160 bool enable;
161 struct msm_drm_private *priv;
162};
163
164static void vblank_ctrl_worker(struct work_struct *work)
165{
166 struct msm_vblank_work *vbl_work = container_of(work,
167 struct msm_vblank_work, work);
168 struct msm_drm_private *priv = vbl_work->priv;
169 struct msm_kms *kms = priv->kms;
170
171 if (vbl_work->enable)
172 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
173 else
174 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
175
176 kfree(vbl_work);
177}
178
179static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
180 int crtc_id, bool enable)
181{
182 struct msm_vblank_work *vbl_work;
183
184 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
185 if (!vbl_work)
186 return -ENOMEM;
187
188 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
189
190 vbl_work->crtc_id = crtc_id;
191 vbl_work->enable = enable;
192 vbl_work->priv = priv;
193
194 queue_work(priv->wq, &vbl_work->work);
195
196 return 0;
197}
198
199static int msm_drm_uninit(struct device *dev)
200{
201 struct platform_device *pdev = to_platform_device(dev);
202 struct msm_drm_private *priv = platform_get_drvdata(pdev);
203 struct drm_device *ddev = priv->dev;
204 struct msm_kms *kms = priv->kms;
205 int i;
206
207 /*
208 * Shutdown the hw if we're far enough along where things might be on.
209 * If we run this too early, we'll end up panicking in any variety of
210 * places. Since we don't register the drm device until late in
211 * msm_drm_init, drm_dev->registered is used as an indicator that the
212 * shutdown will be successful.
213 */
214 if (ddev->registered) {
215 drm_dev_unregister(ddev);
216 drm_atomic_helper_shutdown(ddev);
217 }
218
219 /* We must cancel and cleanup any pending vblank enable/disable
220 * work before msm_irq_uninstall() to avoid work re-enabling an
221 * irq after uninstall has disabled it.
222 */
223
224 flush_workqueue(priv->wq);
225
226 /* clean up event worker threads */
227 for (i = 0; i < priv->num_crtcs; i++) {
228 if (priv->event_thread[i].worker)
229 kthread_destroy_worker(priv->event_thread[i].worker);
230 }
231
232 msm_gem_shrinker_cleanup(ddev);
233
234 drm_kms_helper_poll_fini(ddev);
235
236 msm_perf_debugfs_cleanup(priv);
237 msm_rd_debugfs_cleanup(priv);
238
239#ifdef CONFIG_DRM_FBDEV_EMULATION
240 if (fbdev && priv->fbdev)
241 msm_fbdev_free(ddev);
242#endif
243
244 msm_disp_snapshot_destroy(ddev);
245
246 drm_mode_config_cleanup(ddev);
247
248 for (i = 0; i < priv->num_bridges; i++)
249 drm_bridge_remove(priv->bridges[i]);
250 priv->num_bridges = 0;
251
252 pm_runtime_get_sync(dev);
253 msm_irq_uninstall(ddev);
254 pm_runtime_put_sync(dev);
255
256 if (kms && kms->funcs)
257 kms->funcs->destroy(kms);
258
259 if (priv->vram.paddr) {
260 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
261 drm_mm_takedown(&priv->vram.mm);
262 dma_free_attrs(dev, priv->vram.size, NULL,
263 priv->vram.paddr, attrs);
264 }
265
266 component_unbind_all(dev, ddev);
267
268 ddev->dev_private = NULL;
269 drm_dev_put(ddev);
270
271 destroy_workqueue(priv->wq);
272
273 return 0;
274}
275
276#include <linux/of_address.h>
277
278struct msm_gem_address_space *msm_kms_init_aspace(struct drm_device *dev)
279{
280 struct msm_gem_address_space *aspace;
281 struct msm_mmu *mmu;
282 struct device *mdp_dev = dev->dev;
283 struct device *mdss_dev = mdp_dev->parent;
284 struct device *iommu_dev;
285
286 /*
287 * IOMMUs can be a part of MDSS device tree binding, or the
288 * MDP/DPU device.
289 */
290 if (device_iommu_mapped(mdp_dev))
291 iommu_dev = mdp_dev;
292 else
293 iommu_dev = mdss_dev;
294
295 mmu = msm_iommu_new(iommu_dev, 0);
296 if (IS_ERR(mmu))
297 return ERR_CAST(mmu);
298
299 if (!mmu) {
300 drm_info(dev, "no IOMMU, fallback to phys contig buffers for scanout\n");
301 return NULL;
302 }
303
304 aspace = msm_gem_address_space_create(mmu, "mdp_kms",
305 0x1000, 0x100000000 - 0x1000);
306 if (IS_ERR(aspace)) {
307 dev_err(mdp_dev, "aspace create, error %pe\n", aspace);
308 mmu->funcs->destroy(mmu);
309 }
310
311 return aspace;
312}
313
314bool msm_use_mmu(struct drm_device *dev)
315{
316 struct msm_drm_private *priv = dev->dev_private;
317
318 /*
319 * a2xx comes with its own MMU
320 * On other platforms IOMMU can be declared specified either for the
321 * MDP/DPU device or for its parent, MDSS device.
322 */
323 return priv->is_a2xx ||
324 device_iommu_mapped(dev->dev) ||
325 device_iommu_mapped(dev->dev->parent);
326}
327
328static int msm_init_vram(struct drm_device *dev)
329{
330 struct msm_drm_private *priv = dev->dev_private;
331 struct device_node *node;
332 unsigned long size = 0;
333 int ret = 0;
334
335 /* In the device-tree world, we could have a 'memory-region'
336 * phandle, which gives us a link to our "vram". Allocating
337 * is all nicely abstracted behind the dma api, but we need
338 * to know the entire size to allocate it all in one go. There
339 * are two cases:
340 * 1) device with no IOMMU, in which case we need exclusive
341 * access to a VRAM carveout big enough for all gpu
342 * buffers
343 * 2) device with IOMMU, but where the bootloader puts up
344 * a splash screen. In this case, the VRAM carveout
345 * need only be large enough for fbdev fb. But we need
346 * exclusive access to the buffer to avoid the kernel
347 * using those pages for other purposes (which appears
348 * as corruption on screen before we have a chance to
349 * load and do initial modeset)
350 */
351
352 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
353 if (node) {
354 struct resource r;
355 ret = of_address_to_resource(node, 0, &r);
356 of_node_put(node);
357 if (ret)
358 return ret;
359 size = r.end - r.start + 1;
360 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
361
362 /* if we have no IOMMU, then we need to use carveout allocator.
363 * Grab the entire DMA chunk carved out in early startup in
364 * mach-msm:
365 */
366 } else if (!msm_use_mmu(dev)) {
367 DRM_INFO("using %s VRAM carveout\n", vram);
368 size = memparse(vram, NULL);
369 }
370
371 if (size) {
372 unsigned long attrs = 0;
373 void *p;
374
375 priv->vram.size = size;
376
377 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
378 spin_lock_init(&priv->vram.lock);
379
380 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
381 attrs |= DMA_ATTR_WRITE_COMBINE;
382
383 /* note that for no-kernel-mapping, the vaddr returned
384 * is bogus, but non-null if allocation succeeded:
385 */
386 p = dma_alloc_attrs(dev->dev, size,
387 &priv->vram.paddr, GFP_KERNEL, attrs);
388 if (!p) {
389 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
390 priv->vram.paddr = 0;
391 return -ENOMEM;
392 }
393
394 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
395 (uint32_t)priv->vram.paddr,
396 (uint32_t)(priv->vram.paddr + size));
397 }
398
399 return ret;
400}
401
402static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
403{
404 struct msm_drm_private *priv = dev_get_drvdata(dev);
405 struct drm_device *ddev;
406 struct msm_kms *kms;
407 int ret, i;
408
409 if (drm_firmware_drivers_only())
410 return -ENODEV;
411
412 ddev = drm_dev_alloc(drv, dev);
413 if (IS_ERR(ddev)) {
414 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
415 return PTR_ERR(ddev);
416 }
417 ddev->dev_private = priv;
418 priv->dev = ddev;
419
420 priv->wq = alloc_ordered_workqueue("msm", 0);
421
422 INIT_LIST_HEAD(&priv->objects);
423 mutex_init(&priv->obj_lock);
424
425 /*
426 * Initialize the LRUs:
427 */
428 mutex_init(&priv->lru.lock);
429 drm_gem_lru_init(&priv->lru.unbacked, &priv->lru.lock);
430 drm_gem_lru_init(&priv->lru.pinned, &priv->lru.lock);
431 drm_gem_lru_init(&priv->lru.willneed, &priv->lru.lock);
432 drm_gem_lru_init(&priv->lru.dontneed, &priv->lru.lock);
433
434 /* Teach lockdep about lock ordering wrt. shrinker: */
435 fs_reclaim_acquire(GFP_KERNEL);
436 might_lock(&priv->lru.lock);
437 fs_reclaim_release(GFP_KERNEL);
438
439 drm_mode_config_init(ddev);
440
441 ret = msm_init_vram(ddev);
442 if (ret)
443 return ret;
444
445 /* Bind all our sub-components: */
446 ret = component_bind_all(dev, ddev);
447 if (ret)
448 return ret;
449
450 dma_set_max_seg_size(dev, UINT_MAX);
451
452 msm_gem_shrinker_init(ddev);
453
454 if (priv->kms_init) {
455 ret = priv->kms_init(ddev);
456 if (ret) {
457 DRM_DEV_ERROR(dev, "failed to load kms\n");
458 priv->kms = NULL;
459 goto err_msm_uninit;
460 }
461 kms = priv->kms;
462 } else {
463 /* valid only for the dummy headless case, where of_node=NULL */
464 WARN_ON(dev->of_node);
465 kms = NULL;
466 }
467
468 /* Enable normalization of plane zpos */
469 ddev->mode_config.normalize_zpos = true;
470
471 if (kms) {
472 kms->dev = ddev;
473 ret = kms->funcs->hw_init(kms);
474 if (ret) {
475 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
476 goto err_msm_uninit;
477 }
478 }
479
480 drm_helper_move_panel_connectors_to_head(ddev);
481
482 ddev->mode_config.funcs = &mode_config_funcs;
483 ddev->mode_config.helper_private = &mode_config_helper_funcs;
484
485 for (i = 0; i < priv->num_crtcs; i++) {
486 /* initialize event thread */
487 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
488 priv->event_thread[i].dev = ddev;
489 priv->event_thread[i].worker = kthread_create_worker(0,
490 "crtc_event:%d", priv->event_thread[i].crtc_id);
491 if (IS_ERR(priv->event_thread[i].worker)) {
492 ret = PTR_ERR(priv->event_thread[i].worker);
493 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
494 ret = PTR_ERR(priv->event_thread[i].worker);
495 goto err_msm_uninit;
496 }
497
498 sched_set_fifo(priv->event_thread[i].worker->task);
499 }
500
501 ret = drm_vblank_init(ddev, priv->num_crtcs);
502 if (ret < 0) {
503 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
504 goto err_msm_uninit;
505 }
506
507 if (kms) {
508 pm_runtime_get_sync(dev);
509 ret = msm_irq_install(ddev, kms->irq);
510 pm_runtime_put_sync(dev);
511 if (ret < 0) {
512 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
513 goto err_msm_uninit;
514 }
515 }
516
517 ret = drm_dev_register(ddev, 0);
518 if (ret)
519 goto err_msm_uninit;
520
521 if (kms) {
522 ret = msm_disp_snapshot_init(ddev);
523 if (ret)
524 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
525 }
526 drm_mode_config_reset(ddev);
527
528#ifdef CONFIG_DRM_FBDEV_EMULATION
529 if (kms && fbdev)
530 priv->fbdev = msm_fbdev_init(ddev);
531#endif
532
533 ret = msm_debugfs_late_init(ddev);
534 if (ret)
535 goto err_msm_uninit;
536
537 drm_kms_helper_poll_init(ddev);
538
539 return 0;
540
541err_msm_uninit:
542 msm_drm_uninit(dev);
543 return ret;
544}
545
546/*
547 * DRM operations:
548 */
549
550static void load_gpu(struct drm_device *dev)
551{
552 static DEFINE_MUTEX(init_lock);
553 struct msm_drm_private *priv = dev->dev_private;
554
555 mutex_lock(&init_lock);
556
557 if (!priv->gpu)
558 priv->gpu = adreno_load_gpu(dev);
559
560 mutex_unlock(&init_lock);
561}
562
563static int context_init(struct drm_device *dev, struct drm_file *file)
564{
565 static atomic_t ident = ATOMIC_INIT(0);
566 struct msm_drm_private *priv = dev->dev_private;
567 struct msm_file_private *ctx;
568
569 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
570 if (!ctx)
571 return -ENOMEM;
572
573 INIT_LIST_HEAD(&ctx->submitqueues);
574 rwlock_init(&ctx->queuelock);
575
576 kref_init(&ctx->ref);
577 msm_submitqueue_init(dev, ctx);
578
579 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
580 file->driver_priv = ctx;
581
582 ctx->seqno = atomic_inc_return(&ident);
583
584 return 0;
585}
586
587static int msm_open(struct drm_device *dev, struct drm_file *file)
588{
589 /* For now, load gpu on open.. to avoid the requirement of having
590 * firmware in the initrd.
591 */
592 load_gpu(dev);
593
594 return context_init(dev, file);
595}
596
597static void context_close(struct msm_file_private *ctx)
598{
599 msm_submitqueue_close(ctx);
600 msm_file_private_put(ctx);
601}
602
603static void msm_postclose(struct drm_device *dev, struct drm_file *file)
604{
605 struct msm_drm_private *priv = dev->dev_private;
606 struct msm_file_private *ctx = file->driver_priv;
607
608 /*
609 * It is not possible to set sysprof param to non-zero if gpu
610 * is not initialized:
611 */
612 if (priv->gpu)
613 msm_file_private_set_sysprof(ctx, priv->gpu, 0);
614
615 context_close(ctx);
616}
617
618int msm_crtc_enable_vblank(struct drm_crtc *crtc)
619{
620 struct drm_device *dev = crtc->dev;
621 unsigned int pipe = crtc->index;
622 struct msm_drm_private *priv = dev->dev_private;
623 struct msm_kms *kms = priv->kms;
624 if (!kms)
625 return -ENXIO;
626 drm_dbg_vbl(dev, "crtc=%u", pipe);
627 return vblank_ctrl_queue_work(priv, pipe, true);
628}
629
630void msm_crtc_disable_vblank(struct drm_crtc *crtc)
631{
632 struct drm_device *dev = crtc->dev;
633 unsigned int pipe = crtc->index;
634 struct msm_drm_private *priv = dev->dev_private;
635 struct msm_kms *kms = priv->kms;
636 if (!kms)
637 return;
638 drm_dbg_vbl(dev, "crtc=%u", pipe);
639 vblank_ctrl_queue_work(priv, pipe, false);
640}
641
642/*
643 * DRM ioctls:
644 */
645
646static int msm_ioctl_get_param(struct drm_device *dev, void *data,
647 struct drm_file *file)
648{
649 struct msm_drm_private *priv = dev->dev_private;
650 struct drm_msm_param *args = data;
651 struct msm_gpu *gpu;
652
653 /* for now, we just have 3d pipe.. eventually this would need to
654 * be more clever to dispatch to appropriate gpu module:
655 */
656 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
657 return -EINVAL;
658
659 gpu = priv->gpu;
660
661 if (!gpu)
662 return -ENXIO;
663
664 return gpu->funcs->get_param(gpu, file->driver_priv,
665 args->param, &args->value, &args->len);
666}
667
668static int msm_ioctl_set_param(struct drm_device *dev, void *data,
669 struct drm_file *file)
670{
671 struct msm_drm_private *priv = dev->dev_private;
672 struct drm_msm_param *args = data;
673 struct msm_gpu *gpu;
674
675 if ((args->pipe != MSM_PIPE_3D0) || (args->pad != 0))
676 return -EINVAL;
677
678 gpu = priv->gpu;
679
680 if (!gpu)
681 return -ENXIO;
682
683 return gpu->funcs->set_param(gpu, file->driver_priv,
684 args->param, args->value, args->len);
685}
686
687static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
688 struct drm_file *file)
689{
690 struct drm_msm_gem_new *args = data;
691 uint32_t flags = args->flags;
692
693 if (args->flags & ~MSM_BO_FLAGS) {
694 DRM_ERROR("invalid flags: %08x\n", args->flags);
695 return -EINVAL;
696 }
697
698 /*
699 * Uncached CPU mappings are deprecated, as of:
700 *
701 * 9ef364432db4 ("drm/msm: deprecate MSM_BO_UNCACHED (map as writecombine instead)")
702 *
703 * So promote them to WC.
704 */
705 if (flags & MSM_BO_UNCACHED) {
706 flags &= ~MSM_BO_CACHED;
707 flags |= MSM_BO_WC;
708 }
709
710 if (should_fail(&fail_gem_alloc, args->size))
711 return -ENOMEM;
712
713 return msm_gem_new_handle(dev, file, args->size,
714 args->flags, &args->handle, NULL);
715}
716
717static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
718{
719 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
720}
721
722static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
723 struct drm_file *file)
724{
725 struct drm_msm_gem_cpu_prep *args = data;
726 struct drm_gem_object *obj;
727 ktime_t timeout = to_ktime(args->timeout);
728 int ret;
729
730 if (args->op & ~MSM_PREP_FLAGS) {
731 DRM_ERROR("invalid op: %08x\n", args->op);
732 return -EINVAL;
733 }
734
735 obj = drm_gem_object_lookup(file, args->handle);
736 if (!obj)
737 return -ENOENT;
738
739 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
740
741 drm_gem_object_put(obj);
742
743 return ret;
744}
745
746static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
747 struct drm_file *file)
748{
749 struct drm_msm_gem_cpu_fini *args = data;
750 struct drm_gem_object *obj;
751 int ret;
752
753 obj = drm_gem_object_lookup(file, args->handle);
754 if (!obj)
755 return -ENOENT;
756
757 ret = msm_gem_cpu_fini(obj);
758
759 drm_gem_object_put(obj);
760
761 return ret;
762}
763
764static int msm_ioctl_gem_info_iova(struct drm_device *dev,
765 struct drm_file *file, struct drm_gem_object *obj,
766 uint64_t *iova)
767{
768 struct msm_drm_private *priv = dev->dev_private;
769 struct msm_file_private *ctx = file->driver_priv;
770
771 if (!priv->gpu)
772 return -EINVAL;
773
774 if (should_fail(&fail_gem_iova, obj->size))
775 return -ENOMEM;
776
777 /*
778 * Don't pin the memory here - just get an address so that userspace can
779 * be productive
780 */
781 return msm_gem_get_iova(obj, ctx->aspace, iova);
782}
783
784static int msm_ioctl_gem_info_set_iova(struct drm_device *dev,
785 struct drm_file *file, struct drm_gem_object *obj,
786 uint64_t iova)
787{
788 struct msm_drm_private *priv = dev->dev_private;
789 struct msm_file_private *ctx = file->driver_priv;
790
791 if (!priv->gpu)
792 return -EINVAL;
793
794 /* Only supported if per-process address space is supported: */
795 if (priv->gpu->aspace == ctx->aspace)
796 return -EOPNOTSUPP;
797
798 if (should_fail(&fail_gem_iova, obj->size))
799 return -ENOMEM;
800
801 return msm_gem_set_iova(obj, ctx->aspace, iova);
802}
803
804static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
805 struct drm_file *file)
806{
807 struct drm_msm_gem_info *args = data;
808 struct drm_gem_object *obj;
809 struct msm_gem_object *msm_obj;
810 int i, ret = 0;
811
812 if (args->pad)
813 return -EINVAL;
814
815 switch (args->info) {
816 case MSM_INFO_GET_OFFSET:
817 case MSM_INFO_GET_IOVA:
818 case MSM_INFO_SET_IOVA:
819 case MSM_INFO_GET_FLAGS:
820 /* value returned as immediate, not pointer, so len==0: */
821 if (args->len)
822 return -EINVAL;
823 break;
824 case MSM_INFO_SET_NAME:
825 case MSM_INFO_GET_NAME:
826 break;
827 default:
828 return -EINVAL;
829 }
830
831 obj = drm_gem_object_lookup(file, args->handle);
832 if (!obj)
833 return -ENOENT;
834
835 msm_obj = to_msm_bo(obj);
836
837 switch (args->info) {
838 case MSM_INFO_GET_OFFSET:
839 args->value = msm_gem_mmap_offset(obj);
840 break;
841 case MSM_INFO_GET_IOVA:
842 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
843 break;
844 case MSM_INFO_SET_IOVA:
845 ret = msm_ioctl_gem_info_set_iova(dev, file, obj, args->value);
846 break;
847 case MSM_INFO_GET_FLAGS:
848 if (obj->import_attach) {
849 ret = -EINVAL;
850 break;
851 }
852 /* Hide internal kernel-only flags: */
853 args->value = to_msm_bo(obj)->flags & MSM_BO_FLAGS;
854 ret = 0;
855 break;
856 case MSM_INFO_SET_NAME:
857 /* length check should leave room for terminating null: */
858 if (args->len >= sizeof(msm_obj->name)) {
859 ret = -EINVAL;
860 break;
861 }
862 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
863 args->len)) {
864 msm_obj->name[0] = '\0';
865 ret = -EFAULT;
866 break;
867 }
868 msm_obj->name[args->len] = '\0';
869 for (i = 0; i < args->len; i++) {
870 if (!isprint(msm_obj->name[i])) {
871 msm_obj->name[i] = '\0';
872 break;
873 }
874 }
875 break;
876 case MSM_INFO_GET_NAME:
877 if (args->value && (args->len < strlen(msm_obj->name))) {
878 ret = -EINVAL;
879 break;
880 }
881 args->len = strlen(msm_obj->name);
882 if (args->value) {
883 if (copy_to_user(u64_to_user_ptr(args->value),
884 msm_obj->name, args->len))
885 ret = -EFAULT;
886 }
887 break;
888 }
889
890 drm_gem_object_put(obj);
891
892 return ret;
893}
894
895static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
896 ktime_t timeout)
897{
898 struct dma_fence *fence;
899 int ret;
900
901 if (fence_after(fence_id, queue->last_fence)) {
902 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
903 fence_id, queue->last_fence);
904 return -EINVAL;
905 }
906
907 /*
908 * Map submitqueue scoped "seqno" (which is actually an idr key)
909 * back to underlying dma-fence
910 *
911 * The fence is removed from the fence_idr when the submit is
912 * retired, so if the fence is not found it means there is nothing
913 * to wait for
914 */
915 ret = mutex_lock_interruptible(&queue->idr_lock);
916 if (ret)
917 return ret;
918 fence = idr_find(&queue->fence_idr, fence_id);
919 if (fence)
920 fence = dma_fence_get_rcu(fence);
921 mutex_unlock(&queue->idr_lock);
922
923 if (!fence)
924 return 0;
925
926 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
927 if (ret == 0) {
928 ret = -ETIMEDOUT;
929 } else if (ret != -ERESTARTSYS) {
930 ret = 0;
931 }
932
933 dma_fence_put(fence);
934
935 return ret;
936}
937
938static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
939 struct drm_file *file)
940{
941 struct msm_drm_private *priv = dev->dev_private;
942 struct drm_msm_wait_fence *args = data;
943 struct msm_gpu_submitqueue *queue;
944 int ret;
945
946 if (args->pad) {
947 DRM_ERROR("invalid pad: %08x\n", args->pad);
948 return -EINVAL;
949 }
950
951 if (!priv->gpu)
952 return 0;
953
954 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
955 if (!queue)
956 return -ENOENT;
957
958 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
959
960 msm_submitqueue_put(queue);
961
962 return ret;
963}
964
965static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
966 struct drm_file *file)
967{
968 struct drm_msm_gem_madvise *args = data;
969 struct drm_gem_object *obj;
970 int ret;
971
972 switch (args->madv) {
973 case MSM_MADV_DONTNEED:
974 case MSM_MADV_WILLNEED:
975 break;
976 default:
977 return -EINVAL;
978 }
979
980 obj = drm_gem_object_lookup(file, args->handle);
981 if (!obj) {
982 return -ENOENT;
983 }
984
985 ret = msm_gem_madvise(obj, args->madv);
986 if (ret >= 0) {
987 args->retained = ret;
988 ret = 0;
989 }
990
991 drm_gem_object_put(obj);
992
993 return ret;
994}
995
996
997static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
998 struct drm_file *file)
999{
1000 struct drm_msm_submitqueue *args = data;
1001
1002 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1003 return -EINVAL;
1004
1005 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1006 args->flags, &args->id);
1007}
1008
1009static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1010 struct drm_file *file)
1011{
1012 return msm_submitqueue_query(dev, file->driver_priv, data);
1013}
1014
1015static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1016 struct drm_file *file)
1017{
1018 u32 id = *(u32 *) data;
1019
1020 return msm_submitqueue_remove(file->driver_priv, id);
1021}
1022
1023static const struct drm_ioctl_desc msm_ioctls[] = {
1024 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1025 DRM_IOCTL_DEF_DRV(MSM_SET_PARAM, msm_ioctl_set_param, DRM_RENDER_ALLOW),
1026 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1027 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1028 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1029 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1030 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1031 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1032 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1033 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1034 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1035 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1036};
1037
1038static void msm_fop_show_fdinfo(struct seq_file *m, struct file *f)
1039{
1040 struct drm_file *file = f->private_data;
1041 struct drm_device *dev = file->minor->dev;
1042 struct msm_drm_private *priv = dev->dev_private;
1043 struct drm_printer p = drm_seq_file_printer(m);
1044
1045 if (!priv->gpu)
1046 return;
1047
1048 msm_gpu_show_fdinfo(priv->gpu, file->driver_priv, &p);
1049}
1050
1051static const struct file_operations fops = {
1052 .owner = THIS_MODULE,
1053 DRM_GEM_FOPS,
1054 .show_fdinfo = msm_fop_show_fdinfo,
1055};
1056
1057static const struct drm_driver msm_driver = {
1058 .driver_features = DRIVER_GEM |
1059 DRIVER_RENDER |
1060 DRIVER_ATOMIC |
1061 DRIVER_MODESET |
1062 DRIVER_SYNCOBJ,
1063 .open = msm_open,
1064 .postclose = msm_postclose,
1065 .lastclose = drm_fb_helper_lastclose,
1066 .dumb_create = msm_gem_dumb_create,
1067 .dumb_map_offset = msm_gem_dumb_map_offset,
1068 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1069 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1070 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1071 .gem_prime_mmap = msm_gem_prime_mmap,
1072#ifdef CONFIG_DEBUG_FS
1073 .debugfs_init = msm_debugfs_init,
1074#endif
1075 .ioctls = msm_ioctls,
1076 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1077 .fops = &fops,
1078 .name = "msm",
1079 .desc = "MSM Snapdragon DRM",
1080 .date = "20130625",
1081 .major = MSM_VERSION_MAJOR,
1082 .minor = MSM_VERSION_MINOR,
1083 .patchlevel = MSM_VERSION_PATCHLEVEL,
1084};
1085
1086int msm_pm_prepare(struct device *dev)
1087{
1088 struct msm_drm_private *priv = dev_get_drvdata(dev);
1089 struct drm_device *ddev = priv ? priv->dev : NULL;
1090
1091 if (!priv || !priv->kms)
1092 return 0;
1093
1094 return drm_mode_config_helper_suspend(ddev);
1095}
1096
1097void msm_pm_complete(struct device *dev)
1098{
1099 struct msm_drm_private *priv = dev_get_drvdata(dev);
1100 struct drm_device *ddev = priv ? priv->dev : NULL;
1101
1102 if (!priv || !priv->kms)
1103 return;
1104
1105 drm_mode_config_helper_resume(ddev);
1106}
1107
1108static const struct dev_pm_ops msm_pm_ops = {
1109 .prepare = msm_pm_prepare,
1110 .complete = msm_pm_complete,
1111};
1112
1113/*
1114 * Componentized driver support:
1115 */
1116
1117/*
1118 * Identify what components need to be added by parsing what remote-endpoints
1119 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1120 * is no external component that we need to add since LVDS is within MDP4
1121 * itself.
1122 */
1123static int add_components_mdp(struct device *master_dev,
1124 struct component_match **matchptr)
1125{
1126 struct device_node *np = master_dev->of_node;
1127 struct device_node *ep_node;
1128
1129 for_each_endpoint_of_node(np, ep_node) {
1130 struct device_node *intf;
1131 struct of_endpoint ep;
1132 int ret;
1133
1134 ret = of_graph_parse_endpoint(ep_node, &ep);
1135 if (ret) {
1136 DRM_DEV_ERROR(master_dev, "unable to parse port endpoint\n");
1137 of_node_put(ep_node);
1138 return ret;
1139 }
1140
1141 /*
1142 * The LCDC/LVDS port on MDP4 is a speacial case where the
1143 * remote-endpoint isn't a component that we need to add
1144 */
1145 if (of_device_is_compatible(np, "qcom,mdp4") &&
1146 ep.port == 0)
1147 continue;
1148
1149 /*
1150 * It's okay if some of the ports don't have a remote endpoint
1151 * specified. It just means that the port isn't connected to
1152 * any external interface.
1153 */
1154 intf = of_graph_get_remote_port_parent(ep_node);
1155 if (!intf)
1156 continue;
1157
1158 if (of_device_is_available(intf))
1159 drm_of_component_match_add(master_dev, matchptr,
1160 component_compare_of, intf);
1161
1162 of_node_put(intf);
1163 }
1164
1165 return 0;
1166}
1167
1168/*
1169 * We don't know what's the best binding to link the gpu with the drm device.
1170 * Fow now, we just hunt for all the possible gpus that we support, and add them
1171 * as components.
1172 */
1173static const struct of_device_id msm_gpu_match[] = {
1174 { .compatible = "qcom,adreno" },
1175 { .compatible = "qcom,adreno-3xx" },
1176 { .compatible = "amd,imageon" },
1177 { .compatible = "qcom,kgsl-3d0" },
1178 { },
1179};
1180
1181static int add_gpu_components(struct device *dev,
1182 struct component_match **matchptr)
1183{
1184 struct device_node *np;
1185
1186 np = of_find_matching_node(NULL, msm_gpu_match);
1187 if (!np)
1188 return 0;
1189
1190 if (of_device_is_available(np))
1191 drm_of_component_match_add(dev, matchptr, component_compare_of, np);
1192
1193 of_node_put(np);
1194
1195 return 0;
1196}
1197
1198static int msm_drm_bind(struct device *dev)
1199{
1200 return msm_drm_init(dev, &msm_driver);
1201}
1202
1203static void msm_drm_unbind(struct device *dev)
1204{
1205 msm_drm_uninit(dev);
1206}
1207
1208const struct component_master_ops msm_drm_ops = {
1209 .bind = msm_drm_bind,
1210 .unbind = msm_drm_unbind,
1211};
1212
1213int msm_drv_probe(struct device *master_dev,
1214 int (*kms_init)(struct drm_device *dev))
1215{
1216 struct msm_drm_private *priv;
1217 struct component_match *match = NULL;
1218 int ret;
1219
1220 priv = devm_kzalloc(master_dev, sizeof(*priv), GFP_KERNEL);
1221 if (!priv)
1222 return -ENOMEM;
1223
1224 priv->kms_init = kms_init;
1225 dev_set_drvdata(master_dev, priv);
1226
1227 /* Add mdp components if we have KMS. */
1228 if (kms_init) {
1229 ret = add_components_mdp(master_dev, &match);
1230 if (ret)
1231 return ret;
1232 }
1233
1234 ret = add_gpu_components(master_dev, &match);
1235 if (ret)
1236 return ret;
1237
1238 /* on all devices that I am aware of, iommu's which can map
1239 * any address the cpu can see are used:
1240 */
1241 ret = dma_set_mask_and_coherent(master_dev, ~0);
1242 if (ret)
1243 return ret;
1244
1245 ret = component_master_add_with_match(master_dev, &msm_drm_ops, match);
1246 if (ret)
1247 return ret;
1248
1249 return 0;
1250}
1251
1252/*
1253 * Platform driver:
1254 * Used only for headlesss GPU instances
1255 */
1256
1257static int msm_pdev_probe(struct platform_device *pdev)
1258{
1259 return msm_drv_probe(&pdev->dev, NULL);
1260}
1261
1262static int msm_pdev_remove(struct platform_device *pdev)
1263{
1264 component_master_del(&pdev->dev, &msm_drm_ops);
1265
1266 return 0;
1267}
1268
1269void msm_drv_shutdown(struct platform_device *pdev)
1270{
1271 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1272 struct drm_device *drm = priv ? priv->dev : NULL;
1273
1274 /*
1275 * Shutdown the hw if we're far enough along where things might be on.
1276 * If we run this too early, we'll end up panicking in any variety of
1277 * places. Since we don't register the drm device until late in
1278 * msm_drm_init, drm_dev->registered is used as an indicator that the
1279 * shutdown will be successful.
1280 */
1281 if (drm && drm->registered && priv->kms)
1282 drm_atomic_helper_shutdown(drm);
1283}
1284
1285static struct platform_driver msm_platform_driver = {
1286 .probe = msm_pdev_probe,
1287 .remove = msm_pdev_remove,
1288 .shutdown = msm_drv_shutdown,
1289 .driver = {
1290 .name = "msm",
1291 .pm = &msm_pm_ops,
1292 },
1293};
1294
1295static int __init msm_drm_register(void)
1296{
1297 if (!modeset)
1298 return -EINVAL;
1299
1300 DBG("init");
1301 msm_mdp_register();
1302 msm_dpu_register();
1303 msm_dsi_register();
1304 msm_hdmi_register();
1305 msm_dp_register();
1306 adreno_register();
1307 msm_mdp4_register();
1308 msm_mdss_register();
1309 return platform_driver_register(&msm_platform_driver);
1310}
1311
1312static void __exit msm_drm_unregister(void)
1313{
1314 DBG("fini");
1315 platform_driver_unregister(&msm_platform_driver);
1316 msm_mdss_unregister();
1317 msm_mdp4_unregister();
1318 msm_dp_unregister();
1319 msm_hdmi_unregister();
1320 adreno_unregister();
1321 msm_dsi_unregister();
1322 msm_mdp_unregister();
1323 msm_dpu_unregister();
1324}
1325
1326module_init(msm_drm_register);
1327module_exit(msm_drm_unregister);
1328
1329MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1330MODULE_DESCRIPTION("MSM DRM Driver");
1331MODULE_LICENSE("GPL");