1/*
  2 * Copyright 2015 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DC_HW_SEQUENCER_PRIVATE_H__
 27#define __DC_HW_SEQUENCER_PRIVATE_H__
 28
 29#include "dc_types.h"
 30
 31enum pipe_gating_control {
 32	PIPE_GATING_CONTROL_DISABLE = 0,
 33	PIPE_GATING_CONTROL_ENABLE,
 34	PIPE_GATING_CONTROL_INIT
 35};
 36
 37struct dce_hwseq_wa {
 38	bool blnd_crtc_trigger;
 39	bool DEGVIDCN10_253;
 40	bool false_optc_underflow;
 41	bool DEGVIDCN10_254;
 42	bool DEGVIDCN21;
 43	bool disallow_self_refresh_during_multi_plane_transition;
 44	bool dp_hpo_and_otg_sequence;
 45	bool wait_hubpret_read_start_during_mpo_transition;
 46};
 47
 48struct hwseq_wa_state {
 49	bool DEGVIDCN10_253_applied;
 50	bool disallow_self_refresh_during_multi_plane_transition_applied;
 51	unsigned int disallow_self_refresh_during_multi_plane_transition_applied_on_frame;
 52};
 53
 54struct pipe_ctx;
 55struct dc_state;
 56struct dc_stream_status;
 57struct dc_writeback_info;
 58struct dchub_init_data;
 59struct dc_static_screen_params;
 60struct resource_pool;
 61struct resource_context;
 62struct stream_resource;
 63struct dc_phy_addr_space_config;
 64struct dc_virtual_addr_space_config;
 65struct hubp;
 66struct dpp;
 67struct dce_hwseq;
 68struct timing_generator;
 69struct tg_color;
 70struct output_pixel_processor;
 71struct mpcc_blnd_cfg;
 72
 73struct hwseq_private_funcs {
 74
 75	void (*disable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 76	void (*enable_stream_gating)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 77	void (*init_pipes)(struct dc *dc, struct dc_state *context);
 78	void (*reset_hw_ctx_wrap)(struct dc *dc, struct dc_state *context);
 79	void (*update_plane_addr)(const struct dc *dc,
 80			struct pipe_ctx *pipe_ctx);
 81	void (*plane_atomic_disconnect)(struct dc *dc,
 82			struct pipe_ctx *pipe_ctx);
 83	void (*update_mpcc)(struct dc *dc, struct pipe_ctx *pipe_ctx);
 84	bool (*set_input_transfer_func)(struct dc *dc,
 85				struct pipe_ctx *pipe_ctx,
 86				const struct dc_plane_state *plane_state);
 87	bool (*set_output_transfer_func)(struct dc *dc,
 88				struct pipe_ctx *pipe_ctx,
 89				const struct dc_stream_state *stream);
 90	void (*power_down)(struct dc *dc);
 91	void (*enable_display_pipe_clock_gating)(struct dc_context *ctx,
 92					bool clock_gating);
 93	bool (*enable_display_power_gating)(struct dc *dc,
 94					uint8_t controller_id,
 95					struct dc_bios *dcb,
 96					enum pipe_gating_control power_gating);
 97	void (*blank_pixel_data)(struct dc *dc,
 98			struct pipe_ctx *pipe_ctx,
 99			bool blank);
100	enum dc_status (*enable_stream_timing)(
101			struct pipe_ctx *pipe_ctx,
102			struct dc_state *context,
103			struct dc *dc);
104	void (*edp_backlight_control)(struct dc_link *link,
105			bool enable);
106	void (*setup_vupdate_interrupt)(struct dc *dc,
107			struct pipe_ctx *pipe_ctx);
108	bool (*did_underflow_occur)(struct dc *dc, struct pipe_ctx *pipe_ctx);
109	void (*init_blank)(struct dc *dc, struct timing_generator *tg);
110	void (*disable_vga)(struct dce_hwseq *hws);
111	void (*bios_golden_init)(struct dc *dc);
112	void (*plane_atomic_power_down)(struct dc *dc,
113			struct dpp *dpp,
114			struct hubp *hubp);
115	void (*plane_atomic_disable)(struct dc *dc, struct pipe_ctx *pipe_ctx);
116	void (*enable_power_gating_plane)(struct dce_hwseq *hws,
117		bool enable);
118	void (*dpp_pg_control)(struct dce_hwseq *hws,
119			unsigned int dpp_inst,
120			bool power_on);
121	void (*hubp_pg_control)(struct dce_hwseq *hws,
122			unsigned int hubp_inst,
123			bool power_on);
124	void (*dsc_pg_control)(struct dce_hwseq *hws,
125			unsigned int dsc_inst,
126			bool power_on);
127	bool (*dsc_pg_status)(struct dce_hwseq *hws,
128			unsigned int dsc_inst);
129	void (*update_odm)(struct dc *dc, struct dc_state *context,
130			struct pipe_ctx *pipe_ctx);
131	void (*program_all_writeback_pipes_in_tree)(struct dc *dc,
132			const struct dc_stream_state *stream,
133			struct dc_state *context);
134	bool (*s0i3_golden_init_wa)(struct dc *dc);
135	void (*set_hdr_multiplier)(struct pipe_ctx *pipe_ctx);
136	void (*verify_allow_pstate_change_high)(struct dc *dc);
137	void (*program_pipe)(struct dc *dc,
138			struct pipe_ctx *pipe_ctx,
139			struct dc_state *context);
140	bool (*wait_for_blank_complete)(struct output_pixel_processor *opp);
141	void (*dccg_init)(struct dce_hwseq *hws);
142	bool (*set_blend_lut)(struct pipe_ctx *pipe_ctx,
143			const struct dc_plane_state *plane_state);
144	bool (*set_shaper_3dlut)(struct pipe_ctx *pipe_ctx,
145			const struct dc_plane_state *plane_state);
146	bool (*set_mcm_luts)(struct pipe_ctx *pipe_ctx,
147			const struct dc_plane_state *plane_state);
148	void (*PLAT_58856_wa)(struct dc_state *context,
149			struct pipe_ctx *pipe_ctx);
150	void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable);
151#ifdef CONFIG_DRM_AMD_DC_DCN
152	void (*program_mall_pipe_config)(struct dc *dc, struct dc_state *context);
153	void (*subvp_update_force_pstate)(struct dc *dc, struct dc_state *context);
154	void (*update_mall_sel)(struct dc *dc, struct dc_state *context);
155	unsigned int (*calculate_dccg_k1_k2_values)(struct pipe_ctx *pipe_ctx,
156			unsigned int *k1_div,
157			unsigned int *k2_div);
158	void (*set_pixels_per_cycle)(struct pipe_ctx *pipe_ctx);
159	bool (*is_dp_dig_pixel_rate_div_policy)(struct pipe_ctx *pipe_ctx);
160#endif
161};
162
163struct dce_hwseq {
164	struct dc_context *ctx;
165	const struct dce_hwseq_registers *regs;
166	const struct dce_hwseq_shift *shifts;
167	const struct dce_hwseq_mask *masks;
168	struct dce_hwseq_wa wa;
169	struct hwseq_wa_state wa_state;
170	struct hwseq_private_funcs funcs;
171
172	PHYSICAL_ADDRESS_LOC fb_base;
173	PHYSICAL_ADDRESS_LOC fb_top;
174	PHYSICAL_ADDRESS_LOC fb_offset;
175	PHYSICAL_ADDRESS_LOC uma_top;
176};
177
178#endif /* __DC_HW_SEQUENCER_PRIVATE_H__ */