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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef __DC_LINK_DP_H__
27#define __DC_LINK_DP_H__
28
29#define LINK_TRAINING_ATTEMPTS 4
30#define LINK_TRAINING_RETRY_DELAY 50 /* ms */
31#define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
32#define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
33#define MAX_MTP_SLOT_COUNT 64
34#define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
35#define TRAINING_AUX_RD_INTERVAL 100 //us
36#define LINK_AUX_WAKE_TIMEOUT_MS 1500 // Timeout when trying to wake unresponsive DPRX.
37
38struct dc_link;
39struct dc_stream_state;
40struct dc_link_settings;
41
42enum {
43 LINK_TRAINING_MAX_RETRY_COUNT = 5,
44 /* to avoid infinite loop where-in the receiver
45 * switches between different VS
46 */
47 LINK_TRAINING_MAX_CR_RETRY = 100,
48 /*
49 * Some receivers fail to train on first try and are good
50 * on subsequent tries. 2 retries should be plenty. If we
51 * don't have a successful training then we don't expect to
52 * ever get one.
53 */
54 LINK_TRAINING_MAX_VERIFY_RETRY = 2,
55 PEAK_FACTOR_X1000 = 1006,
56};
57
58struct dc_link_settings dp_get_max_link_cap(struct dc_link *link);
59
60bool dp_verify_link_cap_with_retries(
61 struct dc_link *link,
62 struct dc_link_settings *known_limit_link_setting,
63 int attempts);
64
65bool dp_validate_mode_timing(
66 struct dc_link *link,
67 const struct dc_crtc_timing *timing);
68
69bool decide_edp_link_settings(struct dc_link *link,
70 struct dc_link_settings *link_setting,
71 uint32_t req_bw);
72
73bool decide_link_settings(
74 struct dc_stream_state *stream,
75 struct dc_link_settings *link_setting);
76
77bool perform_link_training_with_retries(
78 const struct dc_link_settings *link_setting,
79 bool skip_video_pattern,
80 int attempts,
81 struct pipe_ctx *pipe_ctx,
82 enum signal_type signal,
83 bool do_fallback);
84
85bool hpd_rx_irq_check_link_loss_status(
86 struct dc_link *link,
87 union hpd_irq_data *hpd_irq_dpcd_data);
88
89bool is_mst_supported(struct dc_link *link);
90
91bool detect_dp_sink_caps(struct dc_link *link);
92
93void detect_edp_sink_caps(struct dc_link *link);
94
95bool is_dp_active_dongle(const struct dc_link *link);
96
97bool is_dp_branch_device(const struct dc_link *link);
98
99bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);
100
101void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
102
103enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
104void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
105
106bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
107
108void dpcd_set_source_specific_data(struct dc_link *link);
109
110void dpcd_write_cable_id_to_dprx(struct dc_link *link);
111
112/* Write DPCD link configuration data. */
113enum dc_status dpcd_set_link_settings(
114 struct dc_link *link,
115 const struct link_training_settings *lt_settings);
116/* Write DPCD drive settings. */
117enum dc_status dpcd_set_lane_settings(
118 struct dc_link *link,
119 const struct link_training_settings *link_training_setting,
120 uint32_t offset);
121/* Read training status and adjustment requests from DPCD. */
122enum dc_status dp_get_lane_status_and_lane_adjust(
123 struct dc_link *link,
124 const struct link_training_settings *link_training_setting,
125 union lane_status ln_status[LANE_COUNT_DP_MAX],
126 union lane_align_status_updated *ln_align,
127 union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
128 uint32_t offset);
129
130void dp_wait_for_training_aux_rd_interval(
131 struct dc_link *link,
132 uint32_t wait_in_micro_secs);
133
134bool dp_is_cr_done(enum dc_lane_count ln_count,
135 union lane_status *dpcd_lane_status);
136
137enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
138 union lane_status *dpcd_lane_status);
139
140bool dp_is_ch_eq_done(enum dc_lane_count ln_count,
141 union lane_status *dpcd_lane_status);
142bool dp_is_symbol_locked(enum dc_lane_count ln_count,
143 union lane_status *dpcd_lane_status);
144bool dp_is_interlane_aligned(union lane_align_status_updated align_status);
145
146bool dp_is_max_vs_reached(
147 const struct link_training_settings *lt_settings);
148void dp_hw_to_dpcd_lane_settings(
149 const struct link_training_settings *lt_settings,
150 const struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
151 union dpcd_training_lane dpcd_lane_settings[]);
152void dp_decide_lane_settings(
153 const struct link_training_settings *lt_settings,
154 const union lane_adjust ln_adjust[LANE_COUNT_DP_MAX],
155 struct dc_lane_settings hw_lane_settings[LANE_COUNT_DP_MAX],
156 union dpcd_training_lane dpcd_lane_settings[]);
157
158uint32_t dp_translate_training_aux_read_interval(uint32_t dpcd_aux_read_interval);
159
160enum dpcd_training_patterns
161 dc_dp_training_pattern_to_dpcd_training_pattern(
162 struct dc_link *link,
163 enum dc_dp_training_pattern pattern);
164
165uint8_t dc_dp_initialize_scrambling_data_symbols(
166 struct dc_link *link,
167 enum dc_dp_training_pattern pattern);
168
169enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready);
170void dp_set_fec_enable(struct dc_link *link, bool enable);
171bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
172bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable, bool immediate_update);
173void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
174bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
175bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
176
177/* Initialize output parameter lt_settings. */
178void dp_decide_training_settings(
179 struct dc_link *link,
180 const struct dc_link_settings *link_setting,
181 struct link_training_settings *lt_settings);
182
183/* Convert PHY repeater count read from DPCD uint8_t. */
184uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
185
186/* Check DPCD training status registers to detect link loss. */
187enum link_training_result dp_check_link_loss_status(
188 struct dc_link *link,
189 const struct link_training_settings *link_training_setting);
190
191enum dc_status dpcd_configure_lttpr_mode(
192 struct dc_link *link,
193 struct link_training_settings *lt_settings);
194
195enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
196enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link);
197bool dp_is_lttpr_present(struct dc_link *link);
198enum lttpr_mode dp_decide_lttpr_mode(struct dc_link *link, struct dc_link_settings *link_setting);
199void dp_get_lttpr_mode_override(struct dc_link *link, enum lttpr_mode *override);
200enum lttpr_mode dp_decide_8b_10b_lttpr_mode(struct dc_link *link);
201enum lttpr_mode dp_decide_128b_132b_lttpr_mode(struct dc_link *link);
202bool dpcd_write_128b_132b_sst_payload_allocation_table(
203 const struct dc_stream_state *stream,
204 struct dc_link *link,
205 struct link_mst_stream_allocation_table *proposed_table,
206 bool allocate);
207
208enum dc_status dpcd_configure_channel_coding(
209 struct dc_link *link,
210 struct link_training_settings *lt_settings);
211
212bool dpcd_poll_for_allocation_change_trigger(struct dc_link *link);
213
214struct fixed31_32 calculate_sst_avg_time_slots_per_mtp(
215 const struct dc_stream_state *stream,
216 const struct dc_link *link);
217void enable_dp_hpo_output(struct dc_link *link,
218 const struct link_resource *link_res,
219 const struct dc_link_settings *link_settings);
220void disable_dp_hpo_output(struct dc_link *link,
221 const struct link_resource *link_res,
222 enum signal_type signal);
223
224void setup_dp_hpo_stream(struct pipe_ctx *pipe_ctx, bool enable);
225bool is_dp_128b_132b_signal(struct pipe_ctx *pipe_ctx);
226void edp_panel_backlight_power_on(struct dc_link *link, bool wait_for_hpd);
227void dp_receiver_power_ctrl(struct dc_link *link, bool on);
228void dp_source_sequence_trace(struct dc_link *link, uint8_t dp_test_mode);
229void dp_enable_link_phy(
230 struct dc_link *link,
231 const struct link_resource *link_res,
232 enum signal_type signal,
233 enum clock_source_id clock_source,
234 const struct dc_link_settings *link_settings);
235void edp_add_delay_for_T9(struct dc_link *link);
236bool edp_receiver_ready_T9(struct dc_link *link);
237bool edp_receiver_ready_T7(struct dc_link *link);
238
239void dp_disable_link_phy(struct dc_link *link, const struct link_resource *link_res,
240 enum signal_type signal);
241
242void dp_disable_link_phy_mst(struct dc_link *link, const struct link_resource *link_res,
243 enum signal_type signal);
244
245bool dp_set_hw_training_pattern(
246 struct dc_link *link,
247 const struct link_resource *link_res,
248 enum dc_dp_training_pattern pattern,
249 uint32_t offset);
250
251void dp_set_hw_lane_settings(
252 struct dc_link *link,
253 const struct link_resource *link_res,
254 const struct link_training_settings *link_settings,
255 uint32_t offset);
256
257void dp_set_hw_test_pattern(
258 struct dc_link *link,
259 const struct link_resource *link_res,
260 enum dp_test_pattern test_pattern,
261 uint8_t *custom_pattern,
262 uint32_t custom_pattern_size);
263
264void dp_retrain_link_dp_test(struct dc_link *link,
265 struct dc_link_settings *link_setting,
266 bool skip_video_pattern);
267#endif /* __DC_LINK_DP_H__ */