Loading...
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef __DML2_DISPLAY_MODE_VBA_H__
28#define __DML2_DISPLAY_MODE_VBA_H__
29
30struct display_mode_lib;
31
32void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
33
34#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
35
36dml_get_attr_decl(clk_dcf_deepsleep);
37dml_get_attr_decl(wm_urgent);
38dml_get_attr_decl(wm_memory_trip);
39dml_get_attr_decl(wm_writeback_urgent);
40dml_get_attr_decl(wm_stutter_exit);
41dml_get_attr_decl(wm_stutter_enter_exit);
42dml_get_attr_decl(wm_z8_stutter_exit);
43dml_get_attr_decl(wm_z8_stutter_enter_exit);
44dml_get_attr_decl(stutter_efficiency_z8);
45dml_get_attr_decl(stutter_num_bursts_z8);
46dml_get_attr_decl(wm_dram_clock_change);
47dml_get_attr_decl(wm_writeback_dram_clock_change);
48dml_get_attr_decl(stutter_efficiency_no_vblank);
49dml_get_attr_decl(stutter_efficiency);
50dml_get_attr_decl(stutter_period);
51dml_get_attr_decl(urgent_latency);
52dml_get_attr_decl(urgent_extra_latency);
53dml_get_attr_decl(nonurgent_latency);
54dml_get_attr_decl(dram_clock_change_latency);
55dml_get_attr_decl(dispclk_calculated);
56dml_get_attr_decl(total_data_read_bw);
57dml_get_attr_decl(return_bw);
58dml_get_attr_decl(tcalc);
59dml_get_attr_decl(fraction_of_urgent_bandwidth);
60dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
61dml_get_attr_decl(cstate_max_cap_mode);
62dml_get_attr_decl(comp_buffer_size_kbytes);
63dml_get_attr_decl(pixel_chunk_size_in_kbyte);
64dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
65dml_get_attr_decl(meta_chunk_size_in_kbyte);
66dml_get_attr_decl(min_pixel_chunk_size_in_byte);
67dml_get_attr_decl(min_meta_chunk_size_in_byte);
68dml_get_attr_decl(fclk_watermark);
69dml_get_attr_decl(usr_retraining_watermark);
70dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
71dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
72dml_get_attr_decl(comp_buffer_reserved_space_zs);
73dml_get_attr_decl(unbounded_request_enabled);
74
75#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
76
77dml_get_pipe_attr_decl(dsc_delay);
78dml_get_pipe_attr_decl(dppclk_calculated);
79dml_get_pipe_attr_decl(dscclk_calculated);
80dml_get_pipe_attr_decl(min_ttu_vblank);
81dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
82dml_get_pipe_attr_decl(vratio_prefetch_l);
83dml_get_pipe_attr_decl(vratio_prefetch_c);
84dml_get_pipe_attr_decl(dst_x_after_scaler);
85dml_get_pipe_attr_decl(dst_y_after_scaler);
86dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
87dml_get_pipe_attr_decl(dst_y_per_row_vblank);
88dml_get_pipe_attr_decl(dst_y_prefetch);
89dml_get_pipe_attr_decl(dst_y_per_vm_flip);
90dml_get_pipe_attr_decl(dst_y_per_row_flip);
91dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
92dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
93dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
94dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
95dml_get_pipe_attr_decl(dpte_row_height_linear_c);
96dml_get_pipe_attr_decl(swath_height_l);
97dml_get_pipe_attr_decl(swath_height_c);
98dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
99dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
100dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
101dml_get_pipe_attr_decl(vm_group_size_in_bytes);
102dml_get_pipe_attr_decl(det_buffer_size_kbytes);
103dml_get_pipe_attr_decl(dpte_row_height_linear_l);
104dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
105dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
106dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
107dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
108dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
109dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
110dml_get_pipe_attr_decl(pte_buffer_mode);
111dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
112dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
113dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
114dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
115dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
116dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
117dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
118dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
119dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
120dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
121dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
122dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
123dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
124dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
125dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
126dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
127dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
128dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
129dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
130dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
131dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
132dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
133dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
134dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
135dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
136dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
137
138dml_get_pipe_attr_decl(vstartup);
139dml_get_pipe_attr_decl(vupdate_offset);
140dml_get_pipe_attr_decl(vupdate_width);
141dml_get_pipe_attr_decl(vready_offset);
142dml_get_pipe_attr_decl(vready_at_or_after_vsync);
143dml_get_pipe_attr_decl(min_dst_y_next_start);
144dml_get_pipe_attr_decl(vstartup_calculated);
145dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
146dml_get_pipe_attr_decl(surface_size_in_mall);
147
148double get_total_immediate_flip_bytes(
149 struct display_mode_lib *mode_lib,
150 const display_e2e_pipe_params_st *pipes,
151 unsigned int num_pipes);
152double get_total_immediate_flip_bw(
153 struct display_mode_lib *mode_lib,
154 const display_e2e_pipe_params_st *pipes,
155 unsigned int num_pipes);
156double get_total_prefetch_bw(
157 struct display_mode_lib *mode_lib,
158 const display_e2e_pipe_params_st *pipes,
159 unsigned int num_pipes);
160unsigned int dml_get_voltage_level(
161 struct display_mode_lib *mode_lib,
162 const display_e2e_pipe_params_st *pipes,
163 unsigned int num_pipes);
164
165unsigned int get_total_surface_size_in_mall_bytes(
166 struct display_mode_lib *mode_lib,
167 const display_e2e_pipe_params_st *pipes,
168 unsigned int num_pipes);
169
170bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
171 const display_e2e_pipe_params_st *pipes,
172 unsigned int num_pipes,
173 unsigned int pipe_idx);
174void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
175
176void Calculate256BBlockSizes(
177 enum source_format_class SourcePixelFormat,
178 enum dm_swizzle_mode SurfaceTiling,
179 unsigned int BytePerPixelY,
180 unsigned int BytePerPixelC,
181 unsigned int *BlockHeight256BytesY,
182 unsigned int *BlockHeight256BytesC,
183 unsigned int *BlockWidth256BytesY,
184 unsigned int *BlockWidth256BytesC);
185
186struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
187 unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
188 double dummy_single_array[2][DC__NUM_DPP__MAX];
189 unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
190 double dummy_double_array[2][DC__NUM_DPP__MAX];
191 bool dummy_boolean_array[DC__NUM_DPP__MAX];
192 bool dummy_boolean;
193 bool dummy_boolean2;
194 enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
195 DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
196 bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
197 unsigned int ReorderBytes;
198 unsigned int VMDataOnlyReturnBW;
199 double HostVMInefficiencyFactor;
200 DmlPipe myPipe;
201 SOCParametersList mmSOCParameters;
202 double dummy_unit_vector[DC__NUM_DPP__MAX];
203 double dummy_single[2];
204 enum clock_change_support dummy_dramchange_support;
205 enum dm_fclock_change_support dummy_fclkchange_support;
206 bool dummy_USRRetrainingSupport;
207};
208
209struct dml32_ModeSupportAndSystemConfigurationFull {
210 unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
211 double dummy_double_array[2][DC__NUM_DPP__MAX];
212 DmlPipe SurfParameters[DC__NUM_DPP__MAX];
213 double dummy_single[5];
214 double dummy_single2[5];
215 SOCParametersList mSOCParameters;
216 unsigned int MaximumSwathWidthSupportLuma;
217 unsigned int MaximumSwathWidthSupportChroma;
218 double DSTYAfterScaler[DC__NUM_DPP__MAX];
219 double DSTXAfterScaler[DC__NUM_DPP__MAX];
220 double MaxTotalVActiveRDBandwidth;
221 bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
222 enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
223 DmlPipe myPipe;
224 unsigned int dummy_integer[4];
225 unsigned int TotalNumberOfActiveOTG;
226 unsigned int TotalNumberOfActiveHDMIFRL;
227 unsigned int TotalNumberOfActiveDP2p0;
228 unsigned int TotalNumberOfActiveDP2p0Outputs;
229 unsigned int TotalDSCUnitsRequired;
230 unsigned int ReorderingBytes;
231 unsigned int TotalSlots;
232 unsigned int NumberOfDPPDSC;
233 unsigned int NumberOfDPPNoDSC;
234 unsigned int NextPrefetchModeState;
235 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
236 bool MPCCombineMethodAsPossible;
237 bool FullFrameMALLPStateMethod;
238 bool SubViewportMALLPStateMethod;
239 bool PhantomPipeMALLPStateMethod;
240 bool NoChroma;
241 bool TotalAvailablePipesSupportNoDSC;
242 bool TotalAvailablePipesSupportDSC;
243 enum odm_combine_mode ODMModeNoDSC;
244 enum odm_combine_mode ODMModeDSC;
245 double RequiredDISPCLKPerSurfaceNoDSC;
246 double RequiredDISPCLKPerSurfaceDSC;
247 double BWOfNonCombinedSurfaceOfMaximumBandwidth;
248 double VMDataOnlyReturnBWPerState;
249 double HostVMInefficiencyFactor;
250 bool dummy_boolean[2];
251};
252
253struct dummy_vars {
254 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
255 DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
256 struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
257};
258
259struct vba_vars_st {
260 ip_params_st ip;
261 soc_bounding_box_st soc;
262
263 int maxMpcComb;
264 bool UseMaximumVStartup;
265
266 double MaxVRatioPre;
267 double WritebackDISPCLK;
268 double DPPCLKUsingSingleDPPLuma;
269 double DPPCLKUsingSingleDPPChroma;
270 double DISPCLKWithRamping;
271 double DISPCLKWithoutRamping;
272 double GlobalDPPCLK;
273 double DISPCLKWithRampingRoundedToDFSGranularity;
274 double DISPCLKWithoutRampingRoundedToDFSGranularity;
275 double MaxDispclkRoundedToDFSGranularity;
276 bool DCCEnabledAnyPlane;
277 double ReturnBandwidthToDCN;
278 unsigned int TotalActiveDPP;
279 unsigned int TotalDCCActiveDPP;
280 double UrgentRoundTripAndOutOfOrderLatency;
281 double StutterPeriod;
282 double FrameTimeForMinFullDETBufferingTime;
283 double AverageReadBandwidth;
284 double TotalRowReadBandwidth;
285 double PartOfBurstThatFitsInROB;
286 double StutterBurstTime;
287 unsigned int NextPrefetchMode;
288 double NextMaxVStartup;
289 double VBlankTime;
290 double SmallestVBlank;
291 enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
292 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
293 double EffectiveDETPlusLBLinesLuma;
294 double EffectiveDETPlusLBLinesChroma;
295 double UrgentLatencySupportUsLuma;
296 double UrgentLatencySupportUsChroma;
297 unsigned int DSCFormatFactor;
298
299 bool DummyPStateCheck;
300 bool DRAMClockChangeSupportsVActive;
301 bool PrefetchModeSupported;
302 bool PrefetchAndImmediateFlipSupported;
303 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
304 double XFCRemoteSurfaceFlipDelay;
305 double TInitXFill;
306 double TslvChk;
307 double SrcActiveDrainRate;
308 bool ImmediateFlipSupported;
309 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
310
311 bool PrefetchERROR;
312
313 unsigned int VStartupLines;
314 unsigned int ActiveDPPs;
315 unsigned int LBLatencyHidingSourceLinesY;
316 unsigned int LBLatencyHidingSourceLinesC;
317 double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state
318 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
319 double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
320 double MinActiveDRAMClockChangeMargin;
321 double InitFillLevel;
322 double FinalFillMargin;
323 double FinalFillLevel;
324 double RemainingFillLevel;
325 double TFinalxFill;
326
327 //
328 // SOC Bounding Box Parameters
329 //
330 double SRExitTime;
331 double SREnterPlusExitTime;
332 double UrgentLatencyPixelDataOnly;
333 double UrgentLatencyPixelMixedWithVMData;
334 double UrgentLatencyVMDataOnly;
335 double UrgentLatency; // max of the above three
336 double USRRetrainingLatency;
337 double SMNLatency;
338 double FCLKChangeLatency;
339 unsigned int MALLAllocatedForDCNFinal;
340 double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
341 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
342 double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
343 double WritebackLatency;
344 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
345 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
346 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
347 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
348 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
349 double NumberOfChannels;
350 double DRAMChannelWidth;
351 double FabricDatapathToDCNDataReturn;
352 double ReturnBusWidth;
353 double Downspreading;
354 double DISPCLKDPPCLKDSCCLKDownSpreading;
355 double DISPCLKDPPCLKVCOSpeed;
356 double RoundTripPingLatencyCycles;
357 double UrgentOutOfOrderReturnPerChannel;
358 double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
359 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
360 double UrgentOutOfOrderReturnPerChannelVMDataOnly;
361 unsigned int VMMPageSize;
362 double DRAMClockChangeLatency;
363 double XFCBusTransportTime;
364 bool UseUrgentBurstBandwidth;
365 double XFCXBUFLatencyTolerance;
366
367 //
368 // IP Parameters
369 //
370 unsigned int ROBBufferSizeInKByte;
371 unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
372 double DETBufferSizeInTime;
373 unsigned int DPPOutputBufferPixels;
374 unsigned int OPPOutputBufferLines;
375 unsigned int PixelChunkSizeInKByte;
376 double ReturnBW;
377 bool GPUVMEnable;
378 bool HostVMEnable;
379 unsigned int GPUVMMaxPageTableLevels;
380 unsigned int HostVMMaxPageTableLevels;
381 unsigned int HostVMCachedPageTableLevels;
382 unsigned int OverrideGPUVMPageTableLevels;
383 unsigned int OverrideHostVMPageTableLevels;
384 unsigned int MetaChunkSize;
385 unsigned int MinMetaChunkSizeBytes;
386 unsigned int WritebackChunkSize;
387 bool ODMCapability;
388 unsigned int NumberOfDSC;
389 unsigned int LineBufferSize;
390 unsigned int MaxLineBufferLines;
391 unsigned int WritebackInterfaceLumaBufferSize;
392 unsigned int WritebackInterfaceChromaBufferSize;
393 unsigned int WritebackChromaLineBufferWidth;
394 enum writeback_config WritebackConfiguration;
395 double MaxDCHUBToPSCLThroughput;
396 double MaxPSCLToLBThroughput;
397 unsigned int PTEBufferSizeInRequestsLuma;
398 unsigned int PTEBufferSizeInRequestsChroma;
399 double DISPCLKRampingMargin;
400 unsigned int MaxInterDCNTileRepeaters;
401 bool XFCSupported;
402 double XFCSlvChunkSize;
403 double XFCFillBWOverhead;
404 double XFCFillConstant;
405 double XFCTSlvVupdateOffset;
406 double XFCTSlvVupdateWidth;
407 double XFCTSlvVreadyOffset;
408 double DPPCLKDelaySubtotal;
409 double DPPCLKDelaySCL;
410 double DPPCLKDelaySCLLBOnly;
411 double DPPCLKDelayCNVCFormater;
412 double DPPCLKDelayCNVCCursor;
413 double DISPCLKDelaySubtotal;
414 bool ProgressiveToInterlaceUnitInOPP;
415 unsigned int CompressedBufferSegmentSizeInkByteFinal;
416 unsigned int CompbufReservedSpace64B;
417 unsigned int CompbufReservedSpaceZs;
418 unsigned int LineBufferSizeFinal;
419 unsigned int MaximumPixelsPerLinePerDSCUnit;
420 unsigned int AlphaPixelChunkSizeInKByte;
421 double MinPixelChunkSizeBytes;
422 unsigned int DCCMetaBufferSizeBytes;
423 // Pipe/Plane Parameters
424
425 /** @VoltageLevel:
426 * Every ASIC has a fixed number of DPM states, and some devices might
427 * have some particular voltage configuration that does not map
428 * directly to the DPM states. This field tells how many states the
429 * target device supports; even though this field combines the DPM and
430 * special SOC voltages, it mostly matches the total number of DPM
431 * states.
432 */
433 int VoltageLevel;
434 double FabricClock;
435 double DRAMSpeed;
436 double DISPCLK;
437 double SOCCLK;
438 double DCFCLK;
439 unsigned int MaxTotalDETInKByte;
440 unsigned int MinCompressedBufferSizeInKByte;
441 unsigned int NumberOfActiveSurfaces;
442 bool ViewportStationary[DC__NUM_DPP__MAX];
443 unsigned int RefreshRate[DC__NUM_DPP__MAX];
444 double OutputBPP[DC__NUM_DPP__MAX];
445 unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
446 bool SynchronizeTimingsFinal;
447 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
448 bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
449 unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
450 unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
451 enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
452 bool DRRDisplay[DC__NUM_DPP__MAX];
453 bool PteBufferMode[DC__NUM_DPP__MAX];
454 enum dm_output_type OutputType[DC__NUM_DPP__MAX];
455 enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
456
457 unsigned int NumberOfActivePlanes;
458 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
459 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
460 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
461 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
462 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
463 unsigned int PitchY[DC__NUM_DPP__MAX];
464 unsigned int PitchC[DC__NUM_DPP__MAX];
465 double HRatio[DC__NUM_DPP__MAX];
466 double VRatio[DC__NUM_DPP__MAX];
467 unsigned int htaps[DC__NUM_DPP__MAX];
468 unsigned int vtaps[DC__NUM_DPP__MAX];
469 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
470 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
471 unsigned int HTotal[DC__NUM_DPP__MAX];
472 unsigned int VTotal[DC__NUM_DPP__MAX];
473 unsigned int VTotal_Max[DC__NUM_DPP__MAX];
474 unsigned int VTotal_Min[DC__NUM_DPP__MAX];
475 int DPPPerPlane[DC__NUM_DPP__MAX];
476 double PixelClock[DC__NUM_DPP__MAX];
477 double PixelClockBackEnd[DC__NUM_DPP__MAX];
478 bool DCCEnable[DC__NUM_DPP__MAX];
479 bool FECEnable[DC__NUM_DPP__MAX];
480 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
481 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
482 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
483 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
484 bool WritebackEnable[DC__NUM_DPP__MAX];
485 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
486 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
487 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
488 double WritebackSourceHeight[DC__NUM_DPP__MAX];
489 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
490 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
491 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
492 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
493 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
494 double WritebackHRatio[DC__NUM_DPP__MAX];
495 double WritebackVRatio[DC__NUM_DPP__MAX];
496 unsigned int HActive[DC__NUM_DPP__MAX];
497 unsigned int VActive[DC__NUM_DPP__MAX];
498 bool Interlace[DC__NUM_DPP__MAX];
499 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
500 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
501 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
502 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
503 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
504 double DCCRate[DC__NUM_DPP__MAX];
505 double AverageDCCCompressionRate;
506 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
507 double OutputBpp[DC__NUM_DPP__MAX];
508 bool DSCEnabled[DC__NUM_DPP__MAX];
509 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
510 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
511 enum output_encoder_class Output[DC__NUM_DPP__MAX];
512 bool skip_dio_check[DC__NUM_DPP__MAX];
513 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
514 bool SynchronizedVBlank;
515 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
516 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
517 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
518 bool XFCEnabled[DC__NUM_DPP__MAX];
519 bool ScalerEnabled[DC__NUM_DPP__MAX];
520 unsigned int VBlankNom[DC__NUM_DPP__MAX];
521 bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
522
523 // Intermediates/Informational
524 bool ImmediateFlipSupport;
525 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
526 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
527 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
528 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
529 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
530 double LastPixelOfLineExtraWatermark;
531 double TotalDataReadBandwidth;
532 unsigned int TotalActiveWriteback;
533 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
534 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
535 double BandwidthAvailableForImmediateFlip;
536 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
537 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
538 unsigned int MinPrefetchMode;
539 unsigned int MaxPrefetchMode;
540 bool AnyLinesForVMOrRowTooLarge;
541 double MaxVStartup;
542 bool IgnoreViewportPositioning;
543 bool ErrorResult[DC__NUM_DPP__MAX];
544 //
545 // Calculated dml_ml->vba.Outputs
546 //
547 double DCFCLKDeepSleep;
548 double UrgentWatermark;
549 double UrgentExtraLatency;
550 double WritebackUrgentWatermark;
551 double StutterExitWatermark;
552 double StutterEnterPlusExitWatermark;
553 double DRAMClockChangeWatermark;
554 double WritebackDRAMClockChangeWatermark;
555 double StutterEfficiency;
556 double StutterEfficiencyNotIncludingVBlank;
557 double NonUrgentLatencyTolerance;
558 double MinActiveDRAMClockChangeLatencySupported;
559 double Z8StutterEfficiencyBestCase;
560 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
561 double Z8StutterEfficiencyNotIncludingVBlankBestCase;
562 double StutterPeriodBestCase;
563 Watermarks Watermark;
564 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
565 unsigned int CompBufReservedSpaceKBytes;
566 unsigned int CompBufReservedSpace64B;
567 unsigned int CompBufReservedSpaceZs;
568 bool CompBufReservedSpaceNeedAdjustment;
569
570 // These are the clocks calcuated by the library but they are not actually
571 // used explicitly. They are fetched by tests and then possibly used. The
572 // ultimate values to use are the ones specified by the parameters to DML
573 double DISPCLK_calculated;
574 double DPPCLK_calculated[DC__NUM_DPP__MAX];
575
576 bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
577
578 bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
579 bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
580 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
581 double VUpdateWidthPix[DC__NUM_DPP__MAX];
582 double VReadyOffsetPix[DC__NUM_DPP__MAX];
583
584 unsigned int TotImmediateFlipBytes;
585 double TCalc;
586
587 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
588 unsigned int cache_num_pipes;
589 unsigned int pipe_plane[DC__NUM_DPP__MAX];
590
591 /* vba mode support */
592 /*inputs*/
593 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
594 double MaxHSCLRatio;
595 double MaxVSCLRatio;
596 unsigned int MaxNumWriteback;
597 bool WritebackLumaAndChromaScalingSupported;
598 bool Cursor64BppSupport;
599 double DCFCLKPerState[DC__VOLTAGE_STATES];
600 double DCFCLKState[DC__VOLTAGE_STATES][2];
601 double FabricClockPerState[DC__VOLTAGE_STATES];
602 double SOCCLKPerState[DC__VOLTAGE_STATES];
603 double PHYCLKPerState[DC__VOLTAGE_STATES];
604 double DTBCLKPerState[DC__VOLTAGE_STATES];
605 double MaxDppclk[DC__VOLTAGE_STATES];
606 double MaxDSCCLK[DC__VOLTAGE_STATES];
607 double DRAMSpeedPerState[DC__VOLTAGE_STATES];
608 double MaxDispclk[DC__VOLTAGE_STATES];
609 int VoltageOverrideLevel;
610 double PHYCLKD32PerState[DC__VOLTAGE_STATES];
611
612 /*outputs*/
613 bool ScaleRatioAndTapsSupport;
614 bool SourceFormatPixelAndScanSupport;
615 double TotalBandwidthConsumedGBytePerSecond;
616 bool DCCEnabledInAnyPlane;
617 bool WritebackLatencySupport;
618 bool WritebackModeSupport;
619 bool Writeback10bpc420Supported;
620 bool BandwidthSupport[DC__VOLTAGE_STATES];
621 unsigned int TotalNumberOfActiveWriteback;
622 double CriticalPoint;
623 double ReturnBWToDCNPerState;
624 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
625 bool prefetch_vm_bw_valid;
626 bool prefetch_row_bw_valid;
627 bool NumberOfOTGSupport;
628 bool NonsupportedDSCInputBPC;
629 bool WritebackScaleRatioAndTapsSupport;
630 bool CursorSupport;
631 bool PitchSupport;
632 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
633
634 /* Mode Support Reason */
635 bool P2IWith420;
636 bool DSCOnlyIfNecessaryWithBPP;
637 bool DSC422NativeNotSupported;
638 bool LinkRateDoesNotMatchDPVersion;
639 bool LinkRateForMultistreamNotIndicated;
640 bool BPPForMultistreamNotIndicated;
641 bool MultistreamWithHDMIOreDP;
642 bool MSOOrODMSplitWithNonDPLink;
643 bool NotEnoughLanesForMSO;
644 bool ViewportExceedsSurface;
645
646 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
647 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
648 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
649 bool InvalidCombinationOfMALLUseForPState;
650
651 enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
652 double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
653 double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
654 double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
655 double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
656 double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
657 double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
658 double MetaRowBytesThisState[DC__NUM_DPP__MAX];
659 bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
660 bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
661 bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
662 bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
663
664 unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
665 double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
666 unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
667 unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
668 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
669 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
670 bool ImmediateFlipRequiredFinal;
671 bool DCCProgrammingAssumesScanDirectionUnknownFinal;
672 bool EnoughWritebackUnits;
673 bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
674 bool NumberOfDP2p0Support;
675 unsigned int MaxNumDP2p0Streams;
676 unsigned int MaxNumDP2p0Outputs;
677 enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
678 enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
679 double WritebackLineBufferLumaBufferSize;
680 double WritebackLineBufferChromaBufferSize;
681 double WritebackMinHSCLRatio;
682 double WritebackMinVSCLRatio;
683 double WritebackMaxHSCLRatio;
684 double WritebackMaxVSCLRatio;
685 double WritebackMaxHSCLTaps;
686 double WritebackMaxVSCLTaps;
687 unsigned int MaxNumDPP;
688 unsigned int MaxNumOTG;
689 double CursorBufferSize;
690 double CursorChunkSize;
691 unsigned int Mode;
692 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
693 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
694 double ImmediateFlipBW[DC__NUM_DPP__MAX];
695 double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
696
697 double WritebackLumaVExtra;
698 double WritebackChromaVExtra;
699 double WritebackRequiredDISPCLK;
700 double MaximumSwathWidthSupport;
701 double MaximumSwathWidthInDETBuffer;
702 double MaximumSwathWidthInLineBuffer;
703 double MaxDispclkRoundedDownToDFSGranularity;
704 double MaxDppclkRoundedDownToDFSGranularity;
705 double PlaneRequiredDISPCLKWithoutODMCombine;
706 double PlaneRequiredDISPCLKWithODMCombine;
707 double PlaneRequiredDISPCLK;
708 double TotalNumberOfActiveOTG;
709 double FECOverhead;
710 double EffectiveFECOverhead;
711 double Outbpp;
712 unsigned int OutbppDSC;
713 double TotalDSCUnitsRequired;
714 double bpp;
715 unsigned int slices;
716 double SwathWidthGranularityY;
717 double RoundedUpMaxSwathSizeBytesY;
718 double SwathWidthGranularityC;
719 double RoundedUpMaxSwathSizeBytesC;
720 double EffectiveDETLBLinesLuma;
721 double EffectiveDETLBLinesChroma;
722 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
723 double PDEAndMetaPTEBytesPerFrameY;
724 double PDEAndMetaPTEBytesPerFrameC;
725 unsigned int MetaRowBytesY;
726 unsigned int MetaRowBytesC;
727 unsigned int DPTEBytesPerRowC;
728 unsigned int DPTEBytesPerRowY;
729 double ExtraLatency;
730 double TimeCalc;
731 double TWait;
732 double MaximumReadBandwidthWithPrefetch;
733 double MaximumReadBandwidthWithoutPrefetch;
734 double total_dcn_read_bw_with_flip;
735 double total_dcn_read_bw_with_flip_no_urgent_burst;
736 double FractionOfUrgentBandwidth;
737 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
738
739 /* ms locals */
740 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
741 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
742 int NoOfDPPThisState[DC__NUM_DPP__MAX];
743 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
744 double SwathWidthYThisState[DC__NUM_DPP__MAX];
745 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
746 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
747 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
748 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
749 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
750 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
751 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
752 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
753 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
754 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
755 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
756 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
757 bool PrefetchSupported[DC__VOLTAGE_STATES][2];
758 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
759 double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
760 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
761 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
762 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
763 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
764 bool ModeSupport[DC__VOLTAGE_STATES][2];
765 double ReturnBWPerState[DC__VOLTAGE_STATES][2];
766 bool DIOSupport[DC__VOLTAGE_STATES];
767 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
768 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
769 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
770 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
771 bool ROBSupport[DC__VOLTAGE_STATES][2];
772 //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
773 bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
774 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
775 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
776 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
777 double PrefetchBW[DC__NUM_DPP__MAX];
778 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
779 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
780 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
781 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
782 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
783 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
784 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
785 double PrefillY[DC__NUM_DPP__MAX];
786 double PrefillC[DC__NUM_DPP__MAX];
787 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
788 double LinesForMetaPTE[DC__NUM_DPP__MAX];
789 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
790 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
791 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
792 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
793 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
794 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
795 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
796 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
797 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
798 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
799 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
800 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
801 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
802 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
803 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
804 double MaxSwathHeightY[DC__NUM_DPP__MAX];
805 double MaxSwathHeightC[DC__NUM_DPP__MAX];
806 double MinSwathHeightY[DC__NUM_DPP__MAX];
807 double MinSwathHeightC[DC__NUM_DPP__MAX];
808 double ReadBandwidthLuma[DC__NUM_DPP__MAX];
809 double ReadBandwidthChroma[DC__NUM_DPP__MAX];
810 double ReadBandwidth[DC__NUM_DPP__MAX];
811 double WriteBandwidth[DC__NUM_DPP__MAX];
812 double PSCL_FACTOR[DC__NUM_DPP__MAX];
813 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
814 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
815 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
816 double AlignedYPitch[DC__NUM_DPP__MAX];
817 double AlignedCPitch[DC__NUM_DPP__MAX];
818 double MaximumSwathWidth[DC__NUM_DPP__MAX];
819 double cursor_bw[DC__NUM_DPP__MAX];
820 double cursor_bw_pre[DC__NUM_DPP__MAX];
821 double Tno_bw[DC__NUM_DPP__MAX];
822 double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
823 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
824 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
825 double final_flip_bw[DC__NUM_DPP__MAX];
826 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
827 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
828 unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
829 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
830 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
831 unsigned int meta_req_height[DC__NUM_DPP__MAX];
832 unsigned int meta_req_width[DC__NUM_DPP__MAX];
833 unsigned int meta_row_height[DC__NUM_DPP__MAX];
834 unsigned int meta_row_width[DC__NUM_DPP__MAX];
835 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
836 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
837 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
838 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
839 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
840 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
841 double meta_row_bw[DC__NUM_DPP__MAX];
842 double dpte_row_bw[DC__NUM_DPP__MAX];
843 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
844 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
845 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
846 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
847 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
848 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
849 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
850 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
851 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
852 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
853 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
854
855
856 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
857 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
858 double MaximumSwathWidthInLineBufferLuma;
859 double MaximumSwathWidthInLineBufferChroma;
860 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
861 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
862 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
863 double dummy1[DC__NUM_DPP__MAX];
864 double dummy2[DC__NUM_DPP__MAX];
865 unsigned int dummy3[DC__NUM_DPP__MAX];
866 unsigned int dummy4[DC__NUM_DPP__MAX];
867 double dummy5;
868 double dummy6;
869 double dummy7[DC__NUM_DPP__MAX];
870 double dummy8[DC__NUM_DPP__MAX];
871 double dummy13[DC__NUM_DPP__MAX];
872 double dummy_double_array[2][DC__NUM_DPP__MAX];
873 unsigned int dummyinteger3[DC__NUM_DPP__MAX];
874 unsigned int dummyinteger4[DC__NUM_DPP__MAX];
875 unsigned int dummyinteger5;
876 unsigned int dummyinteger6;
877 unsigned int dummyinteger7;
878 unsigned int dummyinteger8;
879 unsigned int dummyinteger9;
880 unsigned int dummyinteger10;
881 unsigned int dummyinteger11;
882 unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
883
884 bool dummysinglestring;
885 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
886 double PlaneRequiredDISPCLKWithODMCombine2To1;
887 double PlaneRequiredDISPCLKWithODMCombine4To1;
888 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
889 bool LinkDSCEnable;
890 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
891 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
892 double SwathWidthCThisState[DC__NUM_DPP__MAX];
893 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
894 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
895 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
896
897 unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
898 unsigned int NotEnoughUrgentLatencyHidingPre;
899 int PTEBufferSizeInRequestsForLuma;
900 int PTEBufferSizeInRequestsForChroma;
901
902 // Missing from VBA
903 int dpte_group_bytes_chroma;
904 unsigned int vm_group_bytes_chroma;
905 double dst_x_after_scaler;
906 double dst_y_after_scaler;
907 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
908
909 /* perf locals*/
910 double PrefetchBandwidth[DC__NUM_DPP__MAX];
911 double VInitPreFillY[DC__NUM_DPP__MAX];
912 double VInitPreFillC[DC__NUM_DPP__MAX];
913 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
914 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
915 unsigned int VStartup[DC__NUM_DPP__MAX];
916 double DSTYAfterScaler[DC__NUM_DPP__MAX];
917 double DSTXAfterScaler[DC__NUM_DPP__MAX];
918 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
919 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
920 double VRatioPrefetchY[DC__NUM_DPP__MAX];
921 double VRatioPrefetchC[DC__NUM_DPP__MAX];
922 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
923 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
924 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
925 double MinTTUVBlank[DC__NUM_DPP__MAX];
926 double BytePerPixelDETY[DC__NUM_DPP__MAX];
927 double BytePerPixelDETC[DC__NUM_DPP__MAX];
928 double SwathWidthY[DC__NUM_DPP__MAX];
929 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
930 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
931 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
932 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
933 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
934 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
935 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
936 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
937 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
938 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
939 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
940 double MetaRowByte[DC__NUM_DPP__MAX];
941 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
942 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
943 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
944 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
945 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
946 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
947 double DSCCLK_calculated[DC__NUM_DPP__MAX];
948 unsigned int DSCDelay[DC__NUM_DPP__MAX];
949 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
950 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
951 double DPPCLK[DC__NUM_DPP__MAX];
952 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
953 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
954 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
955 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
956 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
957 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
958 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
959 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
960 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
961 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
962 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
963 double XFCTransferDelay[DC__NUM_DPP__MAX];
964 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
965 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
966 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
967 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
968 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
969 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
970 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
971 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
972 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
973 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
974 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
975 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
976 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
977 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
978 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
979 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
980 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
981 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
982 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
983 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
984 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
985 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
986 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
987 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
988 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
989 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
990 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
991 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
992 double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
993 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
994 double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
995 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
996 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
997 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
998 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
999 double LinesToFinishSwathTransferStutterCriticalPlane;
1000 unsigned int BytePerPixelYCriticalPlane;
1001 double SwathWidthYCriticalPlane;
1002 double LinesInDETY[DC__NUM_DPP__MAX];
1003 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
1004
1005 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
1006 double SwathWidthC[DC__NUM_DPP__MAX];
1007 unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
1008 unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
1009 unsigned int dummyinteger1;
1010 unsigned int dummyinteger2;
1011 double FinalDRAMClockChangeLatency;
1012 double Tdmdl_vm[DC__NUM_DPP__MAX];
1013 double Tdmdl[DC__NUM_DPP__MAX];
1014 double TSetup[DC__NUM_DPP__MAX];
1015 unsigned int ThisVStartup;
1016 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1017 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1018 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1019 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1020 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1021 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1022 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1023 double VStartupMargin;
1024 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1025
1026 /* Missing from VBA */
1027 unsigned int MaximumMaxVStartupLines;
1028 double FabricAndDRAMBandwidth;
1029 double LinesInDETLuma;
1030 double LinesInDETChroma;
1031 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1032 unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1033 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1034 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1035 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1036 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1037 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1038 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1039 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1040 double qual_row_bw[DC__NUM_DPP__MAX];
1041 double prefetch_row_bw[DC__NUM_DPP__MAX];
1042 double prefetch_vm_bw[DC__NUM_DPP__MAX];
1043
1044 double PTEGroupSize;
1045 unsigned int PDEProcessingBufIn64KBReqs;
1046
1047 double MaxTotalVActiveRDBandwidth;
1048 bool DoUrgentLatencyAdjustment;
1049 double UrgentLatencyAdjustmentFabricClockComponent;
1050 double UrgentLatencyAdjustmentFabricClockReference;
1051 double MinUrgentLatencySupportUs;
1052 double MinFullDETBufferingTime;
1053 double AverageReadBandwidthGBytePerSecond;
1054 bool FirstMainPlane;
1055 bool NotEnoughDETSwathFillLatencyHiding;
1056
1057 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1058 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1059 double HRatioChroma[DC__NUM_DPP__MAX];
1060 double VRatioChroma[DC__NUM_DPP__MAX];
1061 int WritebackSourceWidth[DC__NUM_DPP__MAX];
1062
1063 bool ModeIsSupported;
1064 bool ODMCombine4To1Supported;
1065
1066 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1067 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1068 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1069 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1070 unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1071 unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1072 bool DSCEnable[DC__NUM_DPP__MAX];
1073
1074 double DRAMClockChangeLatencyOverride;
1075
1076 double GPUVMMinPageSize;
1077 double HostVMMinPageSize;
1078
1079 bool MPCCombineEnable[DC__NUM_DPP__MAX];
1080 unsigned int HostVMMaxNonCachedPageTableLevels;
1081 bool DynamicMetadataVMEnabled;
1082 double WritebackInterfaceBufferSize;
1083 double WritebackLineBufferSize;
1084
1085 double DCCRateLuma[DC__NUM_DPP__MAX];
1086 double DCCRateChroma[DC__NUM_DPP__MAX];
1087
1088 double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1089
1090 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1091 bool NumberOfHDMIFRLSupport;
1092 unsigned int MaxNumHDMIFRLOutputs;
1093 int AudioSampleRate[DC__NUM_DPP__MAX];
1094 int AudioSampleLayout[DC__NUM_DPP__MAX];
1095
1096 int PercentMarginOverMinimumRequiredDCFCLK;
1097 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1098 enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1099 unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1100 unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1101 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1102 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1103 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1104 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1105 double UrgLatency[DC__VOLTAGE_STATES];
1106 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1107 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1108 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1109 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1110 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1111 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1112 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1113 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1114 unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1115 unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1116 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1117 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1118 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1119 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1120 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1121 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1122 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1123 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1124 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1125 double WritebackDelayTime[DC__NUM_DPP__MAX];
1126 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1127 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1128 unsigned int dummyinteger17;
1129 unsigned int dummyinteger18;
1130 unsigned int dummyinteger19;
1131 unsigned int dummyinteger20;
1132 unsigned int dummyinteger21;
1133 unsigned int dummyinteger22;
1134 unsigned int dummyinteger23;
1135 unsigned int dummyinteger24;
1136 unsigned int dummyinteger25;
1137 unsigned int dummyinteger26;
1138 unsigned int dummyinteger27;
1139 unsigned int dummyinteger28;
1140 unsigned int dummyinteger29;
1141 bool dummystring[DC__NUM_DPP__MAX];
1142 double BPP;
1143 enum odm_combine_policy ODMCombinePolicy;
1144 bool UseMinimumRequiredDCFCLK;
1145 bool ClampMinDCFCLK;
1146 bool AllowDramClockChangeOneDisplayVactive;
1147
1148 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1149 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1150 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1151 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1152 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1153 double SRExitZ8Time;
1154 double SREnterPlusExitZ8Time;
1155 double Z8StutterExitWatermark;
1156 double Z8StutterEnterPlusExitWatermark;
1157 double Z8StutterEfficiencyNotIncludingVBlank;
1158 double Z8StutterEfficiency;
1159 double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1160 double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1161 double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1162 double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1163 double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1164 double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1165 double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1166 double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1167 bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1168 bool LinkCapacitySupport[DC__VOLTAGE_STATES];
1169 bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1170 unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1171 unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1172 int ConfigReturnBufferSizeInKByte;
1173 enum unbounded_requesting_policy UseUnboundedRequesting;
1174 int CompressedBufferSegmentSizeInkByte;
1175 int CompressedBufferSizeInkByte;
1176 int MetaFIFOSizeInKEntries;
1177 int ZeroSizeBufferEntries;
1178 int COMPBUF_RESERVED_SPACE_64B;
1179 int COMPBUF_RESERVED_SPACE_ZS;
1180 bool UnboundedRequestEnabled;
1181 bool DSC422NativeSupport;
1182 bool NoEnoughUrgentLatencyHiding;
1183 bool NoEnoughUrgentLatencyHidingPre;
1184 int NumberOfStutterBurstsPerFrame;
1185 int Z8NumberOfStutterBurstsPerFrame;
1186 unsigned int MaximumDSCBitsPerComponent;
1187 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1188 double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1189 double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1190 double SurfaceRequiredDISPCLKWithoutODMCombine;
1191 double SurfaceRequiredDISPCLK;
1192 double MinActiveFCLKChangeLatencySupported;
1193 int MinVoltageLevel;
1194 int MaxVoltageLevel;
1195 unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1196 unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1197 unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1198 unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1199 unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1200 bool ExceededMALLSize;
1201 bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1202 unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1203 unsigned int CompressedBufferSizeInkByteThisState;
1204 enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1205 bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1206 enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1207 bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1208 bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1209 enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1210 bool UnboundedRequestEnabledThisState;
1211 bool DRAMClockChangeRequirementFinal;
1212 bool FCLKChangeRequirementFinal;
1213 bool USRRetrainingRequiredFinal;
1214 unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1215 unsigned int nomDETInKByte;
1216 enum mpc_combine_affinity MPCCombineUse[DC__NUM_DPP__MAX];
1217 bool MPCCombineMethodIncompatible;
1218 unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1219 bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1220 enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1221 unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1222 bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1223 bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1224 double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1225 double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1226 bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1227 bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1228 bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1229 bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1230 bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1231 unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1232 unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1233 unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1234 unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1235 unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1236 unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1237 unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1238 bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1239 bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2];
1240 struct dummy_vars dummy_vars;
1241};
1242
1243bool CalculateMinAndMaxPrefetchMode(
1244 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1245 unsigned int *MinPrefetchMode,
1246 unsigned int *MaxPrefetchMode);
1247
1248double CalculateWriteBackDISPCLK(
1249 enum source_format_class WritebackPixelFormat,
1250 double PixelClock,
1251 double WritebackHRatio,
1252 double WritebackVRatio,
1253 unsigned int WritebackLumaHTaps,
1254 unsigned int WritebackLumaVTaps,
1255 unsigned int WritebackChromaHTaps,
1256 unsigned int WritebackChromaVTaps,
1257 double WritebackDestinationWidth,
1258 unsigned int HTotal,
1259 unsigned int WritebackChromaLineBufferWidth);
1260
1261#endif /* _DML2_DISPLAY_MODE_VBA_H_ */
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27#ifndef __DML2_DISPLAY_MODE_VBA_H__
28#define __DML2_DISPLAY_MODE_VBA_H__
29
30struct display_mode_lib;
31
32void ModeSupportAndSystemConfiguration(struct display_mode_lib *mode_lib);
33
34#define dml_get_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes)
35
36dml_get_attr_decl(clk_dcf_deepsleep);
37dml_get_attr_decl(wm_urgent);
38dml_get_attr_decl(wm_memory_trip);
39dml_get_attr_decl(wm_writeback_urgent);
40dml_get_attr_decl(wm_stutter_exit);
41dml_get_attr_decl(wm_stutter_enter_exit);
42dml_get_attr_decl(wm_z8_stutter_exit);
43dml_get_attr_decl(wm_z8_stutter_enter_exit);
44dml_get_attr_decl(stutter_efficiency_z8);
45dml_get_attr_decl(stutter_num_bursts_z8);
46dml_get_attr_decl(wm_dram_clock_change);
47dml_get_attr_decl(wm_writeback_dram_clock_change);
48dml_get_attr_decl(stutter_efficiency_no_vblank);
49dml_get_attr_decl(stutter_efficiency);
50dml_get_attr_decl(stutter_period);
51dml_get_attr_decl(urgent_latency);
52dml_get_attr_decl(urgent_extra_latency);
53dml_get_attr_decl(nonurgent_latency);
54dml_get_attr_decl(dram_clock_change_latency);
55dml_get_attr_decl(dispclk_calculated);
56dml_get_attr_decl(total_data_read_bw);
57dml_get_attr_decl(return_bw);
58dml_get_attr_decl(tcalc);
59dml_get_attr_decl(fraction_of_urgent_bandwidth);
60dml_get_attr_decl(fraction_of_urgent_bandwidth_imm_flip);
61dml_get_attr_decl(cstate_max_cap_mode);
62dml_get_attr_decl(comp_buffer_size_kbytes);
63dml_get_attr_decl(pixel_chunk_size_in_kbyte);
64dml_get_attr_decl(alpha_pixel_chunk_size_in_kbyte);
65dml_get_attr_decl(meta_chunk_size_in_kbyte);
66dml_get_attr_decl(min_pixel_chunk_size_in_byte);
67dml_get_attr_decl(min_meta_chunk_size_in_byte);
68dml_get_attr_decl(fclk_watermark);
69dml_get_attr_decl(usr_retraining_watermark);
70dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
71dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
72dml_get_attr_decl(comp_buffer_reserved_space_zs);
73dml_get_attr_decl(unbounded_request_enabled);
74
75#define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
76
77dml_get_pipe_attr_decl(dsc_delay);
78dml_get_pipe_attr_decl(dppclk_calculated);
79dml_get_pipe_attr_decl(dscclk_calculated);
80dml_get_pipe_attr_decl(min_ttu_vblank);
81dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
82dml_get_pipe_attr_decl(vratio_prefetch_l);
83dml_get_pipe_attr_decl(vratio_prefetch_c);
84dml_get_pipe_attr_decl(dst_x_after_scaler);
85dml_get_pipe_attr_decl(dst_y_after_scaler);
86dml_get_pipe_attr_decl(dst_y_per_vm_vblank);
87dml_get_pipe_attr_decl(dst_y_per_row_vblank);
88dml_get_pipe_attr_decl(dst_y_prefetch);
89dml_get_pipe_attr_decl(dst_y_per_vm_flip);
90dml_get_pipe_attr_decl(dst_y_per_row_flip);
91dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_l);
92dml_get_pipe_attr_decl(dst_y_per_pte_row_nom_c);
93dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_l);
94dml_get_pipe_attr_decl(dst_y_per_meta_row_nom_c);
95dml_get_pipe_attr_decl(dpte_row_height_linear_c);
96dml_get_pipe_attr_decl(swath_height_l);
97dml_get_pipe_attr_decl(swath_height_c);
98dml_get_pipe_attr_decl(det_stored_buffer_size_l_bytes);
99dml_get_pipe_attr_decl(det_stored_buffer_size_c_bytes);
100dml_get_pipe_attr_decl(dpte_group_size_in_bytes);
101dml_get_pipe_attr_decl(vm_group_size_in_bytes);
102dml_get_pipe_attr_decl(det_buffer_size_kbytes);
103dml_get_pipe_attr_decl(dpte_row_height_linear_l);
104dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_l_in_us);
105dml_get_pipe_attr_decl(refcyc_per_pte_group_nom_c_in_us);
106dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_l_in_us);
107dml_get_pipe_attr_decl(refcyc_per_pte_group_vblank_c_in_us);
108dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_l_in_us);
109dml_get_pipe_attr_decl(refcyc_per_pte_group_flip_c_in_us);
110dml_get_pipe_attr_decl(pte_buffer_mode);
111dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank);
112dml_get_pipe_attr_decl(refcyc_per_vm_group_flip);
113dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank);
114dml_get_pipe_attr_decl(refcyc_per_vm_req_flip);
115dml_get_pipe_attr_decl(refcyc_per_vm_group_vblank_in_us);
116dml_get_pipe_attr_decl(refcyc_per_vm_group_flip_in_us);
117dml_get_pipe_attr_decl(refcyc_per_vm_req_vblank_in_us);
118dml_get_pipe_attr_decl(refcyc_per_vm_req_flip_in_us);
119dml_get_pipe_attr_decl(refcyc_per_vm_dmdata_in_us);
120dml_get_pipe_attr_decl(dmdata_dl_delta_in_us);
121dml_get_pipe_attr_decl(refcyc_per_line_delivery_l_in_us);
122dml_get_pipe_attr_decl(refcyc_per_line_delivery_c_in_us);
123dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_l_in_us);
124dml_get_pipe_attr_decl(refcyc_per_line_delivery_pre_c_in_us);
125dml_get_pipe_attr_decl(refcyc_per_req_delivery_l_in_us);
126dml_get_pipe_attr_decl(refcyc_per_req_delivery_c_in_us);
127dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_l_in_us);
128dml_get_pipe_attr_decl(refcyc_per_req_delivery_pre_c_in_us);
129dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_in_us);
130dml_get_pipe_attr_decl(refcyc_per_cursor_req_delivery_pre_in_us);
131dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_l_in_us);
132dml_get_pipe_attr_decl(refcyc_per_meta_chunk_nom_c_in_us);
133dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_l_in_us);
134dml_get_pipe_attr_decl(refcyc_per_meta_chunk_vblank_c_in_us);
135dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_l_in_us);
136dml_get_pipe_attr_decl(refcyc_per_meta_chunk_flip_c_in_us);
137
138dml_get_pipe_attr_decl(vstartup);
139dml_get_pipe_attr_decl(vupdate_offset);
140dml_get_pipe_attr_decl(vupdate_width);
141dml_get_pipe_attr_decl(vready_offset);
142dml_get_pipe_attr_decl(vready_at_or_after_vsync);
143dml_get_pipe_attr_decl(min_dst_y_next_start);
144dml_get_pipe_attr_decl(vstartup_calculated);
145dml_get_pipe_attr_decl(subviewport_lines_needed_in_mall);
146
147double get_total_immediate_flip_bytes(
148 struct display_mode_lib *mode_lib,
149 const display_e2e_pipe_params_st *pipes,
150 unsigned int num_pipes);
151double get_total_immediate_flip_bw(
152 struct display_mode_lib *mode_lib,
153 const display_e2e_pipe_params_st *pipes,
154 unsigned int num_pipes);
155double get_total_prefetch_bw(
156 struct display_mode_lib *mode_lib,
157 const display_e2e_pipe_params_st *pipes,
158 unsigned int num_pipes);
159unsigned int dml_get_voltage_level(
160 struct display_mode_lib *mode_lib,
161 const display_e2e_pipe_params_st *pipes,
162 unsigned int num_pipes);
163
164unsigned int get_total_surface_size_in_mall_bytes(
165 struct display_mode_lib *mode_lib,
166 const display_e2e_pipe_params_st *pipes,
167 unsigned int num_pipes);
168
169bool get_is_phantom_pipe(struct display_mode_lib *mode_lib,
170 const display_e2e_pipe_params_st *pipes,
171 unsigned int num_pipes,
172 unsigned int pipe_idx);
173void PixelClockAdjustmentForProgressiveToInterlaceUnit(struct display_mode_lib *mode_lib);
174
175void Calculate256BBlockSizes(
176 enum source_format_class SourcePixelFormat,
177 enum dm_swizzle_mode SurfaceTiling,
178 unsigned int BytePerPixelY,
179 unsigned int BytePerPixelC,
180 unsigned int *BlockHeight256BytesY,
181 unsigned int *BlockHeight256BytesC,
182 unsigned int *BlockWidth256BytesY,
183 unsigned int *BlockWidth256BytesC);
184
185struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation {
186 unsigned int dummy_integer_array[2][DC__NUM_DPP__MAX];
187 double dummy_single_array[2][DC__NUM_DPP__MAX];
188 unsigned int dummy_long_array[2][DC__NUM_DPP__MAX];
189 double dummy_double_array[2][DC__NUM_DPP__MAX];
190 bool dummy_boolean_array[DC__NUM_DPP__MAX];
191 bool dummy_boolean;
192 bool dummy_boolean2;
193 enum output_encoder_class dummy_output_encoder_array[DC__NUM_DPP__MAX];
194 DmlPipe SurfaceParameters[DC__NUM_DPP__MAX];
195 bool dummy_boolean_array2[2][DC__NUM_DPP__MAX];
196 unsigned int ReorderBytes;
197 unsigned int VMDataOnlyReturnBW;
198 double HostVMInefficiencyFactor;
199 DmlPipe myPipe;
200 SOCParametersList mmSOCParameters;
201 double dummy_unit_vector[DC__NUM_DPP__MAX];
202 double dummy_single[2];
203 enum clock_change_support dummy_dramchange_support;
204 enum dm_fclock_change_support dummy_fclkchange_support;
205 bool dummy_USRRetrainingSupport;
206};
207
208struct dml32_ModeSupportAndSystemConfigurationFull {
209 unsigned int dummy_integer_array[22][DC__NUM_DPP__MAX];
210 double dummy_double_array[2][DC__NUM_DPP__MAX];
211 DmlPipe SurfParameters[DC__NUM_DPP__MAX];
212 double dummy_single[5];
213 double dummy_single2[5];
214 SOCParametersList mSOCParameters;
215 unsigned int MaximumSwathWidthSupportLuma;
216 unsigned int MaximumSwathWidthSupportChroma;
217 double DSTYAfterScaler[DC__NUM_DPP__MAX];
218 double DSTXAfterScaler[DC__NUM_DPP__MAX];
219 double MaxTotalVActiveRDBandwidth;
220 bool dummy_boolean_array[2][DC__NUM_DPP__MAX];
221 enum odm_combine_mode dummy_odm_mode[DC__NUM_DPP__MAX];
222 DmlPipe myPipe;
223 unsigned int dummy_integer[4];
224 unsigned int TotalNumberOfActiveOTG;
225 unsigned int TotalNumberOfActiveHDMIFRL;
226 unsigned int TotalNumberOfActiveDP2p0;
227 unsigned int TotalNumberOfActiveDP2p0Outputs;
228 unsigned int TotalDSCUnitsRequired;
229 unsigned int ReorderingBytes;
230 unsigned int TotalSlots;
231 unsigned int NumberOfDPPDSC;
232 unsigned int NumberOfDPPNoDSC;
233 unsigned int NextPrefetchModeState;
234 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage;
235 bool MPCCombineMethodAsPossible;
236 bool FullFrameMALLPStateMethod;
237 bool SubViewportMALLPStateMethod;
238 bool PhantomPipeMALLPStateMethod;
239 bool NoChroma;
240 bool TotalAvailablePipesSupportNoDSC;
241 bool TotalAvailablePipesSupportDSC;
242 enum odm_combine_mode ODMModeNoDSC;
243 enum odm_combine_mode ODMModeDSC;
244 double RequiredDISPCLKPerSurfaceNoDSC;
245 double RequiredDISPCLKPerSurfaceDSC;
246 double BWOfNonCombinedSurfaceOfMaximumBandwidth;
247 double VMDataOnlyReturnBWPerState;
248 double HostVMInefficiencyFactor;
249 bool dummy_boolean[2];
250};
251
252struct dummy_vars {
253 struct DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation
254 DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation;
255 struct dml32_ModeSupportAndSystemConfigurationFull dml32_ModeSupportAndSystemConfigurationFull;
256};
257
258struct vba_vars_st {
259 ip_params_st ip;
260 soc_bounding_box_st soc;
261
262 int maxMpcComb;
263 bool UseMaximumVStartup;
264
265 double WritebackDISPCLK;
266 double DPPCLKUsingSingleDPPLuma;
267 double DPPCLKUsingSingleDPPChroma;
268 double DISPCLKWithRamping;
269 double DISPCLKWithoutRamping;
270 double GlobalDPPCLK;
271 double DISPCLKWithRampingRoundedToDFSGranularity;
272 double DISPCLKWithoutRampingRoundedToDFSGranularity;
273 double MaxDispclkRoundedToDFSGranularity;
274 bool DCCEnabledAnyPlane;
275 double ReturnBandwidthToDCN;
276 unsigned int TotalActiveDPP;
277 unsigned int TotalDCCActiveDPP;
278 double UrgentRoundTripAndOutOfOrderLatency;
279 double StutterPeriod;
280 double FrameTimeForMinFullDETBufferingTime;
281 double AverageReadBandwidth;
282 double TotalRowReadBandwidth;
283 double PartOfBurstThatFitsInROB;
284 double StutterBurstTime;
285 unsigned int NextPrefetchMode;
286 double NextMaxVStartup;
287 double VBlankTime;
288 double SmallestVBlank;
289 enum dm_prefetch_modes AllowForPStateChangeOrStutterInVBlankFinal; // Mode Support only
290 double DCFCLKDeepSleepPerPlane[DC__NUM_DPP__MAX];
291 double EffectiveDETPlusLBLinesLuma;
292 double EffectiveDETPlusLBLinesChroma;
293 double UrgentLatencySupportUsLuma;
294 double UrgentLatencySupportUsChroma;
295 unsigned int DSCFormatFactor;
296
297 bool DummyPStateCheck;
298 bool DRAMClockChangeSupportsVActive;
299 bool PrefetchModeSupported;
300 bool PrefetchAndImmediateFlipSupported;
301 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank; // Mode Support only
302 double XFCRemoteSurfaceFlipDelay;
303 double TInitXFill;
304 double TslvChk;
305 double SrcActiveDrainRate;
306 bool ImmediateFlipSupported;
307 enum mpc_combine_affinity WhenToDoMPCCombine; // Mode Support only
308
309 bool PrefetchERROR;
310
311 unsigned int VStartupLines;
312 unsigned int ActiveDPPs;
313 unsigned int LBLatencyHidingSourceLinesY;
314 unsigned int LBLatencyHidingSourceLinesC;
315 double ActiveDRAMClockChangeLatencyMarginPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];// DML doesn't save active margin per state
316 double ActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX];
317 double CachedActiveDRAMClockChangeLatencyMargin[DC__NUM_DPP__MAX]; // Cache in dml_get_voltage_level for debug purposes only
318 double MinActiveDRAMClockChangeMargin;
319 double InitFillLevel;
320 double FinalFillMargin;
321 double FinalFillLevel;
322 double RemainingFillLevel;
323 double TFinalxFill;
324
325 //
326 // SOC Bounding Box Parameters
327 //
328 double SRExitTime;
329 double SREnterPlusExitTime;
330 double UrgentLatencyPixelDataOnly;
331 double UrgentLatencyPixelMixedWithVMData;
332 double UrgentLatencyVMDataOnly;
333 double UrgentLatency; // max of the above three
334 double USRRetrainingLatency;
335 double SMNLatency;
336 double FCLKChangeLatency;
337 unsigned int MALLAllocatedForDCNFinal;
338 double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
339 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
340 double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
341 double WritebackLatency;
342 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
343 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
344 double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyVMDataOnly; // Mode Support
345 double MaxAveragePercentOfIdealSDPPortBWDisplayCanUseInNormalSystemOperation; // Mode Support
346 double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperation; // Mode Support
347 double NumberOfChannels;
348 double DRAMChannelWidth;
349 double FabricDatapathToDCNDataReturn;
350 double ReturnBusWidth;
351 double Downspreading;
352 double DISPCLKDPPCLKDSCCLKDownSpreading;
353 double DISPCLKDPPCLKVCOSpeed;
354 double RoundTripPingLatencyCycles;
355 double UrgentOutOfOrderReturnPerChannel;
356 double UrgentOutOfOrderReturnPerChannelPixelDataOnly;
357 double UrgentOutOfOrderReturnPerChannelPixelMixedWithVMData;
358 double UrgentOutOfOrderReturnPerChannelVMDataOnly;
359 unsigned int VMMPageSize;
360 double DRAMClockChangeLatency;
361 double XFCBusTransportTime;
362 bool UseUrgentBurstBandwidth;
363 double XFCXBUFLatencyTolerance;
364
365 //
366 // IP Parameters
367 //
368 unsigned int ROBBufferSizeInKByte;
369 unsigned int DETBufferSizeInKByte[DC__NUM_DPP__MAX];
370 double DETBufferSizeInTime;
371 unsigned int DPPOutputBufferPixels;
372 unsigned int OPPOutputBufferLines;
373 unsigned int PixelChunkSizeInKByte;
374 double ReturnBW;
375 bool GPUVMEnable;
376 bool HostVMEnable;
377 unsigned int GPUVMMaxPageTableLevels;
378 unsigned int HostVMMaxPageTableLevels;
379 unsigned int HostVMCachedPageTableLevels;
380 unsigned int OverrideGPUVMPageTableLevels;
381 unsigned int OverrideHostVMPageTableLevels;
382 unsigned int MetaChunkSize;
383 unsigned int MinMetaChunkSizeBytes;
384 unsigned int WritebackChunkSize;
385 bool ODMCapability;
386 unsigned int NumberOfDSC;
387 unsigned int LineBufferSize;
388 unsigned int MaxLineBufferLines;
389 unsigned int WritebackInterfaceLumaBufferSize;
390 unsigned int WritebackInterfaceChromaBufferSize;
391 unsigned int WritebackChromaLineBufferWidth;
392 enum writeback_config WritebackConfiguration;
393 double MaxDCHUBToPSCLThroughput;
394 double MaxPSCLToLBThroughput;
395 unsigned int PTEBufferSizeInRequestsLuma;
396 unsigned int PTEBufferSizeInRequestsChroma;
397 double DISPCLKRampingMargin;
398 unsigned int MaxInterDCNTileRepeaters;
399 bool XFCSupported;
400 double XFCSlvChunkSize;
401 double XFCFillBWOverhead;
402 double XFCFillConstant;
403 double XFCTSlvVupdateOffset;
404 double XFCTSlvVupdateWidth;
405 double XFCTSlvVreadyOffset;
406 double DPPCLKDelaySubtotal;
407 double DPPCLKDelaySCL;
408 double DPPCLKDelaySCLLBOnly;
409 double DPPCLKDelayCNVCFormater;
410 double DPPCLKDelayCNVCCursor;
411 double DISPCLKDelaySubtotal;
412 bool ProgressiveToInterlaceUnitInOPP;
413 unsigned int CompressedBufferSegmentSizeInkByteFinal;
414 unsigned int CompbufReservedSpace64B;
415 unsigned int CompbufReservedSpaceZs;
416 unsigned int LineBufferSizeFinal;
417 unsigned int MaximumPixelsPerLinePerDSCUnit;
418 unsigned int AlphaPixelChunkSizeInKByte;
419 double MinPixelChunkSizeBytes;
420 unsigned int DCCMetaBufferSizeBytes;
421 // Pipe/Plane Parameters
422
423 /** @VoltageLevel:
424 * Every ASIC has a fixed number of DPM states, and some devices might
425 * have some particular voltage configuration that does not map
426 * directly to the DPM states. This field tells how many states the
427 * target device supports; even though this field combines the DPM and
428 * special SOC voltages, it mostly matches the total number of DPM
429 * states.
430 */
431 int VoltageLevel;
432 double FabricClock;
433 double DRAMSpeed;
434 double DISPCLK;
435 double SOCCLK;
436 double DCFCLK;
437 unsigned int MaxTotalDETInKByte;
438 unsigned int MinCompressedBufferSizeInKByte;
439 unsigned int NumberOfActiveSurfaces;
440 bool ViewportStationary[DC__NUM_DPP__MAX];
441 unsigned int RefreshRate[DC__NUM_DPP__MAX];
442 double OutputBPP[DC__NUM_DPP__MAX];
443 unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
444 bool SynchronizeTimingsFinal;
445 bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
446 bool ForceOneRowForFrame[DC__NUM_DPP__MAX];
447 unsigned int ViewportXStartY[DC__NUM_DPP__MAX];
448 unsigned int ViewportXStartC[DC__NUM_DPP__MAX];
449 enum dm_rotation_angle SourceRotation[DC__NUM_DPP__MAX];
450 bool DRRDisplay[DC__NUM_DPP__MAX];
451 bool PteBufferMode[DC__NUM_DPP__MAX];
452 enum dm_output_type OutputType[DC__NUM_DPP__MAX];
453 enum dm_output_rate OutputRate[DC__NUM_DPP__MAX];
454
455 unsigned int NumberOfActivePlanes;
456 unsigned int NumberOfDSCSlices[DC__NUM_DPP__MAX];
457 unsigned int ViewportWidth[DC__NUM_DPP__MAX];
458 unsigned int ViewportHeight[DC__NUM_DPP__MAX];
459 unsigned int ViewportYStartY[DC__NUM_DPP__MAX];
460 unsigned int ViewportYStartC[DC__NUM_DPP__MAX];
461 unsigned int PitchY[DC__NUM_DPP__MAX];
462 unsigned int PitchC[DC__NUM_DPP__MAX];
463 double HRatio[DC__NUM_DPP__MAX];
464 double VRatio[DC__NUM_DPP__MAX];
465 unsigned int htaps[DC__NUM_DPP__MAX];
466 unsigned int vtaps[DC__NUM_DPP__MAX];
467 unsigned int HTAPsChroma[DC__NUM_DPP__MAX];
468 unsigned int VTAPsChroma[DC__NUM_DPP__MAX];
469 unsigned int HTotal[DC__NUM_DPP__MAX];
470 unsigned int VTotal[DC__NUM_DPP__MAX];
471 unsigned int VTotal_Max[DC__NUM_DPP__MAX];
472 unsigned int VTotal_Min[DC__NUM_DPP__MAX];
473 int DPPPerPlane[DC__NUM_DPP__MAX];
474 double PixelClock[DC__NUM_DPP__MAX];
475 double PixelClockBackEnd[DC__NUM_DPP__MAX];
476 bool DCCEnable[DC__NUM_DPP__MAX];
477 bool FECEnable[DC__NUM_DPP__MAX];
478 unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
479 unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
480 enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
481 enum source_format_class SourcePixelFormat[DC__NUM_DPP__MAX];
482 bool WritebackEnable[DC__NUM_DPP__MAX];
483 unsigned int ActiveWritebacksPerPlane[DC__NUM_DPP__MAX];
484 double WritebackDestinationWidth[DC__NUM_DPP__MAX];
485 double WritebackDestinationHeight[DC__NUM_DPP__MAX];
486 double WritebackSourceHeight[DC__NUM_DPP__MAX];
487 enum source_format_class WritebackPixelFormat[DC__NUM_DPP__MAX];
488 unsigned int WritebackLumaHTaps[DC__NUM_DPP__MAX];
489 unsigned int WritebackLumaVTaps[DC__NUM_DPP__MAX];
490 unsigned int WritebackChromaHTaps[DC__NUM_DPP__MAX];
491 unsigned int WritebackChromaVTaps[DC__NUM_DPP__MAX];
492 double WritebackHRatio[DC__NUM_DPP__MAX];
493 double WritebackVRatio[DC__NUM_DPP__MAX];
494 unsigned int HActive[DC__NUM_DPP__MAX];
495 unsigned int VActive[DC__NUM_DPP__MAX];
496 bool Interlace[DC__NUM_DPP__MAX];
497 enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
498 unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
499 bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
500 int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
501 unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
502 double DCCRate[DC__NUM_DPP__MAX];
503 double AverageDCCCompressionRate;
504 enum odm_combine_mode ODMCombineEnabled[DC__NUM_DPP__MAX];
505 double OutputBpp[DC__NUM_DPP__MAX];
506 bool DSCEnabled[DC__NUM_DPP__MAX];
507 unsigned int DSCInputBitPerComponent[DC__NUM_DPP__MAX];
508 enum output_format_class OutputFormat[DC__NUM_DPP__MAX];
509 enum output_encoder_class Output[DC__NUM_DPP__MAX];
510 bool skip_dio_check[DC__NUM_DPP__MAX];
511 unsigned int BlendingAndTiming[DC__NUM_DPP__MAX];
512 bool SynchronizedVBlank;
513 unsigned int NumberOfCursors[DC__NUM_DPP__MAX];
514 unsigned int CursorWidth[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
515 unsigned int CursorBPP[DC__NUM_DPP__MAX][DC__NUM_CURSOR__MAX];
516 bool XFCEnabled[DC__NUM_DPP__MAX];
517 bool ScalerEnabled[DC__NUM_DPP__MAX];
518 unsigned int VBlankNom[DC__NUM_DPP__MAX];
519 bool DisableUnboundRequestIfCompBufReservedSpaceNeedAdjustment;
520
521 // Intermediates/Informational
522 bool ImmediateFlipSupport;
523 unsigned int DETBufferSizeY[DC__NUM_DPP__MAX];
524 unsigned int DETBufferSizeC[DC__NUM_DPP__MAX];
525 unsigned int SwathHeightY[DC__NUM_DPP__MAX];
526 unsigned int SwathHeightC[DC__NUM_DPP__MAX];
527 unsigned int LBBitPerPixel[DC__NUM_DPP__MAX];
528 double LastPixelOfLineExtraWatermark;
529 double TotalDataReadBandwidth;
530 unsigned int TotalActiveWriteback;
531 unsigned int EffectiveLBLatencyHidingSourceLinesLuma;
532 unsigned int EffectiveLBLatencyHidingSourceLinesChroma;
533 double BandwidthAvailableForImmediateFlip;
534 unsigned int PrefetchMode[DC__VOLTAGE_STATES][2];
535 unsigned int PrefetchModePerState[DC__VOLTAGE_STATES][2];
536 unsigned int MinPrefetchMode;
537 unsigned int MaxPrefetchMode;
538 bool AnyLinesForVMOrRowTooLarge;
539 double MaxVStartup;
540 bool IgnoreViewportPositioning;
541 bool ErrorResult[DC__NUM_DPP__MAX];
542 //
543 // Calculated dml_ml->vba.Outputs
544 //
545 double DCFCLKDeepSleep;
546 double UrgentWatermark;
547 double UrgentExtraLatency;
548 double WritebackUrgentWatermark;
549 double StutterExitWatermark;
550 double StutterEnterPlusExitWatermark;
551 double DRAMClockChangeWatermark;
552 double WritebackDRAMClockChangeWatermark;
553 double StutterEfficiency;
554 double StutterEfficiencyNotIncludingVBlank;
555 double NonUrgentLatencyTolerance;
556 double MinActiveDRAMClockChangeLatencySupported;
557 double Z8StutterEfficiencyBestCase;
558 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
559 double Z8StutterEfficiencyNotIncludingVBlankBestCase;
560 double StutterPeriodBestCase;
561 Watermarks Watermark;
562 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
563 unsigned int CompBufReservedSpaceKBytes;
564 unsigned int CompBufReservedSpace64B;
565 unsigned int CompBufReservedSpaceZs;
566 bool CompBufReservedSpaceNeedAdjustment;
567
568 // These are the clocks calcuated by the library but they are not actually
569 // used explicitly. They are fetched by tests and then possibly used. The
570 // ultimate values to use are the ones specified by the parameters to DML
571 double DISPCLK_calculated;
572 double DPPCLK_calculated[DC__NUM_DPP__MAX];
573
574 bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
575
576 bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
577 bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
578 unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
579 double VUpdateWidthPix[DC__NUM_DPP__MAX];
580 double VReadyOffsetPix[DC__NUM_DPP__MAX];
581
582 unsigned int TotImmediateFlipBytes;
583 double TCalc;
584
585 display_e2e_pipe_params_st cache_pipes[DC__NUM_DPP__MAX];
586 unsigned int cache_num_pipes;
587 unsigned int pipe_plane[DC__NUM_DPP__MAX];
588
589 /* vba mode support */
590 /*inputs*/
591 bool SupportGFX7CompatibleTilingIn32bppAnd64bpp;
592 double MaxHSCLRatio;
593 double MaxVSCLRatio;
594 unsigned int MaxNumWriteback;
595 bool WritebackLumaAndChromaScalingSupported;
596 bool Cursor64BppSupport;
597 double DCFCLKPerState[DC__VOLTAGE_STATES];
598 double DCFCLKState[DC__VOLTAGE_STATES][2];
599 double FabricClockPerState[DC__VOLTAGE_STATES];
600 double SOCCLKPerState[DC__VOLTAGE_STATES];
601 double PHYCLKPerState[DC__VOLTAGE_STATES];
602 double DTBCLKPerState[DC__VOLTAGE_STATES];
603 double MaxDppclk[DC__VOLTAGE_STATES];
604 double MaxDSCCLK[DC__VOLTAGE_STATES];
605 double DRAMSpeedPerState[DC__VOLTAGE_STATES];
606 double MaxDispclk[DC__VOLTAGE_STATES];
607 int VoltageOverrideLevel;
608 double PHYCLKD32PerState[DC__VOLTAGE_STATES];
609
610 /*outputs*/
611 bool ScaleRatioAndTapsSupport;
612 bool SourceFormatPixelAndScanSupport;
613 double TotalBandwidthConsumedGBytePerSecond;
614 bool DCCEnabledInAnyPlane;
615 bool WritebackLatencySupport;
616 bool WritebackModeSupport;
617 bool Writeback10bpc420Supported;
618 bool BandwidthSupport[DC__VOLTAGE_STATES];
619 unsigned int TotalNumberOfActiveWriteback;
620 double CriticalPoint;
621 double ReturnBWToDCNPerState;
622 bool IsErrorResult[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
623 bool prefetch_vm_bw_valid;
624 bool prefetch_row_bw_valid;
625 bool NumberOfOTGSupport;
626 bool NonsupportedDSCInputBPC;
627 bool WritebackScaleRatioAndTapsSupport;
628 bool CursorSupport;
629 bool PitchSupport;
630 enum dm_validation_status ValidationStatus[DC__VOLTAGE_STATES];
631
632 /* Mode Support Reason */
633 bool P2IWith420;
634 bool DSCOnlyIfNecessaryWithBPP;
635 bool DSC422NativeNotSupported;
636 bool LinkRateDoesNotMatchDPVersion;
637 bool LinkRateForMultistreamNotIndicated;
638 bool BPPForMultistreamNotIndicated;
639 bool MultistreamWithHDMIOreDP;
640 bool MSOOrODMSplitWithNonDPLink;
641 bool NotEnoughLanesForMSO;
642 bool ViewportExceedsSurface;
643
644 bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified;
645 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe;
646 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen;
647 bool InvalidCombinationOfMALLUseForPState;
648
649 enum dm_output_link_dp_rate OutputLinkDPRate[DC__NUM_DPP__MAX];
650 double PrefetchLinesYThisState[DC__NUM_DPP__MAX];
651 double PrefetchLinesCThisState[DC__NUM_DPP__MAX];
652 double meta_row_bandwidth_this_state[DC__NUM_DPP__MAX];
653 double dpte_row_bandwidth_this_state[DC__NUM_DPP__MAX];
654 double DPTEBytesPerRowThisState[DC__NUM_DPP__MAX];
655 double PDEAndMetaPTEBytesPerFrameThisState[DC__NUM_DPP__MAX];
656 double MetaRowBytesThisState[DC__NUM_DPP__MAX];
657 bool use_one_row_for_frame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
658 bool use_one_row_for_frame_flip[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
659 bool use_one_row_for_frame_this_state[DC__NUM_DPP__MAX];
660 bool use_one_row_for_frame_flip_this_state[DC__NUM_DPP__MAX];
661
662 unsigned int OutputTypeAndRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
663 double RequiredDISPCLKPerSurface[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
664 unsigned int MacroTileHeightY[DC__NUM_DPP__MAX];
665 unsigned int MacroTileHeightC[DC__NUM_DPP__MAX];
666 unsigned int MacroTileWidthY[DC__NUM_DPP__MAX];
667 unsigned int MacroTileWidthC[DC__NUM_DPP__MAX];
668 bool ImmediateFlipRequiredFinal;
669 bool DCCProgrammingAssumesScanDirectionUnknownFinal;
670 bool EnoughWritebackUnits;
671 bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
672 bool NumberOfDP2p0Support;
673 unsigned int MaxNumDP2p0Streams;
674 unsigned int MaxNumDP2p0Outputs;
675 enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
676 enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
677 double WritebackLineBufferLumaBufferSize;
678 double WritebackLineBufferChromaBufferSize;
679 double WritebackMinHSCLRatio;
680 double WritebackMinVSCLRatio;
681 double WritebackMaxHSCLRatio;
682 double WritebackMaxVSCLRatio;
683 double WritebackMaxHSCLTaps;
684 double WritebackMaxVSCLTaps;
685 unsigned int MaxNumDPP;
686 unsigned int MaxNumOTG;
687 double CursorBufferSize;
688 double CursorChunkSize;
689 unsigned int Mode;
690 double OutputLinkDPLanes[DC__NUM_DPP__MAX];
691 double ForcedOutputLinkBPP[DC__NUM_DPP__MAX]; // Mode Support only
692 double ImmediateFlipBW[DC__NUM_DPP__MAX];
693 double MaxMaxVStartup[DC__VOLTAGE_STATES][2];
694
695 double WritebackLumaVExtra;
696 double WritebackChromaVExtra;
697 double WritebackRequiredDISPCLK;
698 double MaximumSwathWidthSupport;
699 double MaximumSwathWidthInDETBuffer;
700 double MaximumSwathWidthInLineBuffer;
701 double MaxDispclkRoundedDownToDFSGranularity;
702 double MaxDppclkRoundedDownToDFSGranularity;
703 double PlaneRequiredDISPCLKWithoutODMCombine;
704 double PlaneRequiredDISPCLKWithODMCombine;
705 double PlaneRequiredDISPCLK;
706 double TotalNumberOfActiveOTG;
707 double FECOverhead;
708 double EffectiveFECOverhead;
709 double Outbpp;
710 unsigned int OutbppDSC;
711 double TotalDSCUnitsRequired;
712 double bpp;
713 unsigned int slices;
714 double SwathWidthGranularityY;
715 double RoundedUpMaxSwathSizeBytesY;
716 double SwathWidthGranularityC;
717 double RoundedUpMaxSwathSizeBytesC;
718 double EffectiveDETLBLinesLuma;
719 double EffectiveDETLBLinesChroma;
720 double ProjectedDCFCLKDeepSleep[DC__VOLTAGE_STATES][2];
721 double PDEAndMetaPTEBytesPerFrameY;
722 double PDEAndMetaPTEBytesPerFrameC;
723 unsigned int MetaRowBytesY;
724 unsigned int MetaRowBytesC;
725 unsigned int DPTEBytesPerRowC;
726 unsigned int DPTEBytesPerRowY;
727 double ExtraLatency;
728 double TimeCalc;
729 double TWait;
730 double MaximumReadBandwidthWithPrefetch;
731 double MaximumReadBandwidthWithoutPrefetch;
732 double total_dcn_read_bw_with_flip;
733 double total_dcn_read_bw_with_flip_no_urgent_burst;
734 double FractionOfUrgentBandwidth;
735 double FractionOfUrgentBandwidthImmediateFlip; // Mode Support debugging output
736
737 /* ms locals */
738 double IdealSDPPortBandwidthPerState[DC__VOLTAGE_STATES][2];
739 unsigned int NoOfDPP[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
740 int NoOfDPPThisState[DC__NUM_DPP__MAX];
741 enum odm_combine_mode ODMCombineEnablePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
742 double SwathWidthYThisState[DC__NUM_DPP__MAX];
743 unsigned int SwathHeightCPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
744 unsigned int SwathHeightYThisState[DC__NUM_DPP__MAX];
745 unsigned int SwathHeightCThisState[DC__NUM_DPP__MAX];
746 double VRatioPreY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
747 double VRatioPreC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
748 double RequiredPrefetchPixelDataBWLuma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
749 double RequiredPrefetchPixelDataBWChroma[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
750 double RequiredDPPCLK[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
751 double RequiredDPPCLKThisState[DC__NUM_DPP__MAX];
752 bool PTEBufferSizeNotExceededY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
753 bool PTEBufferSizeNotExceededC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
754 bool BandwidthWithoutPrefetchSupported[DC__VOLTAGE_STATES][2];
755 bool PrefetchSupported[DC__VOLTAGE_STATES][2];
756 bool VRatioInPrefetchSupported[DC__VOLTAGE_STATES][2];
757 double RequiredDISPCLK[DC__VOLTAGE_STATES][2];
758 bool DISPCLK_DPPCLK_Support[DC__VOLTAGE_STATES][2];
759 bool TotalAvailablePipesSupport[DC__VOLTAGE_STATES][2];
760 unsigned int TotalNumberOfActiveDPP[DC__VOLTAGE_STATES][2];
761 unsigned int TotalNumberOfDCCActiveDPP[DC__VOLTAGE_STATES][2];
762 bool ModeSupport[DC__VOLTAGE_STATES][2];
763 double ReturnBWPerState[DC__VOLTAGE_STATES][2];
764 bool DIOSupport[DC__VOLTAGE_STATES];
765 bool NotEnoughDSCUnits[DC__VOLTAGE_STATES];
766 bool DSCCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
767 bool DTBCLKRequiredMoreThanSupported[DC__VOLTAGE_STATES];
768 double UrgentRoundTripAndOutOfOrderLatencyPerState[DC__VOLTAGE_STATES];
769 bool ROBSupport[DC__VOLTAGE_STATES][2];
770 //based on rev 99: Dim DCCMetaBufferSizeSupport(NumberOfStates, 1) As Boolean
771 bool DCCMetaBufferSizeSupport[DC__VOLTAGE_STATES][2];
772 bool PTEBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
773 bool TotalVerticalActiveBandwidthSupport[DC__VOLTAGE_STATES][2];
774 double MaxTotalVerticalActiveAvailableBandwidth[DC__VOLTAGE_STATES][2];
775 double PrefetchBW[DC__NUM_DPP__MAX];
776 double PDEAndMetaPTEBytesPerFrame[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
777 double MetaRowBytes[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
778 double DPTEBytesPerRow[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
779 double PrefetchLinesY[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
780 double PrefetchLinesC[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
781 unsigned int MaxNumSwY[DC__NUM_DPP__MAX];
782 unsigned int MaxNumSwC[DC__NUM_DPP__MAX];
783 double PrefillY[DC__NUM_DPP__MAX];
784 double PrefillC[DC__NUM_DPP__MAX];
785 double LineTimesForPrefetch[DC__NUM_DPP__MAX];
786 double LinesForMetaPTE[DC__NUM_DPP__MAX];
787 double LinesForMetaAndDPTERow[DC__NUM_DPP__MAX];
788 double MinDPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
789 double SwathWidthYSingleDPP[DC__NUM_DPP__MAX];
790 double BytePerPixelInDETY[DC__NUM_DPP__MAX];
791 double BytePerPixelInDETC[DC__NUM_DPP__MAX];
792 bool RequiresDSC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
793 unsigned int NumberOfDSCSlice[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
794 double RequiresFEC[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
795 double OutputBppPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
796 double DSCDelayPerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
797 bool ViewportSizeSupport[DC__VOLTAGE_STATES][2];
798 unsigned int Read256BlockHeightY[DC__NUM_DPP__MAX];
799 unsigned int Read256BlockWidthY[DC__NUM_DPP__MAX];
800 unsigned int Read256BlockHeightC[DC__NUM_DPP__MAX];
801 unsigned int Read256BlockWidthC[DC__NUM_DPP__MAX];
802 double MaxSwathHeightY[DC__NUM_DPP__MAX];
803 double MaxSwathHeightC[DC__NUM_DPP__MAX];
804 double MinSwathHeightY[DC__NUM_DPP__MAX];
805 double MinSwathHeightC[DC__NUM_DPP__MAX];
806 double ReadBandwidthLuma[DC__NUM_DPP__MAX];
807 double ReadBandwidthChroma[DC__NUM_DPP__MAX];
808 double ReadBandwidth[DC__NUM_DPP__MAX];
809 double WriteBandwidth[DC__NUM_DPP__MAX];
810 double PSCL_FACTOR[DC__NUM_DPP__MAX];
811 double PSCL_FACTOR_CHROMA[DC__NUM_DPP__MAX];
812 double MaximumVStartup[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
813 double AlignedDCCMetaPitch[DC__NUM_DPP__MAX];
814 double AlignedYPitch[DC__NUM_DPP__MAX];
815 double AlignedCPitch[DC__NUM_DPP__MAX];
816 double MaximumSwathWidth[DC__NUM_DPP__MAX];
817 double cursor_bw[DC__NUM_DPP__MAX];
818 double cursor_bw_pre[DC__NUM_DPP__MAX];
819 double Tno_bw[DC__NUM_DPP__MAX];
820 double prefetch_vmrow_bw[DC__NUM_DPP__MAX];
821 double DestinationLinesToRequestVMInImmediateFlip[DC__NUM_DPP__MAX];
822 double DestinationLinesToRequestRowInImmediateFlip[DC__NUM_DPP__MAX];
823 double final_flip_bw[DC__NUM_DPP__MAX];
824 bool ImmediateFlipSupportedForState[DC__VOLTAGE_STATES][2];
825 double WritebackDelay[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
826 unsigned int vm_group_bytes[DC__NUM_DPP__MAX];
827 unsigned int dpte_group_bytes[DC__NUM_DPP__MAX];
828 unsigned int dpte_row_height[DC__NUM_DPP__MAX];
829 unsigned int meta_req_height[DC__NUM_DPP__MAX];
830 unsigned int meta_req_width[DC__NUM_DPP__MAX];
831 unsigned int meta_row_height[DC__NUM_DPP__MAX];
832 unsigned int meta_row_width[DC__NUM_DPP__MAX];
833 unsigned int dpte_row_height_chroma[DC__NUM_DPP__MAX];
834 unsigned int meta_req_height_chroma[DC__NUM_DPP__MAX];
835 unsigned int meta_req_width_chroma[DC__NUM_DPP__MAX];
836 unsigned int meta_row_height_chroma[DC__NUM_DPP__MAX];
837 unsigned int meta_row_width_chroma[DC__NUM_DPP__MAX];
838 bool ImmediateFlipSupportedForPipe[DC__NUM_DPP__MAX];
839 double meta_row_bw[DC__NUM_DPP__MAX];
840 double dpte_row_bw[DC__NUM_DPP__MAX];
841 double DisplayPipeLineDeliveryTimeLuma[DC__NUM_DPP__MAX]; // WM
842 double DisplayPipeLineDeliveryTimeChroma[DC__NUM_DPP__MAX]; // WM
843 double DisplayPipeRequestDeliveryTimeLuma[DC__NUM_DPP__MAX];
844 double DisplayPipeRequestDeliveryTimeChroma[DC__NUM_DPP__MAX];
845 enum clock_change_support DRAMClockChangeSupport[DC__VOLTAGE_STATES][2];
846 double UrgentBurstFactorCursor[DC__NUM_DPP__MAX];
847 double UrgentBurstFactorCursorPre[DC__NUM_DPP__MAX];
848 double UrgentBurstFactorLuma[DC__NUM_DPP__MAX];
849 double UrgentBurstFactorLumaPre[DC__NUM_DPP__MAX];
850 double UrgentBurstFactorChroma[DC__NUM_DPP__MAX];
851 double UrgentBurstFactorChromaPre[DC__NUM_DPP__MAX];
852
853
854 bool MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
855 double SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
856 double MaximumSwathWidthInLineBufferLuma;
857 double MaximumSwathWidthInLineBufferChroma;
858 double MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
859 double MaximumSwathWidthChroma[DC__NUM_DPP__MAX];
860 enum odm_combine_mode odm_combine_dummy[DC__NUM_DPP__MAX];
861 double dummy1[DC__NUM_DPP__MAX];
862 double dummy2[DC__NUM_DPP__MAX];
863 unsigned int dummy3[DC__NUM_DPP__MAX];
864 unsigned int dummy4[DC__NUM_DPP__MAX];
865 double dummy5;
866 double dummy6;
867 double dummy7[DC__NUM_DPP__MAX];
868 double dummy8[DC__NUM_DPP__MAX];
869 double dummy13[DC__NUM_DPP__MAX];
870 double dummy_double_array[2][DC__NUM_DPP__MAX];
871 unsigned int dummyinteger3[DC__NUM_DPP__MAX];
872 unsigned int dummyinteger4[DC__NUM_DPP__MAX];
873 unsigned int dummyinteger5;
874 unsigned int dummyinteger6;
875 unsigned int dummyinteger7;
876 unsigned int dummyinteger8;
877 unsigned int dummyinteger9;
878 unsigned int dummyinteger10;
879 unsigned int dummyinteger11;
880 unsigned int dummy_integer_array[8][DC__NUM_DPP__MAX];
881
882 bool dummysinglestring;
883 bool SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
884 double PlaneRequiredDISPCLKWithODMCombine2To1;
885 double PlaneRequiredDISPCLKWithODMCombine4To1;
886 unsigned int TotalNumberOfSingleDPPPlanes[DC__VOLTAGE_STATES][2];
887 bool LinkDSCEnable;
888 bool ODMCombine4To1SupportCheckOK[DC__VOLTAGE_STATES];
889 enum odm_combine_mode ODMCombineEnableThisState[DC__NUM_DPP__MAX];
890 double SwathWidthCThisState[DC__NUM_DPP__MAX];
891 bool ViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
892 double AlignedDCCMetaPitchY[DC__NUM_DPP__MAX];
893 double AlignedDCCMetaPitchC[DC__NUM_DPP__MAX];
894
895 unsigned int NotEnoughUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
896 unsigned int NotEnoughUrgentLatencyHidingPre;
897 int PTEBufferSizeInRequestsForLuma;
898 int PTEBufferSizeInRequestsForChroma;
899
900 // Missing from VBA
901 int dpte_group_bytes_chroma;
902 unsigned int vm_group_bytes_chroma;
903 double dst_x_after_scaler;
904 double dst_y_after_scaler;
905 unsigned int VStartupRequiredWhenNotEnoughTimeForDynamicMetadata;
906
907 /* perf locals*/
908 double PrefetchBandwidth[DC__NUM_DPP__MAX];
909 double VInitPreFillY[DC__NUM_DPP__MAX];
910 double VInitPreFillC[DC__NUM_DPP__MAX];
911 unsigned int MaxNumSwathY[DC__NUM_DPP__MAX];
912 unsigned int MaxNumSwathC[DC__NUM_DPP__MAX];
913 unsigned int VStartup[DC__NUM_DPP__MAX];
914 double DSTYAfterScaler[DC__NUM_DPP__MAX];
915 double DSTXAfterScaler[DC__NUM_DPP__MAX];
916 bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
917 bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
918 double VRatioPrefetchY[DC__NUM_DPP__MAX];
919 double VRatioPrefetchC[DC__NUM_DPP__MAX];
920 double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
921 double DestinationLinesToRequestVMInVBlank[DC__NUM_DPP__MAX];
922 double DestinationLinesToRequestRowInVBlank[DC__NUM_DPP__MAX];
923 double MinTTUVBlank[DC__NUM_DPP__MAX];
924 double BytePerPixelDETY[DC__NUM_DPP__MAX];
925 double BytePerPixelDETC[DC__NUM_DPP__MAX];
926 double SwathWidthY[DC__NUM_DPP__MAX];
927 double SwathWidthSingleDPPY[DC__NUM_DPP__MAX];
928 double CursorRequestDeliveryTime[DC__NUM_DPP__MAX];
929 double CursorRequestDeliveryTimePrefetch[DC__NUM_DPP__MAX];
930 double ReadBandwidthPlaneLuma[DC__NUM_DPP__MAX];
931 double ReadBandwidthPlaneChroma[DC__NUM_DPP__MAX];
932 double DisplayPipeLineDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
933 double DisplayPipeLineDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
934 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DC__NUM_DPP__MAX];
935 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DC__NUM_DPP__MAX];
936 double PixelPTEBytesPerRow[DC__NUM_DPP__MAX];
937 double PDEAndMetaPTEBytesFrame[DC__NUM_DPP__MAX];
938 double MetaRowByte[DC__NUM_DPP__MAX];
939 double PrefetchSourceLinesY[DC__NUM_DPP__MAX];
940 double RequiredPrefetchPixDataBWLuma[DC__NUM_DPP__MAX];
941 double RequiredPrefetchPixDataBWChroma[DC__NUM_DPP__MAX];
942 double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
943 double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
944 double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
945 double DSCCLK_calculated[DC__NUM_DPP__MAX];
946 unsigned int DSCDelay[DC__NUM_DPP__MAX];
947 unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
948 double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
949 double DPPCLK[DC__NUM_DPP__MAX];
950 unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
951 unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
952 unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
953 double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
954 unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
955 unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
956 unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
957 unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
958 double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
959 double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
960 double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
961 double XFCTransferDelay[DC__NUM_DPP__MAX];
962 double XFCPrechargeDelay[DC__NUM_DPP__MAX];
963 double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
964 double XFCPrefetchMargin[DC__NUM_DPP__MAX];
965 unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
966 unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
967 double FullDETBufferingTimeY[DC__NUM_DPP__MAX]; // WM
968 double FullDETBufferingTimeC[DC__NUM_DPP__MAX]; // WM
969 double DST_Y_PER_PTE_ROW_NOM_L[DC__NUM_DPP__MAX];
970 double DST_Y_PER_PTE_ROW_NOM_C[DC__NUM_DPP__MAX];
971 double DST_Y_PER_META_ROW_NOM_L[DC__NUM_DPP__MAX];
972 double TimePerMetaChunkNominal[DC__NUM_DPP__MAX];
973 double TimePerMetaChunkVBlank[DC__NUM_DPP__MAX];
974 double TimePerMetaChunkFlip[DC__NUM_DPP__MAX];
975 unsigned int swath_width_luma_ub[DC__NUM_DPP__MAX];
976 unsigned int swath_width_chroma_ub[DC__NUM_DPP__MAX];
977 unsigned int PixelPTEReqWidthY[DC__NUM_DPP__MAX];
978 unsigned int PixelPTEReqHeightY[DC__NUM_DPP__MAX];
979 unsigned int PTERequestSizeY[DC__NUM_DPP__MAX];
980 unsigned int PixelPTEReqWidthC[DC__NUM_DPP__MAX];
981 unsigned int PixelPTEReqHeightC[DC__NUM_DPP__MAX];
982 unsigned int PTERequestSizeC[DC__NUM_DPP__MAX];
983 double time_per_pte_group_nom_luma[DC__NUM_DPP__MAX];
984 double time_per_pte_group_nom_chroma[DC__NUM_DPP__MAX];
985 double time_per_pte_group_vblank_luma[DC__NUM_DPP__MAX];
986 double time_per_pte_group_vblank_chroma[DC__NUM_DPP__MAX];
987 double time_per_pte_group_flip_luma[DC__NUM_DPP__MAX];
988 double time_per_pte_group_flip_chroma[DC__NUM_DPP__MAX];
989 double TimePerVMGroupVBlank[DC__NUM_DPP__MAX];
990 double TimePerVMGroupFlip[DC__NUM_DPP__MAX];
991 double TimePerVMRequestVBlank[DC__NUM_DPP__MAX];
992 double TimePerVMRequestFlip[DC__NUM_DPP__MAX];
993 unsigned int dpde0_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
994 unsigned int meta_pte_bytes_per_frame_ub_l[DC__NUM_DPP__MAX];
995 unsigned int dpde0_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
996 unsigned int meta_pte_bytes_per_frame_ub_c[DC__NUM_DPP__MAX];
997 double LinesToFinishSwathTransferStutterCriticalPlane;
998 unsigned int BytePerPixelYCriticalPlane;
999 double SwathWidthYCriticalPlane;
1000 double LinesInDETY[DC__NUM_DPP__MAX];
1001 double LinesInDETYRoundedDownToSwath[DC__NUM_DPP__MAX];
1002
1003 double SwathWidthSingleDPPC[DC__NUM_DPP__MAX];
1004 double SwathWidthC[DC__NUM_DPP__MAX];
1005 unsigned int BytePerPixelY[DC__NUM_DPP__MAX];
1006 unsigned int BytePerPixelC[DC__NUM_DPP__MAX];
1007 unsigned int dummyinteger1;
1008 unsigned int dummyinteger2;
1009 double FinalDRAMClockChangeLatency;
1010 double Tdmdl_vm[DC__NUM_DPP__MAX];
1011 double Tdmdl[DC__NUM_DPP__MAX];
1012 double TSetup[DC__NUM_DPP__MAX];
1013 unsigned int ThisVStartup;
1014 bool WritebackAllowDRAMClockChangeEndPosition[DC__NUM_DPP__MAX];
1015 double DST_Y_PER_META_ROW_NOM_C[DC__NUM_DPP__MAX];
1016 double TimePerChromaMetaChunkNominal[DC__NUM_DPP__MAX];
1017 double TimePerChromaMetaChunkVBlank[DC__NUM_DPP__MAX];
1018 double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
1019 unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
1020 unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
1021 double VStartupMargin;
1022 bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
1023
1024 /* Missing from VBA */
1025 unsigned int MaximumMaxVStartupLines;
1026 double FabricAndDRAMBandwidth;
1027 double LinesInDETLuma;
1028 double LinesInDETChroma;
1029 unsigned int ImmediateFlipBytes[DC__NUM_DPP__MAX];
1030 unsigned int LinesInDETC[DC__NUM_DPP__MAX];
1031 unsigned int LinesInDETCRoundedDownToSwath[DC__NUM_DPP__MAX];
1032 double UrgentLatencySupportUsPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1033 double UrgentLatencySupportUs[DC__NUM_DPP__MAX];
1034 double FabricAndDRAMBandwidthPerState[DC__VOLTAGE_STATES];
1035 bool UrgentLatencySupport[DC__VOLTAGE_STATES][2];
1036 unsigned int SwathWidthYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1037 unsigned int SwathHeightYPerState[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1038 double qual_row_bw[DC__NUM_DPP__MAX];
1039 double prefetch_row_bw[DC__NUM_DPP__MAX];
1040 double prefetch_vm_bw[DC__NUM_DPP__MAX];
1041
1042 double PTEGroupSize;
1043 unsigned int PDEProcessingBufIn64KBReqs;
1044
1045 double MaxTotalVActiveRDBandwidth;
1046 bool DoUrgentLatencyAdjustment;
1047 double UrgentLatencyAdjustmentFabricClockComponent;
1048 double UrgentLatencyAdjustmentFabricClockReference;
1049 double MinUrgentLatencySupportUs;
1050 double MinFullDETBufferingTime;
1051 double AverageReadBandwidthGBytePerSecond;
1052 bool FirstMainPlane;
1053 bool NotEnoughDETSwathFillLatencyHiding;
1054
1055 unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
1056 unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
1057 double HRatioChroma[DC__NUM_DPP__MAX];
1058 double VRatioChroma[DC__NUM_DPP__MAX];
1059 int WritebackSourceWidth[DC__NUM_DPP__MAX];
1060
1061 bool ModeIsSupported;
1062 bool ODMCombine4To1Supported;
1063
1064 unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
1065 unsigned int SurfaceWidthC[DC__NUM_DPP__MAX];
1066 unsigned int SurfaceHeightY[DC__NUM_DPP__MAX];
1067 unsigned int SurfaceHeightC[DC__NUM_DPP__MAX];
1068 unsigned int WritebackHTaps[DC__NUM_DPP__MAX];
1069 unsigned int WritebackVTaps[DC__NUM_DPP__MAX];
1070 bool DSCEnable[DC__NUM_DPP__MAX];
1071
1072 double DRAMClockChangeLatencyOverride;
1073
1074 double GPUVMMinPageSize;
1075 double HostVMMinPageSize;
1076
1077 bool MPCCombineEnable[DC__NUM_DPP__MAX];
1078 unsigned int HostVMMaxNonCachedPageTableLevels;
1079 bool DynamicMetadataVMEnabled;
1080 double WritebackInterfaceBufferSize;
1081 double WritebackLineBufferSize;
1082
1083 double DCCRateLuma[DC__NUM_DPP__MAX];
1084 double DCCRateChroma[DC__NUM_DPP__MAX];
1085
1086 double PHYCLKD18PerState[DC__VOLTAGE_STATES];
1087
1088 bool WritebackSupportInterleaveAndUsingWholeBufferForASingleStream;
1089 bool NumberOfHDMIFRLSupport;
1090 unsigned int MaxNumHDMIFRLOutputs;
1091 int AudioSampleRate[DC__NUM_DPP__MAX];
1092 int AudioSampleLayout[DC__NUM_DPP__MAX];
1093
1094 int PercentMarginOverMinimumRequiredDCFCLK;
1095 bool DynamicMetadataSupported[DC__VOLTAGE_STATES][2];
1096 enum immediate_flip_requirement ImmediateFlipRequirement[DC__NUM_DPP__MAX];
1097 unsigned int DETBufferSizeYThisState[DC__NUM_DPP__MAX];
1098 unsigned int DETBufferSizeCThisState[DC__NUM_DPP__MAX];
1099 bool NoUrgentLatencyHiding[DC__NUM_DPP__MAX];
1100 bool NoUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1101 int swath_width_luma_ub_this_state[DC__NUM_DPP__MAX];
1102 int swath_width_chroma_ub_this_state[DC__NUM_DPP__MAX];
1103 double UrgLatency[DC__VOLTAGE_STATES];
1104 double VActiveCursorBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1105 double VActivePixelBandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1106 bool NoTimeForPrefetch[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1107 bool NoTimeForDynamicMetadata[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1108 double dpte_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1109 double meta_row_bandwidth[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1110 double DETBufferSizeYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1111 double DETBufferSizeCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1112 unsigned int swath_width_luma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1113 unsigned int swath_width_chroma_ub_all_states[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1114 bool NotUrgentLatencyHiding[DC__VOLTAGE_STATES][2];
1115 unsigned int SwathHeightYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1116 unsigned int SwathHeightCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1117 unsigned int SwathWidthYAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1118 unsigned int SwathWidthCAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1119 double TotalDPTERowBandwidth[DC__VOLTAGE_STATES][2];
1120 double TotalMetaRowBandwidth[DC__VOLTAGE_STATES][2];
1121 double TotalVActiveCursorBandwidth[DC__VOLTAGE_STATES][2];
1122 double TotalVActivePixelBandwidth[DC__VOLTAGE_STATES][2];
1123 double WritebackDelayTime[DC__NUM_DPP__MAX];
1124 unsigned int DCCYIndependentBlock[DC__NUM_DPP__MAX];
1125 unsigned int DCCCIndependentBlock[DC__NUM_DPP__MAX];
1126 unsigned int dummyinteger17;
1127 unsigned int dummyinteger18;
1128 unsigned int dummyinteger19;
1129 unsigned int dummyinteger20;
1130 unsigned int dummyinteger21;
1131 unsigned int dummyinteger22;
1132 unsigned int dummyinteger23;
1133 unsigned int dummyinteger24;
1134 unsigned int dummyinteger25;
1135 unsigned int dummyinteger26;
1136 unsigned int dummyinteger27;
1137 unsigned int dummyinteger28;
1138 unsigned int dummyinteger29;
1139 bool dummystring[DC__NUM_DPP__MAX];
1140 double BPP;
1141 enum odm_combine_policy ODMCombinePolicy;
1142 bool UseMinimumRequiredDCFCLK;
1143 bool ClampMinDCFCLK;
1144 bool AllowDramClockChangeOneDisplayVactive;
1145
1146 double MaxAveragePercentOfIdealFabricAndSDPPortBWDisplayCanUseInNormalSystemOperation;
1147 double PercentOfIdealFabricAndSDPPortBWReceivedAfterUrgLatency;
1148 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelMixedWithVMData;
1149 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyVMDataOnly;
1150 double PercentOfIdealDRAMBWReceivedAfterUrgLatencyPixelDataOnly;
1151 double SRExitZ8Time;
1152 double SREnterPlusExitZ8Time;
1153 double Z8StutterExitWatermark;
1154 double Z8StutterEnterPlusExitWatermark;
1155 double Z8StutterEfficiencyNotIncludingVBlank;
1156 double Z8StutterEfficiency;
1157 double DCCFractionOfZeroSizeRequestsLuma[DC__NUM_DPP__MAX];
1158 double DCCFractionOfZeroSizeRequestsChroma[DC__NUM_DPP__MAX];
1159 double UrgBurstFactorCursor[DC__NUM_DPP__MAX];
1160 double UrgBurstFactorLuma[DC__NUM_DPP__MAX];
1161 double UrgBurstFactorChroma[DC__NUM_DPP__MAX];
1162 double UrgBurstFactorCursorPre[DC__NUM_DPP__MAX];
1163 double UrgBurstFactorLumaPre[DC__NUM_DPP__MAX];
1164 double UrgBurstFactorChromaPre[DC__NUM_DPP__MAX];
1165 bool NotUrgentLatencyHidingPre[DC__NUM_DPP__MAX];
1166 bool LinkCapacitySupport[DC__VOLTAGE_STATES];
1167 bool VREADY_AT_OR_AFTER_VSYNC[DC__NUM_DPP__MAX];
1168 unsigned int MIN_DST_Y_NEXT_START[DC__NUM_DPP__MAX];
1169 unsigned int VFrontPorch[DC__NUM_DPP__MAX];
1170 int ConfigReturnBufferSizeInKByte;
1171 enum unbounded_requesting_policy UseUnboundedRequesting;
1172 int CompressedBufferSegmentSizeInkByte;
1173 int CompressedBufferSizeInkByte;
1174 int MetaFIFOSizeInKEntries;
1175 int ZeroSizeBufferEntries;
1176 int COMPBUF_RESERVED_SPACE_64B;
1177 int COMPBUF_RESERVED_SPACE_ZS;
1178 bool UnboundedRequestEnabled;
1179 bool DSC422NativeSupport;
1180 bool NoEnoughUrgentLatencyHiding;
1181 bool NoEnoughUrgentLatencyHidingPre;
1182 int NumberOfStutterBurstsPerFrame;
1183 int Z8NumberOfStutterBurstsPerFrame;
1184 unsigned int MaximumDSCBitsPerComponent;
1185 unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
1186 double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
1187 double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
1188 double SurfaceRequiredDISPCLKWithoutODMCombine;
1189 double SurfaceRequiredDISPCLK;
1190 double MinActiveFCLKChangeLatencySupported;
1191 int MinVoltageLevel;
1192 int MaxVoltageLevel;
1193 unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
1194 unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
1195 unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
1196 unsigned int DETBufferSizeInKByteThisState[DC__NUM_DPP__MAX];
1197 unsigned int SurfaceSizeInMALL[DC__NUM_DPP__MAX];
1198 bool ExceededMALLSize;
1199 bool PTE_BUFFER_MODE[DC__NUM_DPP__MAX];
1200 unsigned int BIGK_FRAGMENT_SIZE[DC__NUM_DPP__MAX];
1201 unsigned int CompressedBufferSizeInkByteThisState;
1202 enum dm_fclock_change_support FCLKChangeSupport[DC__VOLTAGE_STATES][2];
1203 bool USRRetrainingSupport[DC__VOLTAGE_STATES][2];
1204 enum dm_use_mall_for_pstate_change_mode UsesMALLForPStateChange[DC__NUM_DPP__MAX];
1205 bool UnboundedRequestEnabledAllStates[DC__VOLTAGE_STATES][2];
1206 bool SingleDPPViewportSizeSupportPerSurface[DC__NUM_DPP__MAX];
1207 enum dm_use_mall_for_static_screen_mode UseMALLForStaticScreen[DC__NUM_DPP__MAX];
1208 bool UnboundedRequestEnabledThisState;
1209 bool DRAMClockChangeRequirementFinal;
1210 bool FCLKChangeRequirementFinal;
1211 bool USRRetrainingRequiredFinal;
1212 unsigned int DETSizeOverride[DC__NUM_DPP__MAX];
1213 unsigned int nomDETInKByte;
1214 enum mpc_combine_affinity MPCCombineUse[DC__NUM_DPP__MAX];
1215 bool MPCCombineMethodIncompatible;
1216 unsigned int RequiredSlots[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
1217 bool ExceededMultistreamSlots[DC__VOLTAGE_STATES];
1218 enum odm_combine_policy ODMUse[DC__NUM_DPP__MAX];
1219 unsigned int OutputMultistreamId[DC__NUM_DPP__MAX];
1220 bool OutputMultistreamEn[DC__NUM_DPP__MAX];
1221 bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
1222 double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
1223 double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
1224 bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1225 bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
1226 bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
1227 bool PixelsPerLinePerDSCUnitSupport[DC__VOLTAGE_STATES];
1228 bool DCCMetaBufferSizeNotExceeded[DC__VOLTAGE_STATES][2];
1229 unsigned int dpte_row_height_linear[DC__NUM_DPP__MAX];
1230 unsigned int dpte_row_height_linear_chroma[DC__NUM_DPP__MAX];
1231 unsigned int BlockHeightY[DC__NUM_DPP__MAX];
1232 unsigned int BlockHeightC[DC__NUM_DPP__MAX];
1233 unsigned int BlockWidthY[DC__NUM_DPP__MAX];
1234 unsigned int BlockWidthC[DC__NUM_DPP__MAX];
1235 unsigned int SubViewportLinesNeededInMALL[DC__NUM_DPP__MAX];
1236 bool VActiveBandwithSupport[DC__VOLTAGE_STATES][2];
1237 bool NotEnoughDETSwathFillLatencyHidingPerState[DC__VOLTAGE_STATES][2];
1238 struct dummy_vars dummy_vars;
1239};
1240
1241bool CalculateMinAndMaxPrefetchMode(
1242 enum self_refresh_affinity AllowDRAMSelfRefreshOrDRAMClockChangeInVblank,
1243 unsigned int *MinPrefetchMode,
1244 unsigned int *MaxPrefetchMode);
1245
1246double CalculateWriteBackDISPCLK(
1247 enum source_format_class WritebackPixelFormat,
1248 double PixelClock,
1249 double WritebackHRatio,
1250 double WritebackVRatio,
1251 unsigned int WritebackLumaHTaps,
1252 unsigned int WritebackLumaVTaps,
1253 unsigned int WritebackChromaHTaps,
1254 unsigned int WritebackChromaVTaps,
1255 double WritebackDestinationWidth,
1256 unsigned int HTotal,
1257 unsigned int WritebackChromaLineBufferWidth);
1258
1259#endif /* _DML2_DISPLAY_MODE_VBA_H_ */