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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2022 Advanced Micro Devices, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27
28#include "dm_services.h"
29#include "dc.h"
30
31#include "dcn31/dcn31_init.h"
32#include "dcn314/dcn314_init.h"
33
34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn314_resource.h"
37
38#include "dcn20/dcn20_resource.h"
39#include "dcn30/dcn30_resource.h"
40#include "dcn31/dcn31_resource.h"
41
42#include "dcn10/dcn10_ipp.h"
43#include "dcn30/dcn30_hubbub.h"
44#include "dcn31/dcn31_hubbub.h"
45#include "dcn30/dcn30_mpc.h"
46#include "dcn31/dcn31_hubp.h"
47#include "irq/dcn31/irq_service_dcn31.h"
48#include "irq/dcn314/irq_service_dcn314.h"
49#include "dcn30/dcn30_dpp.h"
50#include "dcn314/dcn314_optc.h"
51#include "dcn20/dcn20_hwseq.h"
52#include "dcn30/dcn30_hwseq.h"
53#include "dce110/dce110_hw_sequencer.h"
54#include "dcn30/dcn30_opp.h"
55#include "dcn20/dcn20_dsc.h"
56#include "dcn30/dcn30_vpg.h"
57#include "dcn30/dcn30_afmt.h"
58#include "dcn31/dcn31_dio_link_encoder.h"
59#include "dcn314/dcn314_dio_stream_encoder.h"
60#include "dcn31/dcn31_hpo_dp_stream_encoder.h"
61#include "dcn31/dcn31_hpo_dp_link_encoder.h"
62#include "dcn31/dcn31_apg.h"
63#include "dcn31/dcn31_vpg.h"
64#include "dcn31/dcn31_afmt.h"
65#include "dce/dce_clock_source.h"
66#include "dce/dce_audio.h"
67#include "dce/dce_hwseq.h"
68#include "clk_mgr.h"
69#include "virtual/virtual_stream_encoder.h"
70#include "dce110/dce110_resource.h"
71#include "dml/display_mode_vba.h"
72#include "dml/dcn31/dcn31_fpu.h"
73#include "dml/dcn314/dcn314_fpu.h"
74#include "dcn314/dcn314_dccg.h"
75#include "dcn10/dcn10_resource.h"
76#include "dcn31/dcn31_panel_cntl.h"
77#include "dcn314/dcn314_hwseq.h"
78
79#include "dcn30/dcn30_dwb.h"
80#include "dcn30/dcn30_mmhubbub.h"
81
82#include "dcn/dcn_3_1_4_offset.h"
83#include "dcn/dcn_3_1_4_sh_mask.h"
84#include "dpcs/dpcs_3_1_4_offset.h"
85#include "dpcs/dpcs_3_1_4_sh_mask.h"
86
87#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT 0x10
88#define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK 0x01FF0000L
89
90#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE__SHIFT 0x0
91#define DSCC0_DSCC_CONFIG0__ICH_RESET_AT_END_OF_LINE_MASK 0x0000000FL
92
93#include "reg_helper.h"
94#include "dce/dmub_abm.h"
95#include "dce/dmub_psr.h"
96#include "dce/dce_aux.h"
97#include "dce/dce_i2c.h"
98#include "dml/dcn314/display_mode_vba_314.h"
99#include "vm_helper.h"
100#include "dcn20/dcn20_vmid.h"
101
102#include "link_enc_cfg.h"
103
104#define DCN_BASE__INST0_SEG1 0x000000C0
105#define DCN_BASE__INST0_SEG2 0x000034C0
106#define DCN_BASE__INST0_SEG3 0x00009000
107
108#define NBIO_BASE__INST0_SEG1 0x00000014
109
110#define MAX_INSTANCE 7
111#define MAX_SEGMENT 8
112
113#define regBIF_BX2_BIOS_SCRATCH_2 0x003a
114#define regBIF_BX2_BIOS_SCRATCH_2_BASE_IDX 1
115#define regBIF_BX2_BIOS_SCRATCH_3 0x003b
116#define regBIF_BX2_BIOS_SCRATCH_3_BASE_IDX 1
117#define regBIF_BX2_BIOS_SCRATCH_6 0x003e
118#define regBIF_BX2_BIOS_SCRATCH_6_BASE_IDX 1
119
120struct IP_BASE_INSTANCE {
121 unsigned int segment[MAX_SEGMENT];
122};
123
124struct IP_BASE {
125 struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
126};
127
128static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0, 0, 0 } },
129 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
130 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
131 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
132 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
133 { { 0, 0, 0, 0, 0, 0, 0, 0 } },
134 { { 0, 0, 0, 0, 0, 0, 0, 0 } } } };
135
136
137#define DC_LOGGER_INIT(logger)
138
139enum dcn31_clk_src_array_id {
140 DCN31_CLK_SRC_PLL0,
141 DCN31_CLK_SRC_PLL1,
142 DCN31_CLK_SRC_PLL2,
143 DCN31_CLK_SRC_PLL3,
144 DCN31_CLK_SRC_PLL4,
145 DCN30_CLK_SRC_TOTAL
146};
147
148/* begin *********************
149 * macros to expend register list macro defined in HW object header file
150 */
151
152/* DCN */
153/* TODO awful hack. fixup dcn20_dwb.h */
154#undef BASE_INNER
155#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
156
157#define BASE(seg) BASE_INNER(seg)
158
159#define SR(reg_name)\
160 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
161 reg ## reg_name
162
163#define SRI(reg_name, block, id)\
164 .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167#define SRI2(reg_name, block, id)\
168 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
169 reg ## reg_name
170
171#define SRIR(var_name, reg_name, block, id)\
172 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
173 reg ## block ## id ## _ ## reg_name
174
175#define SRII(reg_name, block, id)\
176 .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
177 reg ## block ## id ## _ ## reg_name
178
179#define SRII_MPC_RMU(reg_name, block, id)\
180 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
181 reg ## block ## id ## _ ## reg_name
182
183#define SRII_DWB(reg_name, temp_name, block, id)\
184 .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
185 reg ## block ## id ## _ ## temp_name
186
187#define SF_DWB2(reg_name, block, id, field_name, post_fix) \
188 .field_name = reg_name ## __ ## field_name ## post_fix
189
190#define DCCG_SRII(reg_name, block, id)\
191 .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
192 reg ## block ## id ## _ ## reg_name
193
194#define VUPDATE_SRII(reg_name, block, id)\
195 .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
196 reg ## reg_name ## _ ## block ## id
197
198/* NBIO */
199#define NBIO_BASE_INNER(seg) \
200 NBIO_BASE__INST0_SEG ## seg
201
202#define NBIO_BASE(seg) \
203 NBIO_BASE_INNER(seg)
204
205#define NBIO_SR(reg_name)\
206 .reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
207 regBIF_BX2_ ## reg_name
208
209/* MMHUB */
210#define MMHUB_BASE_INNER(seg) \
211 MMHUB_BASE__INST0_SEG ## seg
212
213#define MMHUB_BASE(seg) \
214 MMHUB_BASE_INNER(seg)
215
216#define MMHUB_SR(reg_name)\
217 .reg_name = MMHUB_BASE(reg ## reg_name ## _BASE_IDX) + \
218 reg ## reg_name
219
220/* CLOCK */
221#define CLK_BASE_INNER(seg) \
222 CLK_BASE__INST0_SEG ## seg
223
224#define CLK_BASE(seg) \
225 CLK_BASE_INNER(seg)
226
227#define CLK_SRI(reg_name, block, inst)\
228 .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
229 reg ## block ## _ ## inst ## _ ## reg_name
230
231
232static const struct bios_registers bios_regs = {
233 NBIO_SR(BIOS_SCRATCH_3),
234 NBIO_SR(BIOS_SCRATCH_6)
235};
236
237#define clk_src_regs(index, pllid)\
238[index] = {\
239 CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
240}
241
242static const struct dce110_clk_src_regs clk_src_regs[] = {
243 clk_src_regs(0, A),
244 clk_src_regs(1, B),
245 clk_src_regs(2, C),
246 clk_src_regs(3, D),
247 clk_src_regs(4, E)
248};
249
250static const struct dce110_clk_src_shift cs_shift = {
251 CS_COMMON_MASK_SH_LIST_DCN3_1_4(__SHIFT)
252};
253
254static const struct dce110_clk_src_mask cs_mask = {
255 CS_COMMON_MASK_SH_LIST_DCN3_1_4(_MASK)
256};
257
258#define abm_regs(id)\
259[id] = {\
260 ABM_DCN302_REG_LIST(id)\
261}
262
263static const struct dce_abm_registers abm_regs[] = {
264 abm_regs(0),
265 abm_regs(1),
266 abm_regs(2),
267 abm_regs(3),
268};
269
270static const struct dce_abm_shift abm_shift = {
271 ABM_MASK_SH_LIST_DCN30(__SHIFT)
272};
273
274static const struct dce_abm_mask abm_mask = {
275 ABM_MASK_SH_LIST_DCN30(_MASK)
276};
277
278#define audio_regs(id)\
279[id] = {\
280 AUD_COMMON_REG_LIST(id)\
281}
282
283static const struct dce_audio_registers audio_regs[] = {
284 audio_regs(0),
285 audio_regs(1),
286 audio_regs(2),
287 audio_regs(3),
288 audio_regs(4),
289 audio_regs(5),
290 audio_regs(6)
291};
292
293#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
294 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
295 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
296 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
297
298static const struct dce_audio_shift audio_shift = {
299 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
300};
301
302static const struct dce_audio_mask audio_mask = {
303 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
304};
305
306#define vpg_regs(id)\
307[id] = {\
308 VPG_DCN31_REG_LIST(id)\
309}
310
311static const struct dcn31_vpg_registers vpg_regs[] = {
312 vpg_regs(0),
313 vpg_regs(1),
314 vpg_regs(2),
315 vpg_regs(3),
316 vpg_regs(4),
317 vpg_regs(5),
318 vpg_regs(6),
319 vpg_regs(7),
320 vpg_regs(8),
321 vpg_regs(9),
322};
323
324static const struct dcn31_vpg_shift vpg_shift = {
325 DCN31_VPG_MASK_SH_LIST(__SHIFT)
326};
327
328static const struct dcn31_vpg_mask vpg_mask = {
329 DCN31_VPG_MASK_SH_LIST(_MASK)
330};
331
332#define afmt_regs(id)\
333[id] = {\
334 AFMT_DCN31_REG_LIST(id)\
335}
336
337static const struct dcn31_afmt_registers afmt_regs[] = {
338 afmt_regs(0),
339 afmt_regs(1),
340 afmt_regs(2),
341 afmt_regs(3),
342 afmt_regs(4),
343 afmt_regs(5)
344};
345
346static const struct dcn31_afmt_shift afmt_shift = {
347 DCN31_AFMT_MASK_SH_LIST(__SHIFT)
348};
349
350static const struct dcn31_afmt_mask afmt_mask = {
351 DCN31_AFMT_MASK_SH_LIST(_MASK)
352};
353
354#define apg_regs(id)\
355[id] = {\
356 APG_DCN31_REG_LIST(id)\
357}
358
359static const struct dcn31_apg_registers apg_regs[] = {
360 apg_regs(0),
361 apg_regs(1),
362 apg_regs(2),
363 apg_regs(3)
364};
365
366static const struct dcn31_apg_shift apg_shift = {
367 DCN31_APG_MASK_SH_LIST(__SHIFT)
368};
369
370static const struct dcn31_apg_mask apg_mask = {
371 DCN31_APG_MASK_SH_LIST(_MASK)
372};
373
374#define stream_enc_regs(id)\
375[id] = {\
376 SE_DCN314_REG_LIST(id)\
377}
378
379static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
380 stream_enc_regs(0),
381 stream_enc_regs(1),
382 stream_enc_regs(2),
383 stream_enc_regs(3),
384 stream_enc_regs(4)
385};
386
387static const struct dcn10_stream_encoder_shift se_shift = {
388 SE_COMMON_MASK_SH_LIST_DCN314(__SHIFT)
389};
390
391static const struct dcn10_stream_encoder_mask se_mask = {
392 SE_COMMON_MASK_SH_LIST_DCN314(_MASK)
393};
394
395
396#define aux_regs(id)\
397[id] = {\
398 DCN2_AUX_REG_LIST(id)\
399}
400
401static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
402 aux_regs(0),
403 aux_regs(1),
404 aux_regs(2),
405 aux_regs(3),
406 aux_regs(4)
407};
408
409#define hpd_regs(id)\
410[id] = {\
411 HPD_REG_LIST(id)\
412}
413
414static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
415 hpd_regs(0),
416 hpd_regs(1),
417 hpd_regs(2),
418 hpd_regs(3),
419 hpd_regs(4)
420};
421
422#define link_regs(id, phyid)\
423[id] = {\
424 LE_DCN31_REG_LIST(id), \
425 UNIPHY_DCN2_REG_LIST(phyid), \
426}
427
428static const struct dce110_aux_registers_shift aux_shift = {
429 DCN_AUX_MASK_SH_LIST(__SHIFT)
430};
431
432static const struct dce110_aux_registers_mask aux_mask = {
433 DCN_AUX_MASK_SH_LIST(_MASK)
434};
435
436static const struct dcn10_link_enc_registers link_enc_regs[] = {
437 link_regs(0, A),
438 link_regs(1, B),
439 link_regs(2, C),
440 link_regs(3, D),
441 link_regs(4, E)
442};
443
444static const struct dcn10_link_enc_shift le_shift = {
445 LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT),
446 DPCS_DCN31_MASK_SH_LIST(__SHIFT)
447};
448
449static const struct dcn10_link_enc_mask le_mask = {
450 LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK),
451 DPCS_DCN31_MASK_SH_LIST(_MASK)
452};
453
454#define hpo_dp_stream_encoder_reg_list(id)\
455[id] = {\
456 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
457}
458
459static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
460 hpo_dp_stream_encoder_reg_list(0),
461 hpo_dp_stream_encoder_reg_list(1),
462 hpo_dp_stream_encoder_reg_list(2),
463 hpo_dp_stream_encoder_reg_list(3)
464};
465
466static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
467 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
468};
469
470static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
471 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
472};
473
474
475#define hpo_dp_link_encoder_reg_list(id)\
476[id] = {\
477 DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
478 DCN3_1_RDPCSTX_REG_LIST(0),\
479 DCN3_1_RDPCSTX_REG_LIST(1),\
480 DCN3_1_RDPCSTX_REG_LIST(2),\
481}
482
483static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
484 hpo_dp_link_encoder_reg_list(0),
485 hpo_dp_link_encoder_reg_list(1),
486};
487
488static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
489 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
490};
491
492static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
493 DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
494};
495
496#define dpp_regs(id)\
497[id] = {\
498 DPP_REG_LIST_DCN30(id),\
499}
500
501static const struct dcn3_dpp_registers dpp_regs[] = {
502 dpp_regs(0),
503 dpp_regs(1),
504 dpp_regs(2),
505 dpp_regs(3)
506};
507
508static const struct dcn3_dpp_shift tf_shift = {
509 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
510};
511
512static const struct dcn3_dpp_mask tf_mask = {
513 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
514};
515
516#define opp_regs(id)\
517[id] = {\
518 OPP_REG_LIST_DCN30(id),\
519}
520
521static const struct dcn20_opp_registers opp_regs[] = {
522 opp_regs(0),
523 opp_regs(1),
524 opp_regs(2),
525 opp_regs(3)
526};
527
528static const struct dcn20_opp_shift opp_shift = {
529 OPP_MASK_SH_LIST_DCN20(__SHIFT)
530};
531
532static const struct dcn20_opp_mask opp_mask = {
533 OPP_MASK_SH_LIST_DCN20(_MASK)
534};
535
536#define aux_engine_regs(id)\
537[id] = {\
538 AUX_COMMON_REG_LIST0(id), \
539 .AUXN_IMPCAL = 0, \
540 .AUXP_IMPCAL = 0, \
541 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
542}
543
544static const struct dce110_aux_registers aux_engine_regs[] = {
545 aux_engine_regs(0),
546 aux_engine_regs(1),
547 aux_engine_regs(2),
548 aux_engine_regs(3),
549 aux_engine_regs(4)
550};
551
552#define dwbc_regs_dcn3(id)\
553[id] = {\
554 DWBC_COMMON_REG_LIST_DCN30(id),\
555}
556
557static const struct dcn30_dwbc_registers dwbc30_regs[] = {
558 dwbc_regs_dcn3(0),
559};
560
561static const struct dcn30_dwbc_shift dwbc30_shift = {
562 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
563};
564
565static const struct dcn30_dwbc_mask dwbc30_mask = {
566 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
567};
568
569#define mcif_wb_regs_dcn3(id)\
570[id] = {\
571 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
572}
573
574static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
575 mcif_wb_regs_dcn3(0)
576};
577
578static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
579 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
580};
581
582static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
583 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
584};
585
586#define dsc_regsDCN314(id)\
587[id] = {\
588 DSC_REG_LIST_DCN20(id)\
589}
590
591static const struct dcn20_dsc_registers dsc_regs[] = {
592 dsc_regsDCN314(0),
593 dsc_regsDCN314(1),
594 dsc_regsDCN314(2),
595 dsc_regsDCN314(3)
596};
597
598static const struct dcn20_dsc_shift dsc_shift = {
599 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
600};
601
602static const struct dcn20_dsc_mask dsc_mask = {
603 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
604};
605
606static const struct dcn30_mpc_registers mpc_regs = {
607 MPC_REG_LIST_DCN3_0(0),
608 MPC_REG_LIST_DCN3_0(1),
609 MPC_REG_LIST_DCN3_0(2),
610 MPC_REG_LIST_DCN3_0(3),
611 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
612 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
613 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
614 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
615 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
616 MPC_RMU_REG_LIST_DCN3AG(0),
617 MPC_RMU_REG_LIST_DCN3AG(1),
618 //MPC_RMU_REG_LIST_DCN3AG(2),
619 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
620};
621
622static const struct dcn30_mpc_shift mpc_shift = {
623 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
624};
625
626static const struct dcn30_mpc_mask mpc_mask = {
627 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
628};
629
630#define optc_regs(id)\
631[id] = {OPTC_COMMON_REG_LIST_DCN3_14(id)}
632
633static const struct dcn_optc_registers optc_regs[] = {
634 optc_regs(0),
635 optc_regs(1),
636 optc_regs(2),
637 optc_regs(3)
638};
639
640static const struct dcn_optc_shift optc_shift = {
641 OPTC_COMMON_MASK_SH_LIST_DCN3_14(__SHIFT)
642};
643
644static const struct dcn_optc_mask optc_mask = {
645 OPTC_COMMON_MASK_SH_LIST_DCN3_14(_MASK)
646};
647
648#define hubp_regs(id)\
649[id] = {\
650 HUBP_REG_LIST_DCN30(id)\
651}
652
653static const struct dcn_hubp2_registers hubp_regs[] = {
654 hubp_regs(0),
655 hubp_regs(1),
656 hubp_regs(2),
657 hubp_regs(3)
658};
659
660
661static const struct dcn_hubp2_shift hubp_shift = {
662 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
663};
664
665static const struct dcn_hubp2_mask hubp_mask = {
666 HUBP_MASK_SH_LIST_DCN31(_MASK)
667};
668static const struct dcn_hubbub_registers hubbub_reg = {
669 HUBBUB_REG_LIST_DCN31(0)
670};
671
672static const struct dcn_hubbub_shift hubbub_shift = {
673 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
674};
675
676static const struct dcn_hubbub_mask hubbub_mask = {
677 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
678};
679
680static const struct dccg_registers dccg_regs = {
681 DCCG_REG_LIST_DCN314()
682};
683
684static const struct dccg_shift dccg_shift = {
685 DCCG_MASK_SH_LIST_DCN314(__SHIFT)
686};
687
688static const struct dccg_mask dccg_mask = {
689 DCCG_MASK_SH_LIST_DCN314(_MASK)
690};
691
692
693#define SRII2(reg_name_pre, reg_name_post, id)\
694 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
695 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
696 reg ## reg_name_pre ## id ## _ ## reg_name_post
697
698
699#define HWSEQ_DCN31_REG_LIST()\
700 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
701 SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
702 SR(DIO_MEM_PWR_CTRL), \
703 SR(ODM_MEM_PWR_CTRL3), \
704 SR(DMU_MEM_PWR_CNTL), \
705 SR(MMHUBBUB_MEM_PWR_CNTL), \
706 SR(DCCG_GATE_DISABLE_CNTL), \
707 SR(DCCG_GATE_DISABLE_CNTL2), \
708 SR(DCFCLK_CNTL),\
709 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
710 SRII(PIXEL_RATE_CNTL, OTG, 0), \
711 SRII(PIXEL_RATE_CNTL, OTG, 1),\
712 SRII(PIXEL_RATE_CNTL, OTG, 2),\
713 SRII(PIXEL_RATE_CNTL, OTG, 3),\
714 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
715 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
716 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
717 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
718 SR(MICROSECOND_TIME_BASE_DIV), \
719 SR(MILLISECOND_TIME_BASE_DIV), \
720 SR(DISPCLK_FREQ_CHANGE_CNTL), \
721 SR(RBBMIF_TIMEOUT_DIS), \
722 SR(RBBMIF_TIMEOUT_DIS_2), \
723 SR(DCHUBBUB_CRC_CTRL), \
724 SR(DPP_TOP0_DPP_CRC_CTRL), \
725 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
726 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
727 SR(MPC_CRC_CTRL), \
728 SR(MPC_CRC_RESULT_GB), \
729 SR(MPC_CRC_RESULT_C), \
730 SR(MPC_CRC_RESULT_AR), \
731 SR(DOMAIN0_PG_CONFIG), \
732 SR(DOMAIN1_PG_CONFIG), \
733 SR(DOMAIN2_PG_CONFIG), \
734 SR(DOMAIN3_PG_CONFIG), \
735 SR(DOMAIN16_PG_CONFIG), \
736 SR(DOMAIN17_PG_CONFIG), \
737 SR(DOMAIN18_PG_CONFIG), \
738 SR(DOMAIN19_PG_CONFIG), \
739 SR(DOMAIN0_PG_STATUS), \
740 SR(DOMAIN1_PG_STATUS), \
741 SR(DOMAIN2_PG_STATUS), \
742 SR(DOMAIN3_PG_STATUS), \
743 SR(DOMAIN16_PG_STATUS), \
744 SR(DOMAIN17_PG_STATUS), \
745 SR(DOMAIN18_PG_STATUS), \
746 SR(DOMAIN19_PG_STATUS), \
747 SR(D1VGA_CONTROL), \
748 SR(D2VGA_CONTROL), \
749 SR(D3VGA_CONTROL), \
750 SR(D4VGA_CONTROL), \
751 SR(D5VGA_CONTROL), \
752 SR(D6VGA_CONTROL), \
753 SR(DC_IP_REQUEST_CNTL), \
754 SR(AZALIA_AUDIO_DTO), \
755 SR(AZALIA_CONTROLLER_CLOCK_GATING), \
756 SR(HPO_TOP_HW_CONTROL)
757
758static const struct dce_hwseq_registers hwseq_reg = {
759 HWSEQ_DCN31_REG_LIST()
760};
761
762#define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
763 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
764 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
765 HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
766 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
767 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
768 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
769 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
770 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
771 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
772 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
773 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
774 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
775 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
776 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
777 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
778 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
779 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
780 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
781 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
782 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
783 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
784 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
785 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
786 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
787 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
788 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
789 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
790 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
791 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
792 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
793 HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
794 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
795 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
796 HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
797 HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
798 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
799
800static const struct dce_hwseq_shift hwseq_shift = {
801 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
802};
803
804static const struct dce_hwseq_mask hwseq_mask = {
805 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
806};
807#define vmid_regs(id)\
808[id] = {\
809 DCN20_VMID_REG_LIST(id)\
810}
811
812static const struct dcn_vmid_registers vmid_regs[] = {
813 vmid_regs(0),
814 vmid_regs(1),
815 vmid_regs(2),
816 vmid_regs(3),
817 vmid_regs(4),
818 vmid_regs(5),
819 vmid_regs(6),
820 vmid_regs(7),
821 vmid_regs(8),
822 vmid_regs(9),
823 vmid_regs(10),
824 vmid_regs(11),
825 vmid_regs(12),
826 vmid_regs(13),
827 vmid_regs(14),
828 vmid_regs(15)
829};
830
831static const struct dcn20_vmid_shift vmid_shifts = {
832 DCN20_VMID_MASK_SH_LIST(__SHIFT)
833};
834
835static const struct dcn20_vmid_mask vmid_masks = {
836 DCN20_VMID_MASK_SH_LIST(_MASK)
837};
838
839static const struct resource_caps res_cap_dcn314 = {
840 .num_timing_generator = 4,
841 .num_opp = 4,
842 .num_video_plane = 4,
843 .num_audio = 5,
844 .num_stream_encoder = 5,
845 .num_dig_link_enc = 5,
846 .num_hpo_dp_stream_encoder = 4,
847 .num_hpo_dp_link_encoder = 2,
848 .num_pll = 5,
849 .num_dwb = 1,
850 .num_ddc = 5,
851 .num_vmid = 16,
852 .num_mpc_3dlut = 2,
853 .num_dsc = 4,
854};
855
856static const struct dc_plane_cap plane_cap = {
857 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
858 .blends_with_above = true,
859 .blends_with_below = true,
860 .per_pixel_alpha = true,
861
862 .pixel_format_support = {
863 .argb8888 = true,
864 .nv12 = true,
865 .fp16 = true,
866 .p010 = true,
867 .ayuv = false,
868 },
869
870 .max_upscale_factor = {
871 .argb8888 = 16000,
872 .nv12 = 16000,
873 .fp16 = 16000
874 },
875
876 // 6:1 downscaling ratio: 1000/6 = 166.666
877 // 4:1 downscaling ratio for ARGB888 to prevent underflow during P010 playback: 1000/4 = 250
878 .max_downscale_factor = {
879 .argb8888 = 250,
880 .nv12 = 167,
881 .fp16 = 167
882 },
883 64,
884 64
885};
886
887static const struct dc_debug_options debug_defaults_drv = {
888 .disable_z10 = false,
889 .enable_z9_disable_interface = true,
890 .psr_skip_crtc_disable = true,
891 .disable_dmcu = true,
892 .force_abm_enable = false,
893 .timing_trace = false,
894 .clock_trace = true,
895 .disable_pplib_clock_request = false,
896 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
897 .force_single_disp_pipe_split = false,
898 .disable_dcc = DCC_ENABLE,
899 .vsr_support = true,
900 .performance_trace = false,
901 .max_downscale_src_width = 4096,/*upto true 4k*/
902 .disable_pplib_wm_range = false,
903 .scl_reset_length10 = true,
904 .sanity_checks = false,
905 .underflow_assert_delay_us = 0xFFFFFFFF,
906 .dwb_fi_phase = -1, // -1 = disable,
907 .dmub_command_table = true,
908 .pstate_enabled = true,
909 .use_max_lb = true,
910 .enable_mem_low_power = {
911 .bits = {
912 .vga = true,
913 .i2c = true,
914 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
915 .dscl = true,
916 .cm = true,
917 .mpc = true,
918 .optc = true,
919 .vpg = true,
920 .afmt = true,
921 }
922 },
923 .seamless_boot_odm_combine = true
924};
925
926static const struct dc_debug_options debug_defaults_diags = {
927 .disable_dmcu = true,
928 .force_abm_enable = false,
929 .timing_trace = true,
930 .clock_trace = true,
931 .disable_dpp_power_gate = true,
932 .disable_hubp_power_gate = true,
933 .disable_clock_gate = true,
934 .disable_pplib_clock_request = true,
935 .disable_pplib_wm_range = true,
936 .disable_stutter = false,
937 .scl_reset_length10 = true,
938 .dwb_fi_phase = -1, // -1 = disable
939 .dmub_command_table = true,
940 .enable_tri_buf = true,
941 .use_max_lb = true
942};
943
944static const struct dc_panel_config panel_config_defaults = {
945 .psr = {
946 .disable_psr = false,
947 .disallow_psrsu = false,
948 },
949 .ilr = {
950 .optimize_edp_link_rate = true,
951 },
952};
953
954static void dcn31_dpp_destroy(struct dpp **dpp)
955{
956 kfree(TO_DCN20_DPP(*dpp));
957 *dpp = NULL;
958}
959
960static struct dpp *dcn31_dpp_create(
961 struct dc_context *ctx,
962 uint32_t inst)
963{
964 struct dcn3_dpp *dpp =
965 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
966
967 if (!dpp)
968 return NULL;
969
970 if (dpp3_construct(dpp, ctx, inst,
971 &dpp_regs[inst], &tf_shift, &tf_mask))
972 return &dpp->base;
973
974 BREAK_TO_DEBUGGER();
975 kfree(dpp);
976 return NULL;
977}
978
979static struct output_pixel_processor *dcn31_opp_create(
980 struct dc_context *ctx, uint32_t inst)
981{
982 struct dcn20_opp *opp =
983 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
984
985 if (!opp) {
986 BREAK_TO_DEBUGGER();
987 return NULL;
988 }
989
990 dcn20_opp_construct(opp, ctx, inst,
991 &opp_regs[inst], &opp_shift, &opp_mask);
992 return &opp->base;
993}
994
995static struct dce_aux *dcn31_aux_engine_create(
996 struct dc_context *ctx,
997 uint32_t inst)
998{
999 struct aux_engine_dce110 *aux_engine =
1000 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1001
1002 if (!aux_engine)
1003 return NULL;
1004
1005 dce110_aux_engine_construct(aux_engine, ctx, inst,
1006 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1007 &aux_engine_regs[inst],
1008 &aux_mask,
1009 &aux_shift,
1010 ctx->dc->caps.extended_aux_timeout_support);
1011
1012 return &aux_engine->base;
1013}
1014#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1015
1016static const struct dce_i2c_registers i2c_hw_regs[] = {
1017 i2c_inst_regs(1),
1018 i2c_inst_regs(2),
1019 i2c_inst_regs(3),
1020 i2c_inst_regs(4),
1021 i2c_inst_regs(5),
1022};
1023
1024static const struct dce_i2c_shift i2c_shifts = {
1025 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1026};
1027
1028static const struct dce_i2c_mask i2c_masks = {
1029 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1030};
1031
1032static struct dce_i2c_hw *dcn31_i2c_hw_create(
1033 struct dc_context *ctx,
1034 uint32_t inst)
1035{
1036 struct dce_i2c_hw *dce_i2c_hw =
1037 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1038
1039 if (!dce_i2c_hw)
1040 return NULL;
1041
1042 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1043 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1044
1045 return dce_i2c_hw;
1046}
1047static struct mpc *dcn31_mpc_create(
1048 struct dc_context *ctx,
1049 int num_mpcc,
1050 int num_rmu)
1051{
1052 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1053 GFP_KERNEL);
1054
1055 if (!mpc30)
1056 return NULL;
1057
1058 dcn30_mpc_construct(mpc30, ctx,
1059 &mpc_regs,
1060 &mpc_shift,
1061 &mpc_mask,
1062 num_mpcc,
1063 num_rmu);
1064
1065 return &mpc30->base;
1066}
1067
1068static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1069{
1070 int i;
1071
1072 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1073 GFP_KERNEL);
1074
1075 if (!hubbub3)
1076 return NULL;
1077
1078 hubbub31_construct(hubbub3, ctx,
1079 &hubbub_reg,
1080 &hubbub_shift,
1081 &hubbub_mask,
1082 dcn3_14_ip.det_buffer_size_kbytes,
1083 dcn3_14_ip.pixel_chunk_size_kbytes,
1084 dcn3_14_ip.config_return_buffer_size_in_kbytes);
1085
1086
1087 for (i = 0; i < res_cap_dcn314.num_vmid; i++) {
1088 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1089
1090 vmid->ctx = ctx;
1091
1092 vmid->regs = &vmid_regs[i];
1093 vmid->shifts = &vmid_shifts;
1094 vmid->masks = &vmid_masks;
1095 }
1096
1097 return &hubbub3->base;
1098}
1099
1100static struct timing_generator *dcn31_timing_generator_create(
1101 struct dc_context *ctx,
1102 uint32_t instance)
1103{
1104 struct optc *tgn10 =
1105 kzalloc(sizeof(struct optc), GFP_KERNEL);
1106
1107 if (!tgn10)
1108 return NULL;
1109
1110 tgn10->base.inst = instance;
1111 tgn10->base.ctx = ctx;
1112
1113 tgn10->tg_regs = &optc_regs[instance];
1114 tgn10->tg_shift = &optc_shift;
1115 tgn10->tg_mask = &optc_mask;
1116
1117 dcn314_timing_generator_init(tgn10);
1118
1119 return &tgn10->base;
1120}
1121
1122static const struct encoder_feature_support link_enc_feature = {
1123 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1124 .max_hdmi_pixel_clock = 600000,
1125 .hdmi_ycbcr420_supported = true,
1126 .dp_ycbcr420_supported = true,
1127 .fec_supported = true,
1128 .flags.bits.IS_HBR2_CAPABLE = true,
1129 .flags.bits.IS_HBR3_CAPABLE = true,
1130 .flags.bits.IS_TPS3_CAPABLE = true,
1131 .flags.bits.IS_TPS4_CAPABLE = true
1132};
1133
1134static struct link_encoder *dcn31_link_encoder_create(
1135 struct dc_context *ctx,
1136 const struct encoder_init_data *enc_init_data)
1137{
1138 struct dcn20_link_encoder *enc20 =
1139 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1140
1141 if (!enc20)
1142 return NULL;
1143
1144 dcn31_link_encoder_construct(enc20,
1145 enc_init_data,
1146 &link_enc_feature,
1147 &link_enc_regs[enc_init_data->transmitter],
1148 &link_enc_aux_regs[enc_init_data->channel - 1],
1149 &link_enc_hpd_regs[enc_init_data->hpd_source],
1150 &le_shift,
1151 &le_mask);
1152
1153 return &enc20->enc10.base;
1154}
1155
1156/* Create a minimal link encoder object not associated with a particular
1157 * physical connector.
1158 * resource_funcs.link_enc_create_minimal
1159 */
1160static struct link_encoder *dcn31_link_enc_create_minimal(
1161 struct dc_context *ctx, enum engine_id eng_id)
1162{
1163 struct dcn20_link_encoder *enc20;
1164
1165 if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1166 return NULL;
1167
1168 enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1169 if (!enc20)
1170 return NULL;
1171
1172 dcn31_link_encoder_construct_minimal(
1173 enc20,
1174 ctx,
1175 &link_enc_feature,
1176 &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1177 eng_id);
1178
1179 return &enc20->enc10.base;
1180}
1181
1182static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1183{
1184 struct dcn31_panel_cntl *panel_cntl =
1185 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1186
1187 if (!panel_cntl)
1188 return NULL;
1189
1190 dcn31_panel_cntl_construct(panel_cntl, init_data);
1191
1192 return &panel_cntl->base;
1193}
1194
1195static void read_dce_straps(
1196 struct dc_context *ctx,
1197 struct resource_straps *straps)
1198{
1199 generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1200 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1201
1202}
1203
1204static struct audio *dcn31_create_audio(
1205 struct dc_context *ctx, unsigned int inst)
1206{
1207 return dce_audio_create(ctx, inst,
1208 &audio_regs[inst], &audio_shift, &audio_mask);
1209}
1210
1211static struct vpg *dcn31_vpg_create(
1212 struct dc_context *ctx,
1213 uint32_t inst)
1214{
1215 struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1216
1217 if (!vpg31)
1218 return NULL;
1219
1220 vpg31_construct(vpg31, ctx, inst,
1221 &vpg_regs[inst],
1222 &vpg_shift,
1223 &vpg_mask);
1224
1225 return &vpg31->base;
1226}
1227
1228static struct afmt *dcn31_afmt_create(
1229 struct dc_context *ctx,
1230 uint32_t inst)
1231{
1232 struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1233
1234 if (!afmt31)
1235 return NULL;
1236
1237 afmt31_construct(afmt31, ctx, inst,
1238 &afmt_regs[inst],
1239 &afmt_shift,
1240 &afmt_mask);
1241
1242 // Light sleep by default, no need to power down here
1243
1244 return &afmt31->base;
1245}
1246
1247static struct apg *dcn31_apg_create(
1248 struct dc_context *ctx,
1249 uint32_t inst)
1250{
1251 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1252
1253 if (!apg31)
1254 return NULL;
1255
1256 apg31_construct(apg31, ctx, inst,
1257 &apg_regs[inst],
1258 &apg_shift,
1259 &apg_mask);
1260
1261 return &apg31->base;
1262}
1263
1264static struct stream_encoder *dcn314_stream_encoder_create(
1265 enum engine_id eng_id,
1266 struct dc_context *ctx)
1267{
1268 struct dcn10_stream_encoder *enc1;
1269 struct vpg *vpg;
1270 struct afmt *afmt;
1271 int vpg_inst;
1272 int afmt_inst;
1273
1274 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1275 if (eng_id < ENGINE_ID_DIGF) {
1276 vpg_inst = eng_id;
1277 afmt_inst = eng_id;
1278 } else
1279 return NULL;
1280
1281 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1282 vpg = dcn31_vpg_create(ctx, vpg_inst);
1283 afmt = dcn31_afmt_create(ctx, afmt_inst);
1284
1285 if (!enc1 || !vpg || !afmt) {
1286 kfree(enc1);
1287 kfree(vpg);
1288 kfree(afmt);
1289 return NULL;
1290 }
1291
1292 dcn314_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1293 eng_id, vpg, afmt,
1294 &stream_enc_regs[eng_id],
1295 &se_shift, &se_mask);
1296
1297 return &enc1->base;
1298}
1299
1300static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1301 enum engine_id eng_id,
1302 struct dc_context *ctx)
1303{
1304 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1305 struct vpg *vpg;
1306 struct apg *apg;
1307 uint32_t hpo_dp_inst;
1308 uint32_t vpg_inst;
1309 uint32_t apg_inst;
1310
1311 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1312 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1313
1314 /* Mapping of VPG register blocks to HPO DP block instance:
1315 * VPG[6] -> HPO_DP[0]
1316 * VPG[7] -> HPO_DP[1]
1317 * VPG[8] -> HPO_DP[2]
1318 * VPG[9] -> HPO_DP[3]
1319 */
1320 //Uses offset index 5-8, but actually maps to vpg_inst 6-9
1321 vpg_inst = hpo_dp_inst + 5;
1322
1323 /* Mapping of APG register blocks to HPO DP block instance:
1324 * APG[0] -> HPO_DP[0]
1325 * APG[1] -> HPO_DP[1]
1326 * APG[2] -> HPO_DP[2]
1327 * APG[3] -> HPO_DP[3]
1328 */
1329 apg_inst = hpo_dp_inst;
1330
1331 /* allocate HPO stream encoder and create VPG sub-block */
1332 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1333 vpg = dcn31_vpg_create(ctx, vpg_inst);
1334 apg = dcn31_apg_create(ctx, apg_inst);
1335
1336 if (!hpo_dp_enc31 || !vpg || !apg) {
1337 kfree(hpo_dp_enc31);
1338 kfree(vpg);
1339 kfree(apg);
1340 return NULL;
1341 }
1342
1343 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1344 hpo_dp_inst, eng_id, vpg, apg,
1345 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1346 &hpo_dp_se_shift, &hpo_dp_se_mask);
1347
1348 return &hpo_dp_enc31->base;
1349}
1350
1351static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1352 uint8_t inst,
1353 struct dc_context *ctx)
1354{
1355 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1356
1357 /* allocate HPO link encoder */
1358 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1359
1360 hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1361 &hpo_dp_link_enc_regs[inst],
1362 &hpo_dp_le_shift, &hpo_dp_le_mask);
1363
1364 return &hpo_dp_enc31->base;
1365}
1366
1367static struct dce_hwseq *dcn314_hwseq_create(
1368 struct dc_context *ctx)
1369{
1370 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1371
1372 if (hws) {
1373 hws->ctx = ctx;
1374 hws->regs = &hwseq_reg;
1375 hws->shifts = &hwseq_shift;
1376 hws->masks = &hwseq_mask;
1377 /* DCN3.1 FPGA Workaround
1378 * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1379 * To do so, move calling function enable_stream_timing to only be done AFTER calling
1380 * function core_link_enable_stream
1381 */
1382 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1383 hws->wa.dp_hpo_and_otg_sequence = true;
1384 }
1385 return hws;
1386}
1387static const struct resource_create_funcs res_create_funcs = {
1388 .read_dce_straps = read_dce_straps,
1389 .create_audio = dcn31_create_audio,
1390 .create_stream_encoder = dcn314_stream_encoder_create,
1391 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1392 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1393 .create_hwseq = dcn314_hwseq_create,
1394};
1395
1396static const struct resource_create_funcs res_create_maximus_funcs = {
1397 .read_dce_straps = NULL,
1398 .create_audio = NULL,
1399 .create_stream_encoder = NULL,
1400 .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1401 .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1402 .create_hwseq = dcn314_hwseq_create,
1403};
1404
1405static void dcn314_resource_destruct(struct dcn314_resource_pool *pool)
1406{
1407 unsigned int i;
1408
1409 for (i = 0; i < pool->base.stream_enc_count; i++) {
1410 if (pool->base.stream_enc[i] != NULL) {
1411 if (pool->base.stream_enc[i]->vpg != NULL) {
1412 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1413 pool->base.stream_enc[i]->vpg = NULL;
1414 }
1415 if (pool->base.stream_enc[i]->afmt != NULL) {
1416 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1417 pool->base.stream_enc[i]->afmt = NULL;
1418 }
1419 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1420 pool->base.stream_enc[i] = NULL;
1421 }
1422 }
1423
1424 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1425 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1426 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1427 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1428 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1429 }
1430 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1431 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1432 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1433 }
1434 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1435 pool->base.hpo_dp_stream_enc[i] = NULL;
1436 }
1437 }
1438
1439 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1440 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1441 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1442 pool->base.hpo_dp_link_enc[i] = NULL;
1443 }
1444 }
1445
1446 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1447 if (pool->base.dscs[i] != NULL)
1448 dcn20_dsc_destroy(&pool->base.dscs[i]);
1449 }
1450
1451 if (pool->base.mpc != NULL) {
1452 kfree(TO_DCN20_MPC(pool->base.mpc));
1453 pool->base.mpc = NULL;
1454 }
1455 if (pool->base.hubbub != NULL) {
1456 kfree(pool->base.hubbub);
1457 pool->base.hubbub = NULL;
1458 }
1459 for (i = 0; i < pool->base.pipe_count; i++) {
1460 if (pool->base.dpps[i] != NULL)
1461 dcn31_dpp_destroy(&pool->base.dpps[i]);
1462
1463 if (pool->base.ipps[i] != NULL)
1464 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1465
1466 if (pool->base.hubps[i] != NULL) {
1467 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1468 pool->base.hubps[i] = NULL;
1469 }
1470
1471 if (pool->base.irqs != NULL)
1472 dal_irq_service_destroy(&pool->base.irqs);
1473 }
1474
1475 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1476 if (pool->base.engines[i] != NULL)
1477 dce110_engine_destroy(&pool->base.engines[i]);
1478 if (pool->base.hw_i2cs[i] != NULL) {
1479 kfree(pool->base.hw_i2cs[i]);
1480 pool->base.hw_i2cs[i] = NULL;
1481 }
1482 if (pool->base.sw_i2cs[i] != NULL) {
1483 kfree(pool->base.sw_i2cs[i]);
1484 pool->base.sw_i2cs[i] = NULL;
1485 }
1486 }
1487
1488 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1489 if (pool->base.opps[i] != NULL)
1490 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1491 }
1492
1493 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1494 if (pool->base.timing_generators[i] != NULL) {
1495 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1496 pool->base.timing_generators[i] = NULL;
1497 }
1498 }
1499
1500 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1501 if (pool->base.dwbc[i] != NULL) {
1502 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1503 pool->base.dwbc[i] = NULL;
1504 }
1505 if (pool->base.mcif_wb[i] != NULL) {
1506 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1507 pool->base.mcif_wb[i] = NULL;
1508 }
1509 }
1510
1511 for (i = 0; i < pool->base.audio_count; i++) {
1512 if (pool->base.audios[i])
1513 dce_aud_destroy(&pool->base.audios[i]);
1514 }
1515
1516 for (i = 0; i < pool->base.clk_src_count; i++) {
1517 if (pool->base.clock_sources[i] != NULL) {
1518 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1519 pool->base.clock_sources[i] = NULL;
1520 }
1521 }
1522
1523 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1524 if (pool->base.mpc_lut[i] != NULL) {
1525 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1526 pool->base.mpc_lut[i] = NULL;
1527 }
1528 if (pool->base.mpc_shaper[i] != NULL) {
1529 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1530 pool->base.mpc_shaper[i] = NULL;
1531 }
1532 }
1533
1534 if (pool->base.dp_clock_source != NULL) {
1535 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1536 pool->base.dp_clock_source = NULL;
1537 }
1538
1539 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1540 if (pool->base.multiple_abms[i] != NULL)
1541 dce_abm_destroy(&pool->base.multiple_abms[i]);
1542 }
1543
1544 if (pool->base.psr != NULL)
1545 dmub_psr_destroy(&pool->base.psr);
1546
1547 if (pool->base.dccg != NULL)
1548 dcn_dccg_destroy(&pool->base.dccg);
1549}
1550
1551static struct hubp *dcn31_hubp_create(
1552 struct dc_context *ctx,
1553 uint32_t inst)
1554{
1555 struct dcn20_hubp *hubp2 =
1556 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1557
1558 if (!hubp2)
1559 return NULL;
1560
1561 if (hubp31_construct(hubp2, ctx, inst,
1562 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1563 return &hubp2->base;
1564
1565 BREAK_TO_DEBUGGER();
1566 kfree(hubp2);
1567 return NULL;
1568}
1569
1570static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1571{
1572 int i;
1573 uint32_t pipe_count = pool->res_cap->num_dwb;
1574
1575 for (i = 0; i < pipe_count; i++) {
1576 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1577 GFP_KERNEL);
1578
1579 if (!dwbc30) {
1580 dm_error("DC: failed to create dwbc30!\n");
1581 return false;
1582 }
1583
1584 dcn30_dwbc_construct(dwbc30, ctx,
1585 &dwbc30_regs[i],
1586 &dwbc30_shift,
1587 &dwbc30_mask,
1588 i);
1589
1590 pool->dwbc[i] = &dwbc30->base;
1591 }
1592 return true;
1593}
1594
1595static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1596{
1597 int i;
1598 uint32_t pipe_count = pool->res_cap->num_dwb;
1599
1600 for (i = 0; i < pipe_count; i++) {
1601 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1602 GFP_KERNEL);
1603
1604 if (!mcif_wb30) {
1605 dm_error("DC: failed to create mcif_wb30!\n");
1606 return false;
1607 }
1608
1609 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1610 &mcif_wb30_regs[i],
1611 &mcif_wb30_shift,
1612 &mcif_wb30_mask,
1613 i);
1614
1615 pool->mcif_wb[i] = &mcif_wb30->base;
1616 }
1617 return true;
1618}
1619
1620static struct display_stream_compressor *dcn314_dsc_create(
1621 struct dc_context *ctx, uint32_t inst)
1622{
1623 struct dcn20_dsc *dsc =
1624 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1625
1626 if (!dsc) {
1627 BREAK_TO_DEBUGGER();
1628 return NULL;
1629 }
1630
1631 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1632 return &dsc->base;
1633}
1634
1635static void dcn314_destroy_resource_pool(struct resource_pool **pool)
1636{
1637 struct dcn314_resource_pool *dcn314_pool = TO_DCN314_RES_POOL(*pool);
1638
1639 dcn314_resource_destruct(dcn314_pool);
1640 kfree(dcn314_pool);
1641 *pool = NULL;
1642}
1643
1644static struct clock_source *dcn31_clock_source_create(
1645 struct dc_context *ctx,
1646 struct dc_bios *bios,
1647 enum clock_source_id id,
1648 const struct dce110_clk_src_regs *regs,
1649 bool dp_clk_src)
1650{
1651 struct dce110_clk_src *clk_src =
1652 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1653
1654 if (!clk_src)
1655 return NULL;
1656
1657 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1658 regs, &cs_shift, &cs_mask)) {
1659 clk_src->base.dp_clk_src = dp_clk_src;
1660 return &clk_src->base;
1661 }
1662
1663 BREAK_TO_DEBUGGER();
1664 kfree(clk_src);
1665 return NULL;
1666}
1667
1668static int dcn314_populate_dml_pipes_from_context(
1669 struct dc *dc, struct dc_state *context,
1670 display_e2e_pipe_params_st *pipes,
1671 bool fast_validate)
1672{
1673 int pipe_cnt;
1674
1675 DC_FP_START();
1676 pipe_cnt = dcn314_populate_dml_pipes_from_context_fpu(dc, context, pipes, fast_validate);
1677 DC_FP_END();
1678
1679 return pipe_cnt;
1680}
1681
1682static struct dc_cap_funcs cap_funcs = {
1683 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1684};
1685
1686static void dcn314_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1687{
1688 DC_FP_START();
1689 dcn314_update_bw_bounding_box_fpu(dc, bw_params);
1690 DC_FP_END();
1691}
1692
1693static void dcn314_get_panel_config_defaults(struct dc_panel_config *panel_config)
1694{
1695 *panel_config = panel_config_defaults;
1696}
1697
1698static struct resource_funcs dcn314_res_pool_funcs = {
1699 .destroy = dcn314_destroy_resource_pool,
1700 .link_enc_create = dcn31_link_encoder_create,
1701 .link_enc_create_minimal = dcn31_link_enc_create_minimal,
1702 .link_encs_assign = link_enc_cfg_link_encs_assign,
1703 .link_enc_unassign = link_enc_cfg_link_enc_unassign,
1704 .panel_cntl_create = dcn31_panel_cntl_create,
1705 .validate_bandwidth = dcn31_validate_bandwidth,
1706 .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
1707 .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
1708 .populate_dml_pipes = dcn314_populate_dml_pipes_from_context,
1709 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1710 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1711 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1712 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1713 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1714 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1715 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1716 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1717 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1718 .update_bw_bounding_box = dcn314_update_bw_bounding_box,
1719 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1720 .get_panel_config_defaults = dcn314_get_panel_config_defaults,
1721};
1722
1723static struct clock_source *dcn30_clock_source_create(
1724 struct dc_context *ctx,
1725 struct dc_bios *bios,
1726 enum clock_source_id id,
1727 const struct dce110_clk_src_regs *regs,
1728 bool dp_clk_src)
1729{
1730 struct dce110_clk_src *clk_src =
1731 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1732
1733 if (!clk_src)
1734 return NULL;
1735
1736 if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
1737 regs, &cs_shift, &cs_mask)) {
1738 clk_src->base.dp_clk_src = dp_clk_src;
1739 return &clk_src->base;
1740 }
1741
1742 BREAK_TO_DEBUGGER();
1743 kfree(clk_src);
1744 return NULL;
1745}
1746
1747static bool dcn314_resource_construct(
1748 uint8_t num_virtual_links,
1749 struct dc *dc,
1750 struct dcn314_resource_pool *pool)
1751{
1752 int i;
1753 struct dc_context *ctx = dc->ctx;
1754 struct irq_service_init_data init_data;
1755
1756 ctx->dc_bios->regs = &bios_regs;
1757
1758 pool->base.res_cap = &res_cap_dcn314;
1759 pool->base.funcs = &dcn314_res_pool_funcs;
1760
1761 /*************************************************
1762 * Resource + asic cap harcoding *
1763 *************************************************/
1764 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1765 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1766 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1767 dc->caps.max_downscale_ratio = 400;
1768 dc->caps.i2c_speed_in_khz = 100;
1769 dc->caps.i2c_speed_in_khz_hdcp = 100;
1770 dc->caps.max_cursor_size = 256;
1771 dc->caps.min_horizontal_blanking_period = 80;
1772 dc->caps.dmdata_alloc_size = 2048;
1773 dc->caps.max_slave_planes = 2;
1774 dc->caps.max_slave_yuv_planes = 2;
1775 dc->caps.max_slave_rgb_planes = 2;
1776 dc->caps.post_blend_color_processing = true;
1777 dc->caps.force_dp_tps4_for_cp2520 = true;
1778 if (dc->config.forceHBR2CP2520)
1779 dc->caps.force_dp_tps4_for_cp2520 = false;
1780 dc->caps.dp_hpo = true;
1781 dc->caps.dp_hdmi21_pcon_support = true;
1782 dc->caps.edp_dsc_support = true;
1783 dc->caps.extended_aux_timeout_support = true;
1784 dc->caps.dmcub_support = true;
1785 dc->caps.is_apu = true;
1786 dc->caps.seamless_odm = true;
1787
1788 dc->caps.zstate_support = true;
1789
1790 /* Color pipeline capabilities */
1791 dc->caps.color.dpp.dcn_arch = 1;
1792 dc->caps.color.dpp.input_lut_shared = 0;
1793 dc->caps.color.dpp.icsc = 1;
1794 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1795 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1796 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1797 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1798 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1799 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1800 dc->caps.color.dpp.post_csc = 1;
1801 dc->caps.color.dpp.gamma_corr = 1;
1802 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1803
1804 dc->caps.color.dpp.hw_3d_lut = 1;
1805 dc->caps.color.dpp.ogam_ram = 1;
1806 // no OGAM ROM on DCN301
1807 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1808 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1809 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1810 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1811 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1812 dc->caps.color.dpp.ocsc = 0;
1813
1814 dc->caps.color.mpc.gamut_remap = 1;
1815 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
1816 dc->caps.color.mpc.ogam_ram = 1;
1817 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1818 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1819 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1820 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1821 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1822 dc->caps.color.mpc.ocsc = 1;
1823
1824 /* Use pipe context based otg sync logic */
1825 dc->config.use_pipe_ctx_sync_logic = true;
1826
1827 /* read VBIOS LTTPR caps */
1828 {
1829 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1830 enum bp_result bp_query_result;
1831 uint8_t is_vbios_lttpr_enable = 0;
1832
1833 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1834 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1835 }
1836
1837 /* interop bit is implicit */
1838 {
1839 dc->caps.vbios_lttpr_aware = true;
1840 }
1841 }
1842
1843 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1844 dc->debug = debug_defaults_drv;
1845 else
1846 dc->debug = debug_defaults_diags;
1847 // Init the vm_helper
1848 if (dc->vm_helper)
1849 vm_helper_init(dc->vm_helper, 16);
1850
1851 /*************************************************
1852 * Create resources *
1853 *************************************************/
1854
1855 /* Clock Sources for Pixel Clock*/
1856 pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
1857 dcn30_clock_source_create(ctx, ctx->dc_bios,
1858 CLOCK_SOURCE_COMBO_PHY_PLL0,
1859 &clk_src_regs[0], false);
1860 pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
1861 dcn30_clock_source_create(ctx, ctx->dc_bios,
1862 CLOCK_SOURCE_COMBO_PHY_PLL1,
1863 &clk_src_regs[1], false);
1864 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
1865 dcn30_clock_source_create(ctx, ctx->dc_bios,
1866 CLOCK_SOURCE_COMBO_PHY_PLL2,
1867 &clk_src_regs[2], false);
1868 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
1869 dcn30_clock_source_create(ctx, ctx->dc_bios,
1870 CLOCK_SOURCE_COMBO_PHY_PLL3,
1871 &clk_src_regs[3], false);
1872 pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
1873 dcn30_clock_source_create(ctx, ctx->dc_bios,
1874 CLOCK_SOURCE_COMBO_PHY_PLL4,
1875 &clk_src_regs[4], false);
1876
1877 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
1878
1879 /* todo: not reuse phy_pll registers */
1880 pool->base.dp_clock_source =
1881 dcn31_clock_source_create(ctx, ctx->dc_bios,
1882 CLOCK_SOURCE_ID_DP_DTO,
1883 &clk_src_regs[0], true);
1884
1885 for (i = 0; i < pool->base.clk_src_count; i++) {
1886 if (pool->base.clock_sources[i] == NULL) {
1887 dm_error("DC: failed to create clock sources!\n");
1888 BREAK_TO_DEBUGGER();
1889 goto create_fail;
1890 }
1891 }
1892
1893 pool->base.dccg = dccg314_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1894 if (pool->base.dccg == NULL) {
1895 dm_error("DC: failed to create dccg!\n");
1896 BREAK_TO_DEBUGGER();
1897 goto create_fail;
1898 }
1899
1900 init_data.ctx = dc->ctx;
1901 pool->base.irqs = dal_irq_service_dcn314_create(&init_data);
1902 if (!pool->base.irqs)
1903 goto create_fail;
1904
1905 /* HUBBUB */
1906 pool->base.hubbub = dcn31_hubbub_create(ctx);
1907 if (pool->base.hubbub == NULL) {
1908 BREAK_TO_DEBUGGER();
1909 dm_error("DC: failed to create hubbub!\n");
1910 goto create_fail;
1911 }
1912
1913 /* HUBPs, DPPs, OPPs and TGs */
1914 for (i = 0; i < pool->base.pipe_count; i++) {
1915 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
1916 if (pool->base.hubps[i] == NULL) {
1917 BREAK_TO_DEBUGGER();
1918 dm_error(
1919 "DC: failed to create hubps!\n");
1920 goto create_fail;
1921 }
1922
1923 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
1924 if (pool->base.dpps[i] == NULL) {
1925 BREAK_TO_DEBUGGER();
1926 dm_error(
1927 "DC: failed to create dpps!\n");
1928 goto create_fail;
1929 }
1930 }
1931
1932 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1933 pool->base.opps[i] = dcn31_opp_create(ctx, i);
1934 if (pool->base.opps[i] == NULL) {
1935 BREAK_TO_DEBUGGER();
1936 dm_error(
1937 "DC: failed to create output pixel processor!\n");
1938 goto create_fail;
1939 }
1940 }
1941
1942 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1943 pool->base.timing_generators[i] = dcn31_timing_generator_create(
1944 ctx, i);
1945 if (pool->base.timing_generators[i] == NULL) {
1946 BREAK_TO_DEBUGGER();
1947 dm_error("DC: failed to create tg!\n");
1948 goto create_fail;
1949 }
1950 }
1951 pool->base.timing_generator_count = i;
1952
1953 /* PSR */
1954 pool->base.psr = dmub_psr_create(ctx);
1955 if (pool->base.psr == NULL) {
1956 dm_error("DC: failed to create psr obj!\n");
1957 BREAK_TO_DEBUGGER();
1958 goto create_fail;
1959 }
1960
1961 /* ABM */
1962 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1963 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1964 &abm_regs[i],
1965 &abm_shift,
1966 &abm_mask);
1967 if (pool->base.multiple_abms[i] == NULL) {
1968 dm_error("DC: failed to create abm for pipe %d!\n", i);
1969 BREAK_TO_DEBUGGER();
1970 goto create_fail;
1971 }
1972 }
1973
1974 /* MPC and DSC */
1975 pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1976 if (pool->base.mpc == NULL) {
1977 BREAK_TO_DEBUGGER();
1978 dm_error("DC: failed to create mpc!\n");
1979 goto create_fail;
1980 }
1981
1982 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1983 pool->base.dscs[i] = dcn314_dsc_create(ctx, i);
1984 if (pool->base.dscs[i] == NULL) {
1985 BREAK_TO_DEBUGGER();
1986 dm_error("DC: failed to create display stream compressor %d!\n", i);
1987 goto create_fail;
1988 }
1989 }
1990
1991 /* DWB and MMHUBBUB */
1992 if (!dcn31_dwbc_create(ctx, &pool->base)) {
1993 BREAK_TO_DEBUGGER();
1994 dm_error("DC: failed to create dwbc!\n");
1995 goto create_fail;
1996 }
1997
1998 if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
1999 BREAK_TO_DEBUGGER();
2000 dm_error("DC: failed to create mcif_wb!\n");
2001 goto create_fail;
2002 }
2003
2004 /* AUX and I2C */
2005 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2006 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2007 if (pool->base.engines[i] == NULL) {
2008 BREAK_TO_DEBUGGER();
2009 dm_error(
2010 "DC:failed to create aux engine!!\n");
2011 goto create_fail;
2012 }
2013 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2014 if (pool->base.hw_i2cs[i] == NULL) {
2015 BREAK_TO_DEBUGGER();
2016 dm_error(
2017 "DC:failed to create hw i2c!!\n");
2018 goto create_fail;
2019 }
2020 pool->base.sw_i2cs[i] = NULL;
2021 }
2022
2023 /* DCN314 has 4 DPIA */
2024 pool->base.usb4_dpia_count = 4;
2025
2026 /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2027 if (!resource_construct(num_virtual_links, dc, &pool->base,
2028 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2029 &res_create_funcs : &res_create_maximus_funcs)))
2030 goto create_fail;
2031
2032 /* HW Sequencer and Plane caps */
2033 dcn314_hw_sequencer_construct(dc);
2034
2035 dc->caps.max_planes = pool->base.pipe_count;
2036
2037 for (i = 0; i < dc->caps.max_planes; ++i)
2038 dc->caps.planes[i] = plane_cap;
2039
2040 dc->cap_funcs = cap_funcs;
2041
2042 dc->dcn_ip->max_num_dpp = dcn3_14_ip.max_num_dpp;
2043
2044 return true;
2045
2046create_fail:
2047
2048 dcn314_resource_destruct(pool);
2049
2050 return false;
2051}
2052
2053struct resource_pool *dcn314_create_resource_pool(
2054 const struct dc_init_data *init_data,
2055 struct dc *dc)
2056{
2057 struct dcn314_resource_pool *pool =
2058 kzalloc(sizeof(struct dcn314_resource_pool), GFP_KERNEL);
2059
2060 if (!pool)
2061 return NULL;
2062
2063 if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
2064 return &pool->base;
2065
2066 BREAK_TO_DEBUGGER();
2067 kfree(pool);
2068 return NULL;
2069}