1/*
  2 * Copyright 2016-2020 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#include "dce110/dce110_hw_sequencer.h"
 27#include "dcn10/dcn10_hw_sequencer.h"
 28#include "dcn20/dcn20_hwseq.h"
 29#include "dcn21_hwseq.h"
 30
 31#include "dcn21_init.h"
 32
 33static const struct hw_sequencer_funcs dcn21_funcs = {
 34	.program_gamut_remap = dcn10_program_gamut_remap,
 35	.init_hw = dcn10_init_hw,
 36	.power_down_on_boot = dcn10_power_down_on_boot,
 37	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 38	.apply_ctx_for_surface = NULL,
 39	.program_front_end_for_ctx = dcn20_program_front_end_for_ctx,
 40	.wait_for_pending_cleared = dcn10_wait_for_pending_cleared,
 41	.post_unlock_program_front_end = dcn20_post_unlock_program_front_end,
 42	.update_plane_addr = dcn20_update_plane_addr,
 43	.update_dchub = dcn10_update_dchub,
 44	.update_pending_status = dcn10_update_pending_status,
 45	.program_output_csc = dcn20_program_output_csc,
 46	.enable_accelerated_mode = dce110_enable_accelerated_mode,
 47	.enable_timing_synchronization = dcn10_enable_timing_synchronization,
 48	.enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
 49	.update_info_frame = dce110_update_info_frame,
 50	.send_immediate_sdp_message = dcn10_send_immediate_sdp_message,
 51	.enable_stream = dcn20_enable_stream,
 52	.disable_stream = dce110_disable_stream,
 53	.unblank_stream = dcn20_unblank_stream,
 54	.blank_stream = dce110_blank_stream,
 55	.enable_audio_stream = dce110_enable_audio_stream,
 56	.disable_audio_stream = dce110_disable_audio_stream,
 57	.disable_plane = dcn20_disable_plane,
 58	.pipe_control_lock = dcn20_pipe_control_lock,
 59	.interdependent_update_lock = dcn10_lock_all_pipes,
 60	.cursor_lock = dcn10_cursor_lock,
 61	.prepare_bandwidth = dcn20_prepare_bandwidth,
 62	.optimize_bandwidth = dcn20_optimize_bandwidth,
 63	.update_bandwidth = dcn20_update_bandwidth,
 64	.set_drr = dcn10_set_drr,
 65	.get_position = dcn10_get_position,
 66	.set_static_screen_control = dcn10_set_static_screen_control,
 67	.setup_stereo = dcn10_setup_stereo,
 68	.set_avmute = dce110_set_avmute,
 69	.log_hw_state = dcn10_log_hw_state,
 70	.get_hw_state = dcn10_get_hw_state,
 71	.clear_status_bits = dcn10_clear_status_bits,
 72	.wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
 73	.edp_backlight_control = dce110_edp_backlight_control,
 74	.edp_power_control = dce110_edp_power_control,
 75	.edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
 76	.set_cursor_position = dcn10_set_cursor_position,
 77	.set_cursor_attribute = dcn10_set_cursor_attribute,
 78	.set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
 79	.setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
 80	.set_clock = dcn10_set_clock,
 81	.get_clock = dcn10_get_clock,
 82	.program_triplebuffer = dcn20_program_triple_buffer,
 83	.enable_writeback = dcn20_enable_writeback,
 84	.disable_writeback = dcn20_disable_writeback,
 85	.dmdata_status_done = dcn20_dmdata_status_done,
 86	.program_dmdata_engine = dcn20_program_dmdata_engine,
 87	.set_dmdata_attributes = dcn20_set_dmdata_attributes,
 88	.init_sys_ctx = dcn21_init_sys_ctx,
 89	.init_vm_ctx = dcn20_init_vm_ctx,
 90	.set_flip_control_gsl = dcn20_set_flip_control_gsl,
 91	.optimize_pwr_state = dcn21_optimize_pwr_state,
 92	.exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state,
 93	.get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync,
 94	.calc_vupdate_position = dcn10_calc_vupdate_position,
 95	.power_down = dce110_power_down,
 96	.set_backlight_level = dcn21_set_backlight_level,
 97	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
 98	.set_pipe = dcn21_set_pipe,
 99#ifndef TRIM_FSFT
100	.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
101#endif
102	.enable_lvds_link_output = dce110_enable_lvds_link_output,
103	.enable_tmds_link_output = dce110_enable_tmds_link_output,
104	.enable_dp_link_output = dce110_enable_dp_link_output,
105	.disable_link_output = dce110_disable_link_output,
106	.is_abm_supported = dcn21_is_abm_supported,
107	.set_disp_pattern_generator = dcn20_set_disp_pattern_generator,
108	.get_dcc_en_bits = dcn10_get_dcc_en_bits,
109	.update_visual_confirm_color = dcn20_update_visual_confirm_color,
110};
111
112static const struct hwseq_private_funcs dcn21_private_funcs = {
113	.init_pipes = dcn10_init_pipes,
114	.update_plane_addr = dcn20_update_plane_addr,
115	.plane_atomic_disconnect = dcn10_plane_atomic_disconnect,
116	.update_mpcc = dcn20_update_mpcc,
117	.set_input_transfer_func = dcn20_set_input_transfer_func,
118	.set_output_transfer_func = dcn20_set_output_transfer_func,
119	.power_down = dce110_power_down,
120	.enable_display_power_gating = dcn10_dummy_display_power_gating,
121	.blank_pixel_data = dcn20_blank_pixel_data,
122	.reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap,
123	.enable_stream_timing = dcn20_enable_stream_timing,
124	.edp_backlight_control = dce110_edp_backlight_control,
125	.disable_stream_gating = dcn20_disable_stream_gating,
126	.enable_stream_gating = dcn20_enable_stream_gating,
127	.setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt,
128	.did_underflow_occur = dcn10_did_underflow_occur,
129	.init_blank = dcn20_init_blank,
130	.disable_vga = dcn20_disable_vga,
131	.bios_golden_init = dcn10_bios_golden_init,
132	.plane_atomic_disable = dcn20_plane_atomic_disable,
133	.plane_atomic_power_down = dcn10_plane_atomic_power_down,
134	.enable_power_gating_plane = dcn20_enable_power_gating_plane,
135	.dpp_pg_control = dcn20_dpp_pg_control,
136	.hubp_pg_control = dcn20_hubp_pg_control,
137	.update_odm = dcn20_update_odm,
138	.dsc_pg_control = dcn20_dsc_pg_control,
139	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
140	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
141	.s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa,
142	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
143	.dccg_init = dcn20_dccg_init,
144	.set_blend_lut = dcn20_set_blend_lut,
145	.set_shaper_3dlut = dcn20_set_shaper_3dlut,
146	.PLAT_58856_wa = dcn21_PLAT_58856_wa,
147};
148
149void dcn21_hw_sequencer_construct(struct dc *dc)
150{
151	dc->hwss = dcn21_funcs;
152	dc->hwseq->funcs = dcn21_private_funcs;
153
154	if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
155		dc->hwss.init_hw = dcn20_fpga_init_hw;
156		dc->hwseq->funcs.init_pipes = NULL;
157	}
158}