1// SPDX-License-Identifier: GPL-2.0 OR MIT
   2/*
   3 * Copyright 2015-2022 Advanced Micro Devices, Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 */
  23
  24#include <linux/pci.h>
  25#include <linux/acpi.h>
  26#include "kfd_crat.h"
  27#include "kfd_priv.h"
  28#include "kfd_topology.h"
 
  29#include "amdgpu.h"
  30#include "amdgpu_amdkfd.h"
  31
  32/* GPU Processor ID base for dGPUs for which VCRAT needs to be created.
  33 * GPU processor ID are expressed with Bit[31]=1.
  34 * The base is set to 0x8000_0000 + 0x1000 to avoid collision with GPU IDs
  35 * used in the CRAT.
  36 */
  37static uint32_t gpu_processor_id_low = 0x80001000;
  38
  39/* Return the next available gpu_processor_id and increment it for next GPU
  40 *	@total_cu_count - Total CUs present in the GPU including ones
  41 *			  masked off
  42 */
  43static inline unsigned int get_and_inc_gpu_processor_id(
  44				unsigned int total_cu_count)
  45{
  46	int current_id = gpu_processor_id_low;
  47
  48	gpu_processor_id_low += total_cu_count;
  49	return current_id;
  50}
  51
  52
  53static struct kfd_gpu_cache_info kaveri_cache_info[] = {
  54	{
  55		/* TCP L1 Cache per CU */
  56		.cache_size = 16,
  57		.cache_level = 1,
  58		.cache_line_size = 64,
  59		.flags = (CRAT_CACHE_FLAGS_ENABLED |
  60				CRAT_CACHE_FLAGS_DATA_CACHE |
  61				CRAT_CACHE_FLAGS_SIMD_CACHE),
  62		.num_cu_shared = 1,
  63	},
  64	{
  65		/* Scalar L1 Instruction Cache (in SQC module) per bank */
  66		.cache_size = 16,
  67		.cache_level = 1,
  68		.cache_line_size = 64,
  69		.flags = (CRAT_CACHE_FLAGS_ENABLED |
  70				CRAT_CACHE_FLAGS_INST_CACHE |
  71				CRAT_CACHE_FLAGS_SIMD_CACHE),
  72		.num_cu_shared = 2,
  73	},
  74	{
  75		/* Scalar L1 Data Cache (in SQC module) per bank */
  76		.cache_size = 8,
  77		.cache_level = 1,
  78		.cache_line_size = 64,
  79		.flags = (CRAT_CACHE_FLAGS_ENABLED |
  80				CRAT_CACHE_FLAGS_DATA_CACHE |
  81				CRAT_CACHE_FLAGS_SIMD_CACHE),
  82		.num_cu_shared = 2,
  83	},
  84
  85	/* TODO: Add L2 Cache information */
  86};
  87
  88
  89static struct kfd_gpu_cache_info carrizo_cache_info[] = {
  90	{
  91		/* TCP L1 Cache per CU */
  92		.cache_size = 16,
  93		.cache_level = 1,
  94		.cache_line_size = 64,
  95		.flags = (CRAT_CACHE_FLAGS_ENABLED |
  96				CRAT_CACHE_FLAGS_DATA_CACHE |
  97				CRAT_CACHE_FLAGS_SIMD_CACHE),
  98		.num_cu_shared = 1,
  99	},
 100	{
 101		/* Scalar L1 Instruction Cache (in SQC module) per bank */
 102		.cache_size = 32,
 103		.cache_level = 1,
 104		.cache_line_size = 64,
 105		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 106				CRAT_CACHE_FLAGS_INST_CACHE |
 107				CRAT_CACHE_FLAGS_SIMD_CACHE),
 108		.num_cu_shared = 4,
 109	},
 110	{
 111		/* Scalar L1 Data Cache (in SQC module) per bank. */
 112		.cache_size = 16,
 113		.cache_level = 1,
 114		.cache_line_size = 64,
 115		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 116				CRAT_CACHE_FLAGS_DATA_CACHE |
 117				CRAT_CACHE_FLAGS_SIMD_CACHE),
 118		.num_cu_shared = 4,
 119	},
 120
 121	/* TODO: Add L2 Cache information */
 122};
 123
 124#define hawaii_cache_info kaveri_cache_info
 125#define tonga_cache_info carrizo_cache_info
 126#define fiji_cache_info  carrizo_cache_info
 127#define polaris10_cache_info carrizo_cache_info
 128#define polaris11_cache_info carrizo_cache_info
 129#define polaris12_cache_info carrizo_cache_info
 130#define vegam_cache_info carrizo_cache_info
 131
 132/* NOTE: L1 cache information has been updated and L2/L3
 133 * cache information has been added for Vega10 and
 134 * newer ASICs. The unit for cache_size is KiB.
 135 * In future,  check & update cache details
 136 * for every new ASIC is required.
 137 */
 138
 139static struct kfd_gpu_cache_info vega10_cache_info[] = {
 140	{
 141		/* TCP L1 Cache per CU */
 142		.cache_size = 16,
 143		.cache_level = 1,
 144		.cache_line_size = 64,
 145		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 146				CRAT_CACHE_FLAGS_DATA_CACHE |
 147				CRAT_CACHE_FLAGS_SIMD_CACHE),
 148		.num_cu_shared = 1,
 149	},
 150	{
 151		/* Scalar L1 Instruction Cache per SQC */
 152		.cache_size = 32,
 153		.cache_level = 1,
 154		.cache_line_size = 64,
 155		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 156				CRAT_CACHE_FLAGS_INST_CACHE |
 157				CRAT_CACHE_FLAGS_SIMD_CACHE),
 158		.num_cu_shared = 3,
 159	},
 160	{
 161		/* Scalar L1 Data Cache per SQC */
 162		.cache_size = 16,
 163		.cache_level = 1,
 164		.cache_line_size = 64,
 165		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 166				CRAT_CACHE_FLAGS_DATA_CACHE |
 167				CRAT_CACHE_FLAGS_SIMD_CACHE),
 168		.num_cu_shared = 3,
 169	},
 170	{
 171		/* L2 Data Cache per GPU (Total Tex Cache) */
 172		.cache_size = 4096,
 173		.cache_level = 2,
 174		.cache_line_size = 64,
 175		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 176				CRAT_CACHE_FLAGS_DATA_CACHE |
 177				CRAT_CACHE_FLAGS_SIMD_CACHE),
 178		.num_cu_shared = 16,
 179	},
 180};
 181
 182static struct kfd_gpu_cache_info raven_cache_info[] = {
 183	{
 184		/* TCP L1 Cache per CU */
 185		.cache_size = 16,
 186		.cache_level = 1,
 187		.cache_line_size = 64,
 188		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 189				CRAT_CACHE_FLAGS_DATA_CACHE |
 190				CRAT_CACHE_FLAGS_SIMD_CACHE),
 191		.num_cu_shared = 1,
 192	},
 193	{
 194		/* Scalar L1 Instruction Cache per SQC */
 195		.cache_size = 32,
 196		.cache_level = 1,
 197		.cache_line_size = 64,
 198		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 199				CRAT_CACHE_FLAGS_INST_CACHE |
 200				CRAT_CACHE_FLAGS_SIMD_CACHE),
 201		.num_cu_shared = 3,
 202	},
 203	{
 204		/* Scalar L1 Data Cache per SQC */
 205		.cache_size = 16,
 206		.cache_level = 1,
 207		.cache_line_size = 64,
 208		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 209				CRAT_CACHE_FLAGS_DATA_CACHE |
 210				CRAT_CACHE_FLAGS_SIMD_CACHE),
 211		.num_cu_shared = 3,
 212	},
 213	{
 214		/* L2 Data Cache per GPU (Total Tex Cache) */
 215		.cache_size = 1024,
 216		.cache_level = 2,
 217		.cache_line_size = 64,
 218		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 219				CRAT_CACHE_FLAGS_DATA_CACHE |
 220				CRAT_CACHE_FLAGS_SIMD_CACHE),
 221		.num_cu_shared = 11,
 222	},
 223};
 224
 225static struct kfd_gpu_cache_info renoir_cache_info[] = {
 226	{
 227		/* TCP L1 Cache per CU */
 228		.cache_size = 16,
 229		.cache_level = 1,
 230		.cache_line_size = 64,
 231		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 232				CRAT_CACHE_FLAGS_DATA_CACHE |
 233				CRAT_CACHE_FLAGS_SIMD_CACHE),
 234		.num_cu_shared = 1,
 235	},
 236	{
 237		/* Scalar L1 Instruction Cache per SQC */
 238		.cache_size = 32,
 239		.cache_level = 1,
 240		.cache_line_size = 64,
 241		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 242				CRAT_CACHE_FLAGS_INST_CACHE |
 243				CRAT_CACHE_FLAGS_SIMD_CACHE),
 244		.num_cu_shared = 3,
 245	},
 246	{
 247		/* Scalar L1 Data Cache per SQC */
 248		.cache_size = 16,
 249		.cache_level = 1,
 250		.cache_line_size = 64,
 251		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 252				CRAT_CACHE_FLAGS_DATA_CACHE |
 253				CRAT_CACHE_FLAGS_SIMD_CACHE),
 254		.num_cu_shared = 3,
 255	},
 256	{
 257		/* L2 Data Cache per GPU (Total Tex Cache) */
 258		.cache_size = 1024,
 259		.cache_level = 2,
 260		.cache_line_size = 64,
 261		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 262				CRAT_CACHE_FLAGS_DATA_CACHE |
 263				CRAT_CACHE_FLAGS_SIMD_CACHE),
 264		.num_cu_shared = 8,
 265	},
 266};
 267
 268static struct kfd_gpu_cache_info vega12_cache_info[] = {
 269	{
 270		/* TCP L1 Cache per CU */
 271		.cache_size = 16,
 272		.cache_level = 1,
 273		.cache_line_size = 64,
 274		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 275				CRAT_CACHE_FLAGS_DATA_CACHE |
 276				CRAT_CACHE_FLAGS_SIMD_CACHE),
 277		.num_cu_shared = 1,
 278	},
 279	{
 280		/* Scalar L1 Instruction Cache per SQC */
 281		.cache_size = 32,
 282		.cache_level = 1,
 283		.cache_line_size = 64,
 284		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 285				CRAT_CACHE_FLAGS_INST_CACHE |
 286				CRAT_CACHE_FLAGS_SIMD_CACHE),
 287		.num_cu_shared = 3,
 288	},
 289	{
 290		/* Scalar L1 Data Cache per SQC */
 291		.cache_size = 16,
 292		.cache_level = 1,
 293		.cache_line_size = 64,
 294		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 295				CRAT_CACHE_FLAGS_DATA_CACHE |
 296				CRAT_CACHE_FLAGS_SIMD_CACHE),
 297		.num_cu_shared = 3,
 298	},
 299	{
 300		/* L2 Data Cache per GPU (Total Tex Cache) */
 301		.cache_size = 2048,
 302		.cache_level = 2,
 303		.cache_line_size = 64,
 304		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 305				CRAT_CACHE_FLAGS_DATA_CACHE |
 306				CRAT_CACHE_FLAGS_SIMD_CACHE),
 307		.num_cu_shared = 5,
 308	},
 309};
 310
 311static struct kfd_gpu_cache_info vega20_cache_info[] = {
 312	{
 313		/* TCP L1 Cache per CU */
 314		.cache_size = 16,
 315		.cache_level = 1,
 316		.cache_line_size = 64,
 317		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 318				CRAT_CACHE_FLAGS_DATA_CACHE |
 319				CRAT_CACHE_FLAGS_SIMD_CACHE),
 320		.num_cu_shared = 1,
 321	},
 322	{
 323		/* Scalar L1 Instruction Cache per SQC */
 324		.cache_size = 32,
 325		.cache_level = 1,
 326		.cache_line_size = 64,
 327		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 328				CRAT_CACHE_FLAGS_INST_CACHE |
 329				CRAT_CACHE_FLAGS_SIMD_CACHE),
 330		.num_cu_shared = 3,
 331	},
 332	{
 333		/* Scalar L1 Data Cache per SQC */
 334		.cache_size = 16,
 335		.cache_level = 1,
 336		.cache_line_size = 64,
 337		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 338				CRAT_CACHE_FLAGS_DATA_CACHE |
 339				CRAT_CACHE_FLAGS_SIMD_CACHE),
 340		.num_cu_shared = 3,
 341	},
 342	{
 343		/* L2 Data Cache per GPU (Total Tex Cache) */
 344		.cache_size = 8192,
 345		.cache_level = 2,
 346		.cache_line_size = 64,
 347		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 348				CRAT_CACHE_FLAGS_DATA_CACHE |
 349				CRAT_CACHE_FLAGS_SIMD_CACHE),
 350		.num_cu_shared = 16,
 351	},
 352};
 353
 354static struct kfd_gpu_cache_info aldebaran_cache_info[] = {
 355	{
 356		/* TCP L1 Cache per CU */
 357		.cache_size = 16,
 358		.cache_level = 1,
 359		.cache_line_size = 64,
 360		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 361				CRAT_CACHE_FLAGS_DATA_CACHE |
 362				CRAT_CACHE_FLAGS_SIMD_CACHE),
 363		.num_cu_shared = 1,
 364	},
 365	{
 366		/* Scalar L1 Instruction Cache per SQC */
 367		.cache_size = 32,
 368		.cache_level = 1,
 369		.cache_line_size = 64,
 370		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 371				CRAT_CACHE_FLAGS_INST_CACHE |
 372				CRAT_CACHE_FLAGS_SIMD_CACHE),
 373		.num_cu_shared = 2,
 374	},
 375	{
 376		/* Scalar L1 Data Cache per SQC */
 377		.cache_size = 16,
 378		.cache_level = 1,
 379		.cache_line_size = 64,
 380		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 381				CRAT_CACHE_FLAGS_DATA_CACHE |
 382				CRAT_CACHE_FLAGS_SIMD_CACHE),
 383		.num_cu_shared = 2,
 384	},
 385	{
 386		/* L2 Data Cache per GPU (Total Tex Cache) */
 387		.cache_size = 8192,
 388		.cache_level = 2,
 389		.cache_line_size = 128,
 390		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 391				CRAT_CACHE_FLAGS_DATA_CACHE |
 392				CRAT_CACHE_FLAGS_SIMD_CACHE),
 393		.num_cu_shared = 14,
 394	},
 395};
 396
 397static struct kfd_gpu_cache_info navi10_cache_info[] = {
 398	{
 399		/* TCP L1 Cache per CU */
 400		.cache_size = 16,
 401		.cache_level = 1,
 402		.cache_line_size = 128,
 403		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 404				CRAT_CACHE_FLAGS_DATA_CACHE |
 405				CRAT_CACHE_FLAGS_SIMD_CACHE),
 406		.num_cu_shared = 1,
 407	},
 408	{
 409		/* Scalar L1 Instruction Cache per SQC */
 410		.cache_size = 32,
 411		.cache_level = 1,
 412		.cache_line_size = 64,
 413		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 414				CRAT_CACHE_FLAGS_INST_CACHE |
 415				CRAT_CACHE_FLAGS_SIMD_CACHE),
 416		.num_cu_shared = 2,
 417	},
 418	{
 419		/* Scalar L1 Data Cache per SQC */
 420		.cache_size = 16,
 421		.cache_level = 1,
 422		.cache_line_size = 64,
 423		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 424				CRAT_CACHE_FLAGS_DATA_CACHE |
 425				CRAT_CACHE_FLAGS_SIMD_CACHE),
 426		.num_cu_shared = 2,
 427	},
 428	{
 429		/* GL1 Data Cache per SA */
 430		.cache_size = 128,
 431		.cache_level = 1,
 432		.cache_line_size = 128,
 433		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 434				CRAT_CACHE_FLAGS_DATA_CACHE |
 435				CRAT_CACHE_FLAGS_SIMD_CACHE),
 436		.num_cu_shared = 10,
 437	},
 438	{
 439		/* L2 Data Cache per GPU (Total Tex Cache) */
 440		.cache_size = 4096,
 441		.cache_level = 2,
 442		.cache_line_size = 128,
 443		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 444				CRAT_CACHE_FLAGS_DATA_CACHE |
 445				CRAT_CACHE_FLAGS_SIMD_CACHE),
 446		.num_cu_shared = 10,
 447	},
 448};
 449
 450static struct kfd_gpu_cache_info vangogh_cache_info[] = {
 451	{
 452		/* TCP L1 Cache per CU */
 453		.cache_size = 16,
 454		.cache_level = 1,
 455		.cache_line_size = 128,
 456		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 457				CRAT_CACHE_FLAGS_DATA_CACHE |
 458				CRAT_CACHE_FLAGS_SIMD_CACHE),
 459		.num_cu_shared = 1,
 460	},
 461	{
 462		/* Scalar L1 Instruction Cache per SQC */
 463		.cache_size = 32,
 464		.cache_level = 1,
 465		.cache_line_size = 64,
 466		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 467				CRAT_CACHE_FLAGS_INST_CACHE |
 468				CRAT_CACHE_FLAGS_SIMD_CACHE),
 469		.num_cu_shared = 2,
 470	},
 471	{
 472		/* Scalar L1 Data Cache per SQC */
 473		.cache_size = 16,
 474		.cache_level = 1,
 475		.cache_line_size = 64,
 476		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 477				CRAT_CACHE_FLAGS_DATA_CACHE |
 478				CRAT_CACHE_FLAGS_SIMD_CACHE),
 479		.num_cu_shared = 2,
 480	},
 481	{
 482		/* GL1 Data Cache per SA */
 483		.cache_size = 128,
 484		.cache_level = 1,
 485		.cache_line_size = 128,
 486		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 487				CRAT_CACHE_FLAGS_DATA_CACHE |
 488				CRAT_CACHE_FLAGS_SIMD_CACHE),
 489		.num_cu_shared = 8,
 490	},
 491	{
 492		/* L2 Data Cache per GPU (Total Tex Cache) */
 493		.cache_size = 1024,
 494		.cache_level = 2,
 495		.cache_line_size = 128,
 496		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 497				CRAT_CACHE_FLAGS_DATA_CACHE |
 498				CRAT_CACHE_FLAGS_SIMD_CACHE),
 499		.num_cu_shared = 8,
 500	},
 501};
 502
 503static struct kfd_gpu_cache_info navi14_cache_info[] = {
 504	{
 505		/* TCP L1 Cache per CU */
 506		.cache_size = 16,
 507		.cache_level = 1,
 508		.cache_line_size = 128,
 509		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 510				CRAT_CACHE_FLAGS_DATA_CACHE |
 511				CRAT_CACHE_FLAGS_SIMD_CACHE),
 512		.num_cu_shared = 1,
 513	},
 514	{
 515		/* Scalar L1 Instruction Cache per SQC */
 516		.cache_size = 32,
 517		.cache_level = 1,
 518		.cache_line_size = 64,
 519		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 520				CRAT_CACHE_FLAGS_INST_CACHE |
 521				CRAT_CACHE_FLAGS_SIMD_CACHE),
 522		.num_cu_shared = 2,
 523	},
 524	{
 525		/* Scalar L1 Data Cache per SQC */
 526		.cache_size = 16,
 527		.cache_level = 1,
 528		.cache_line_size = 64,
 529		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 530				CRAT_CACHE_FLAGS_DATA_CACHE |
 531				CRAT_CACHE_FLAGS_SIMD_CACHE),
 532		.num_cu_shared = 2,
 533	},
 534	{
 535		/* GL1 Data Cache per SA */
 536		.cache_size = 128,
 537		.cache_level = 1,
 538		.cache_line_size = 128,
 539		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 540				CRAT_CACHE_FLAGS_DATA_CACHE |
 541				CRAT_CACHE_FLAGS_SIMD_CACHE),
 542		.num_cu_shared = 12,
 543	},
 544	{
 545		/* L2 Data Cache per GPU (Total Tex Cache) */
 546		.cache_size = 2048,
 547		.cache_level = 2,
 548		.cache_line_size = 128,
 549		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 550				CRAT_CACHE_FLAGS_DATA_CACHE |
 551				CRAT_CACHE_FLAGS_SIMD_CACHE),
 552		.num_cu_shared = 12,
 553	},
 554};
 555
 556static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = {
 557	{
 558		/* TCP L1 Cache per CU */
 559		.cache_size = 16,
 560		.cache_level = 1,
 561		.cache_line_size = 128,
 562		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 563				CRAT_CACHE_FLAGS_DATA_CACHE |
 564				CRAT_CACHE_FLAGS_SIMD_CACHE),
 565		.num_cu_shared = 1,
 566	},
 567	{
 568		/* Scalar L1 Instruction Cache per SQC */
 569		.cache_size = 32,
 570		.cache_level = 1,
 571		.cache_line_size = 64,
 572		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 573				CRAT_CACHE_FLAGS_INST_CACHE |
 574				CRAT_CACHE_FLAGS_SIMD_CACHE),
 575		.num_cu_shared = 2,
 576	},
 577	{
 578		/* Scalar L1 Data Cache per SQC */
 579		.cache_size = 16,
 580		.cache_level = 1,
 581		.cache_line_size = 64,
 582		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 583				CRAT_CACHE_FLAGS_DATA_CACHE |
 584				CRAT_CACHE_FLAGS_SIMD_CACHE),
 585		.num_cu_shared = 2,
 586	},
 587	{
 588		/* GL1 Data Cache per SA */
 589		.cache_size = 128,
 590		.cache_level = 1,
 591		.cache_line_size = 128,
 592		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 593				CRAT_CACHE_FLAGS_DATA_CACHE |
 594				CRAT_CACHE_FLAGS_SIMD_CACHE),
 595		.num_cu_shared = 10,
 596	},
 597	{
 598		/* L2 Data Cache per GPU (Total Tex Cache) */
 599		.cache_size = 4096,
 600		.cache_level = 2,
 601		.cache_line_size = 128,
 602		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 603				CRAT_CACHE_FLAGS_DATA_CACHE |
 604				CRAT_CACHE_FLAGS_SIMD_CACHE),
 605		.num_cu_shared = 10,
 606	},
 607	{
 608		/* L3 Data Cache per GPU */
 609		.cache_size = 128*1024,
 610		.cache_level = 3,
 611		.cache_line_size = 64,
 612		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 613				CRAT_CACHE_FLAGS_DATA_CACHE |
 614				CRAT_CACHE_FLAGS_SIMD_CACHE),
 615		.num_cu_shared = 10,
 616	},
 617};
 618
 619static struct kfd_gpu_cache_info navy_flounder_cache_info[] = {
 620	{
 621		/* TCP L1 Cache per CU */
 622		.cache_size = 16,
 623		.cache_level = 1,
 624		.cache_line_size = 128,
 625		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 626				CRAT_CACHE_FLAGS_DATA_CACHE |
 627				CRAT_CACHE_FLAGS_SIMD_CACHE),
 628		.num_cu_shared = 1,
 629	},
 630	{
 631		/* Scalar L1 Instruction Cache per SQC */
 632		.cache_size = 32,
 633		.cache_level = 1,
 634		.cache_line_size = 64,
 635		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 636				CRAT_CACHE_FLAGS_INST_CACHE |
 637				CRAT_CACHE_FLAGS_SIMD_CACHE),
 638		.num_cu_shared = 2,
 639	},
 640	{
 641		/* Scalar L1 Data Cache per SQC */
 642		.cache_size = 16,
 643		.cache_level = 1,
 644		.cache_line_size = 64,
 645		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 646				CRAT_CACHE_FLAGS_DATA_CACHE |
 647				CRAT_CACHE_FLAGS_SIMD_CACHE),
 648		.num_cu_shared = 2,
 649	},
 650	{
 651		/* GL1 Data Cache per SA */
 652		.cache_size = 128,
 653		.cache_level = 1,
 654		.cache_line_size = 128,
 655		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 656				CRAT_CACHE_FLAGS_DATA_CACHE |
 657				CRAT_CACHE_FLAGS_SIMD_CACHE),
 658		.num_cu_shared = 10,
 659	},
 660	{
 661		/* L2 Data Cache per GPU (Total Tex Cache) */
 662		.cache_size = 3072,
 663		.cache_level = 2,
 664		.cache_line_size = 128,
 665		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 666				CRAT_CACHE_FLAGS_DATA_CACHE |
 667				CRAT_CACHE_FLAGS_SIMD_CACHE),
 668		.num_cu_shared = 10,
 669	},
 670	{
 671		/* L3 Data Cache per GPU */
 672		.cache_size = 96*1024,
 673		.cache_level = 3,
 674		.cache_line_size = 64,
 675		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 676				CRAT_CACHE_FLAGS_DATA_CACHE |
 677				CRAT_CACHE_FLAGS_SIMD_CACHE),
 678		.num_cu_shared = 10,
 679	},
 680};
 681
 682static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = {
 683	{
 684		/* TCP L1 Cache per CU */
 685		.cache_size = 16,
 686		.cache_level = 1,
 687		.cache_line_size = 128,
 688		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 689				CRAT_CACHE_FLAGS_DATA_CACHE |
 690				CRAT_CACHE_FLAGS_SIMD_CACHE),
 691		.num_cu_shared = 1,
 692	},
 693	{
 694		/* Scalar L1 Instruction Cache per SQC */
 695		.cache_size = 32,
 696		.cache_level = 1,
 697		.cache_line_size = 64,
 698		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 699				CRAT_CACHE_FLAGS_INST_CACHE |
 700				CRAT_CACHE_FLAGS_SIMD_CACHE),
 701		.num_cu_shared = 2,
 702	},
 703	{
 704		/* Scalar L1 Data Cache per SQC */
 705		.cache_size = 16,
 706		.cache_level = 1,
 707		.cache_line_size = 64,
 708		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 709				CRAT_CACHE_FLAGS_DATA_CACHE |
 710				CRAT_CACHE_FLAGS_SIMD_CACHE),
 711		.num_cu_shared = 2,
 712	},
 713	{
 714		/* GL1 Data Cache per SA */
 715		.cache_size = 128,
 716		.cache_level = 1,
 717		.cache_line_size = 128,
 718		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 719				CRAT_CACHE_FLAGS_DATA_CACHE |
 720				CRAT_CACHE_FLAGS_SIMD_CACHE),
 721		.num_cu_shared = 8,
 722	},
 723	{
 724		/* L2 Data Cache per GPU (Total Tex Cache) */
 725		.cache_size = 2048,
 726		.cache_level = 2,
 727		.cache_line_size = 128,
 728		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 729				CRAT_CACHE_FLAGS_DATA_CACHE |
 730				CRAT_CACHE_FLAGS_SIMD_CACHE),
 731		.num_cu_shared = 8,
 732	},
 733	{
 734		/* L3 Data Cache per GPU */
 735		.cache_size = 32*1024,
 736		.cache_level = 3,
 737		.cache_line_size = 64,
 738		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 739				CRAT_CACHE_FLAGS_DATA_CACHE |
 740				CRAT_CACHE_FLAGS_SIMD_CACHE),
 741		.num_cu_shared = 8,
 742	},
 743};
 744
 745static struct kfd_gpu_cache_info beige_goby_cache_info[] = {
 746	{
 747		/* TCP L1 Cache per CU */
 748		.cache_size = 16,
 749		.cache_level = 1,
 750		.cache_line_size = 128,
 751		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 752				CRAT_CACHE_FLAGS_DATA_CACHE |
 753				CRAT_CACHE_FLAGS_SIMD_CACHE),
 754		.num_cu_shared = 1,
 755	},
 756	{
 757		/* Scalar L1 Instruction Cache per SQC */
 758		.cache_size = 32,
 759		.cache_level = 1,
 760		.cache_line_size = 64,
 761		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 762				CRAT_CACHE_FLAGS_INST_CACHE |
 763				CRAT_CACHE_FLAGS_SIMD_CACHE),
 764		.num_cu_shared = 2,
 765	},
 766	{
 767		/* Scalar L1 Data Cache per SQC */
 768		.cache_size = 16,
 769		.cache_level = 1,
 770		.cache_line_size = 64,
 771		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 772				CRAT_CACHE_FLAGS_DATA_CACHE |
 773				CRAT_CACHE_FLAGS_SIMD_CACHE),
 774		.num_cu_shared = 2,
 775	},
 776	{
 777		/* GL1 Data Cache per SA */
 778		.cache_size = 128,
 779		.cache_level = 1,
 780		.cache_line_size = 128,
 781		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 782				CRAT_CACHE_FLAGS_DATA_CACHE |
 783				CRAT_CACHE_FLAGS_SIMD_CACHE),
 784		.num_cu_shared = 8,
 785	},
 786	{
 787		/* L2 Data Cache per GPU (Total Tex Cache) */
 788		.cache_size = 1024,
 789		.cache_level = 2,
 790		.cache_line_size = 128,
 791		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 792				CRAT_CACHE_FLAGS_DATA_CACHE |
 793				CRAT_CACHE_FLAGS_SIMD_CACHE),
 794		.num_cu_shared = 8,
 795	},
 796	{
 797		/* L3 Data Cache per GPU */
 798		.cache_size = 16*1024,
 799		.cache_level = 3,
 800		.cache_line_size = 64,
 801		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 802				CRAT_CACHE_FLAGS_DATA_CACHE |
 803				CRAT_CACHE_FLAGS_SIMD_CACHE),
 804		.num_cu_shared = 8,
 805	},
 806};
 807
 808static struct kfd_gpu_cache_info yellow_carp_cache_info[] = {
 809	{
 810		/* TCP L1 Cache per CU */
 811		.cache_size = 16,
 812		.cache_level = 1,
 813		.cache_line_size = 128,
 814		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 815				CRAT_CACHE_FLAGS_DATA_CACHE |
 816				CRAT_CACHE_FLAGS_SIMD_CACHE),
 817		.num_cu_shared = 1,
 818	},
 819	{
 820		/* Scalar L1 Instruction Cache per SQC */
 821		.cache_size = 32,
 822		.cache_level = 1,
 823		.cache_line_size = 64,
 824		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 825				CRAT_CACHE_FLAGS_INST_CACHE |
 826				CRAT_CACHE_FLAGS_SIMD_CACHE),
 827		.num_cu_shared = 2,
 828	},
 829	{
 830		/* Scalar L1 Data Cache per SQC */
 831		.cache_size = 16,
 832		.cache_level = 1,
 833		.cache_line_size = 64,
 834		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 835				CRAT_CACHE_FLAGS_DATA_CACHE |
 836				CRAT_CACHE_FLAGS_SIMD_CACHE),
 837		.num_cu_shared = 2,
 838	},
 839	{
 840		/* GL1 Data Cache per SA */
 841		.cache_size = 128,
 842		.cache_level = 1,
 843		.cache_line_size = 128,
 844		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 845				CRAT_CACHE_FLAGS_DATA_CACHE |
 846				CRAT_CACHE_FLAGS_SIMD_CACHE),
 847		.num_cu_shared = 6,
 848	},
 849	{
 850		/* L2 Data Cache per GPU (Total Tex Cache) */
 851		.cache_size = 2048,
 852		.cache_level = 2,
 853		.cache_line_size = 128,
 854		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 855				CRAT_CACHE_FLAGS_DATA_CACHE |
 856				CRAT_CACHE_FLAGS_SIMD_CACHE),
 857		.num_cu_shared = 6,
 858	},
 859};
 860
 861static struct kfd_gpu_cache_info gfx1037_cache_info[] = {
 862	{
 863		/* TCP L1 Cache per CU */
 864		.cache_size = 16,
 865		.cache_level = 1,
 866		.cache_line_size = 128,
 867		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 868				CRAT_CACHE_FLAGS_DATA_CACHE |
 869				CRAT_CACHE_FLAGS_SIMD_CACHE),
 870		.num_cu_shared = 1,
 871	},
 872	{
 873		/* Scalar L1 Instruction Cache per SQC */
 874		.cache_size = 32,
 875		.cache_level = 1,
 876		.cache_line_size = 64,
 877		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 878				CRAT_CACHE_FLAGS_INST_CACHE |
 879				CRAT_CACHE_FLAGS_SIMD_CACHE),
 880		.num_cu_shared = 2,
 881	},
 882	{
 883		/* Scalar L1 Data Cache per SQC */
 884		.cache_size = 16,
 885		.cache_level = 1,
 886		.cache_line_size = 64,
 887		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 888				CRAT_CACHE_FLAGS_DATA_CACHE |
 889				CRAT_CACHE_FLAGS_SIMD_CACHE),
 890		.num_cu_shared = 2,
 891	},
 892	{
 893		/* GL1 Data Cache per SA */
 894		.cache_size = 128,
 895		.cache_level = 1,
 896		.cache_line_size = 128,
 897		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 898				CRAT_CACHE_FLAGS_DATA_CACHE |
 899				CRAT_CACHE_FLAGS_SIMD_CACHE),
 900		.num_cu_shared = 2,
 901	},
 902	{
 903		/* L2 Data Cache per GPU (Total Tex Cache) */
 904		.cache_size = 256,
 905		.cache_level = 2,
 906		.cache_line_size = 128,
 907		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 908				CRAT_CACHE_FLAGS_DATA_CACHE |
 909				CRAT_CACHE_FLAGS_SIMD_CACHE),
 910		.num_cu_shared = 2,
 911	},
 912};
 913
 914static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = {
 915	{
 916		/* TCP L1 Cache per CU */
 917		.cache_size = 16,
 918		.cache_level = 1,
 919		.cache_line_size = 128,
 920		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 921			  CRAT_CACHE_FLAGS_DATA_CACHE |
 922			  CRAT_CACHE_FLAGS_SIMD_CACHE),
 923		.num_cu_shared = 1,
 924	},
 925	{
 926		/* Scalar L1 Instruction Cache per SQC */
 927		.cache_size = 32,
 928		.cache_level = 1,
 929		.cache_line_size = 64,
 930		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 931			  CRAT_CACHE_FLAGS_INST_CACHE |
 932			  CRAT_CACHE_FLAGS_SIMD_CACHE),
 933		.num_cu_shared = 2,
 934	},
 935	{
 936		/* Scalar L1 Data Cache per SQC */
 937		.cache_size = 16,
 938		.cache_level = 1,
 939		.cache_line_size = 64,
 940		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 941			  CRAT_CACHE_FLAGS_DATA_CACHE |
 942			  CRAT_CACHE_FLAGS_SIMD_CACHE),
 943		.num_cu_shared = 2,
 944	},
 945	{
 946		/* GL1 Data Cache per SA */
 947		.cache_size = 128,
 948		.cache_level = 1,
 949		.cache_line_size = 128,
 950		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 951			  CRAT_CACHE_FLAGS_DATA_CACHE |
 952			  CRAT_CACHE_FLAGS_SIMD_CACHE),
 953		.num_cu_shared = 2,
 954	},
 955	{
 956		/* L2 Data Cache per GPU (Total Tex Cache) */
 957		.cache_size = 256,
 958		.cache_level = 2,
 959		.cache_line_size = 128,
 960		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 961			  CRAT_CACHE_FLAGS_DATA_CACHE |
 962			  CRAT_CACHE_FLAGS_SIMD_CACHE),
 963		.num_cu_shared = 2,
 964	},
 965};
 966
 967static struct kfd_gpu_cache_info dummy_cache_info[] = {
 968	{
 969		/* TCP L1 Cache per CU */
 970		.cache_size = 16,
 971		.cache_level = 1,
 972		.cache_line_size = 64,
 973		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 974				CRAT_CACHE_FLAGS_DATA_CACHE |
 975				CRAT_CACHE_FLAGS_SIMD_CACHE),
 976		.num_cu_shared = 1,
 977	},
 978	{
 979		/* Scalar L1 Instruction Cache per SQC */
 980		.cache_size = 32,
 981		.cache_level = 1,
 982		.cache_line_size = 64,
 983		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 984				CRAT_CACHE_FLAGS_INST_CACHE |
 985				CRAT_CACHE_FLAGS_SIMD_CACHE),
 986		.num_cu_shared = 2,
 987	},
 988	{
 989		/* Scalar L1 Data Cache per SQC */
 990		.cache_size = 16,
 991		.cache_level = 1,
 992		.cache_line_size = 64,
 993		.flags = (CRAT_CACHE_FLAGS_ENABLED |
 994				CRAT_CACHE_FLAGS_DATA_CACHE |
 995				CRAT_CACHE_FLAGS_SIMD_CACHE),
 996		.num_cu_shared = 2,
 997	},
 998	{
 999		/* GL1 Data Cache per SA */
1000		.cache_size = 128,
1001		.cache_level = 1,
1002		.cache_line_size = 64,
1003		.flags = (CRAT_CACHE_FLAGS_ENABLED |
1004				CRAT_CACHE_FLAGS_DATA_CACHE |
1005				CRAT_CACHE_FLAGS_SIMD_CACHE),
1006		.num_cu_shared = 6,
1007	},
1008	{
1009		/* L2 Data Cache per GPU (Total Tex Cache) */
1010		.cache_size = 2048,
1011		.cache_level = 2,
1012		.cache_line_size = 64,
1013		.flags = (CRAT_CACHE_FLAGS_ENABLED |
1014				CRAT_CACHE_FLAGS_DATA_CACHE |
1015				CRAT_CACHE_FLAGS_SIMD_CACHE),
1016		.num_cu_shared = 6,
1017	},
1018};
1019
1020static void kfd_populated_cu_info_cpu(struct kfd_topology_device *dev,
1021		struct crat_subtype_computeunit *cu)
1022{
1023	dev->node_props.cpu_cores_count = cu->num_cpu_cores;
1024	dev->node_props.cpu_core_id_base = cu->processor_id_low;
1025	if (cu->hsa_capability & CRAT_CU_FLAGS_IOMMU_PRESENT)
1026		dev->node_props.capability |= HSA_CAP_ATS_PRESENT;
1027
1028	pr_debug("CU CPU: cores=%d id_base=%d\n", cu->num_cpu_cores,
1029			cu->processor_id_low);
1030}
1031
1032static void kfd_populated_cu_info_gpu(struct kfd_topology_device *dev,
1033		struct crat_subtype_computeunit *cu)
1034{
1035	dev->node_props.simd_id_base = cu->processor_id_low;
1036	dev->node_props.simd_count = cu->num_simd_cores;
1037	dev->node_props.lds_size_in_kb = cu->lds_size_in_kb;
1038	dev->node_props.max_waves_per_simd = cu->max_waves_simd;
1039	dev->node_props.wave_front_size = cu->wave_front_size;
1040	dev->node_props.array_count = cu->array_count;
1041	dev->node_props.cu_per_simd_array = cu->num_cu_per_array;
1042	dev->node_props.simd_per_cu = cu->num_simd_per_cu;
1043	dev->node_props.max_slots_scratch_cu = cu->max_slots_scatch_cu;
1044	if (cu->hsa_capability & CRAT_CU_FLAGS_HOT_PLUGGABLE)
1045		dev->node_props.capability |= HSA_CAP_HOT_PLUGGABLE;
1046	pr_debug("CU GPU: id_base=%d\n", cu->processor_id_low);
1047}
1048
1049/* kfd_parse_subtype_cu - parse compute unit subtypes and attach it to correct
1050 * topology device present in the device_list
1051 */
1052static int kfd_parse_subtype_cu(struct crat_subtype_computeunit *cu,
1053				struct list_head *device_list)
1054{
1055	struct kfd_topology_device *dev;
1056
1057	pr_debug("Found CU entry in CRAT table with proximity_domain=%d caps=%x\n",
1058			cu->proximity_domain, cu->hsa_capability);
1059	list_for_each_entry(dev, device_list, list) {
1060		if (cu->proximity_domain == dev->proximity_domain) {
1061			if (cu->flags & CRAT_CU_FLAGS_CPU_PRESENT)
1062				kfd_populated_cu_info_cpu(dev, cu);
1063
1064			if (cu->flags & CRAT_CU_FLAGS_GPU_PRESENT)
1065				kfd_populated_cu_info_gpu(dev, cu);
1066			break;
1067		}
1068	}
1069
1070	return 0;
1071}
1072
1073static struct kfd_mem_properties *
1074find_subtype_mem(uint32_t heap_type, uint32_t flags, uint32_t width,
1075		struct kfd_topology_device *dev)
1076{
1077	struct kfd_mem_properties *props;
1078
1079	list_for_each_entry(props, &dev->mem_props, list) {
1080		if (props->heap_type == heap_type
1081				&& props->flags == flags
1082				&& props->width == width)
1083			return props;
1084	}
1085
1086	return NULL;
1087}
1088/* kfd_parse_subtype_mem - parse memory subtypes and attach it to correct
1089 * topology device present in the device_list
1090 */
1091static int kfd_parse_subtype_mem(struct crat_subtype_memory *mem,
1092				struct list_head *device_list)
1093{
1094	struct kfd_mem_properties *props;
1095	struct kfd_topology_device *dev;
1096	uint32_t heap_type;
1097	uint64_t size_in_bytes;
1098	uint32_t flags = 0;
1099	uint32_t width;
1100
1101	pr_debug("Found memory entry in CRAT table with proximity_domain=%d\n",
1102			mem->proximity_domain);
1103	list_for_each_entry(dev, device_list, list) {
1104		if (mem->proximity_domain == dev->proximity_domain) {
1105			/* We're on GPU node */
1106			if (dev->node_props.cpu_cores_count == 0) {
1107				/* APU */
1108				if (mem->visibility_type == 0)
1109					heap_type =
1110						HSA_MEM_HEAP_TYPE_FB_PRIVATE;
1111				/* dGPU */
1112				else
1113					heap_type = mem->visibility_type;
1114			} else
1115				heap_type = HSA_MEM_HEAP_TYPE_SYSTEM;
1116
1117			if (mem->flags & CRAT_MEM_FLAGS_HOT_PLUGGABLE)
1118				flags |= HSA_MEM_FLAGS_HOT_PLUGGABLE;
1119			if (mem->flags & CRAT_MEM_FLAGS_NON_VOLATILE)
1120				flags |= HSA_MEM_FLAGS_NON_VOLATILE;
1121
1122			size_in_bytes =
1123				((uint64_t)mem->length_high << 32) +
1124							mem->length_low;
1125			width = mem->width;
1126
1127			/* Multiple banks of the same type are aggregated into
1128			 * one. User mode doesn't care about multiple physical
1129			 * memory segments. It's managed as a single virtual
1130			 * heap for user mode.
1131			 */
1132			props = find_subtype_mem(heap_type, flags, width, dev);
1133			if (props) {
1134				props->size_in_bytes += size_in_bytes;
1135				break;
1136			}
1137
1138			props = kfd_alloc_struct(props);
1139			if (!props)
1140				return -ENOMEM;
1141
1142			props->heap_type = heap_type;
1143			props->flags = flags;
1144			props->size_in_bytes = size_in_bytes;
1145			props->width = width;
1146
1147			dev->node_props.mem_banks_count++;
1148			list_add_tail(&props->list, &dev->mem_props);
1149
1150			break;
1151		}
1152	}
1153
1154	return 0;
1155}
1156
1157/* kfd_parse_subtype_cache - parse cache subtypes and attach it to correct
1158 * topology device present in the device_list
1159 */
1160static int kfd_parse_subtype_cache(struct crat_subtype_cache *cache,
1161			struct list_head *device_list)
1162{
1163	struct kfd_cache_properties *props;
1164	struct kfd_topology_device *dev;
1165	uint32_t id;
1166	uint32_t total_num_of_cu;
1167
1168	id = cache->processor_id_low;
1169
1170	pr_debug("Found cache entry in CRAT table with processor_id=%d\n", id);
1171	list_for_each_entry(dev, device_list, list) {
1172		total_num_of_cu = (dev->node_props.array_count *
1173					dev->node_props.cu_per_simd_array);
1174
1175		/* Cache infomration in CRAT doesn't have proximity_domain
1176		 * information as it is associated with a CPU core or GPU
1177		 * Compute Unit. So map the cache using CPU core Id or SIMD
1178		 * (GPU) ID.
1179		 * TODO: This works because currently we can safely assume that
1180		 *  Compute Units are parsed before caches are parsed. In
1181		 *  future, remove this dependency
1182		 */
1183		if ((id >= dev->node_props.cpu_core_id_base &&
1184			id <= dev->node_props.cpu_core_id_base +
1185				dev->node_props.cpu_cores_count) ||
1186			(id >= dev->node_props.simd_id_base &&
1187			id < dev->node_props.simd_id_base +
1188				total_num_of_cu)) {
1189			props = kfd_alloc_struct(props);
1190			if (!props)
1191				return -ENOMEM;
1192
1193			props->processor_id_low = id;
1194			props->cache_level = cache->cache_level;
1195			props->cache_size = cache->cache_size;
1196			props->cacheline_size = cache->cache_line_size;
1197			props->cachelines_per_tag = cache->lines_per_tag;
1198			props->cache_assoc = cache->associativity;
1199			props->cache_latency = cache->cache_latency;
1200
1201			memcpy(props->sibling_map, cache->sibling_map,
1202					CRAT_SIBLINGMAP_SIZE);
1203
1204			/* set the sibling_map_size as 32 for CRAT from ACPI */
1205			props->sibling_map_size = CRAT_SIBLINGMAP_SIZE;
1206
1207			if (cache->flags & CRAT_CACHE_FLAGS_DATA_CACHE)
1208				props->cache_type |= HSA_CACHE_TYPE_DATA;
1209			if (cache->flags & CRAT_CACHE_FLAGS_INST_CACHE)
1210				props->cache_type |= HSA_CACHE_TYPE_INSTRUCTION;
1211			if (cache->flags & CRAT_CACHE_FLAGS_CPU_CACHE)
1212				props->cache_type |= HSA_CACHE_TYPE_CPU;
1213			if (cache->flags & CRAT_CACHE_FLAGS_SIMD_CACHE)
1214				props->cache_type |= HSA_CACHE_TYPE_HSACU;
1215
1216			dev->node_props.caches_count++;
1217			list_add_tail(&props->list, &dev->cache_props);
1218
1219			break;
1220		}
1221	}
1222
1223	return 0;
1224}
1225
1226/* kfd_parse_subtype_iolink - parse iolink subtypes and attach it to correct
1227 * topology device present in the device_list
1228 */
1229static int kfd_parse_subtype_iolink(struct crat_subtype_iolink *iolink,
1230					struct list_head *device_list)
1231{
1232	struct kfd_iolink_properties *props = NULL, *props2;
1233	struct kfd_topology_device *dev, *to_dev;
1234	uint32_t id_from;
1235	uint32_t id_to;
1236
1237	id_from = iolink->proximity_domain_from;
1238	id_to = iolink->proximity_domain_to;
1239
1240	pr_debug("Found IO link entry in CRAT table with id_from=%d, id_to %d\n",
1241			id_from, id_to);
1242	list_for_each_entry(dev, device_list, list) {
1243		if (id_from == dev->proximity_domain) {
1244			props = kfd_alloc_struct(props);
1245			if (!props)
1246				return -ENOMEM;
1247
1248			props->node_from = id_from;
1249			props->node_to = id_to;
1250			props->ver_maj = iolink->version_major;
1251			props->ver_min = iolink->version_minor;
1252			props->iolink_type = iolink->io_interface_type;
1253
1254			if (props->iolink_type == CRAT_IOLINK_TYPE_PCIEXPRESS)
1255				props->weight = 20;
1256			else if (props->iolink_type == CRAT_IOLINK_TYPE_XGMI)
1257				props->weight = iolink->weight_xgmi;
1258			else
1259				props->weight = node_distance(id_from, id_to);
1260
1261			props->min_latency = iolink->minimum_latency;
1262			props->max_latency = iolink->maximum_latency;
1263			props->min_bandwidth = iolink->minimum_bandwidth_mbs;
1264			props->max_bandwidth = iolink->maximum_bandwidth_mbs;
1265			props->rec_transfer_size =
1266					iolink->recommended_transfer_size;
1267
1268			dev->node_props.io_links_count++;
1269			list_add_tail(&props->list, &dev->io_link_props);
1270			break;
1271		}
1272	}
1273
1274	/* CPU topology is created before GPUs are detected, so CPU->GPU
1275	 * links are not built at that time. If a PCIe type is discovered, it
1276	 * means a GPU is detected and we are adding GPU->CPU to the topology.
1277	 * At this time, also add the corresponded CPU->GPU link if GPU
1278	 * is large bar.
1279	 * For xGMI, we only added the link with one direction in the crat
1280	 * table, add corresponded reversed direction link now.
1281	 */
1282	if (props && (iolink->flags & CRAT_IOLINK_FLAGS_BI_DIRECTIONAL)) {
1283		to_dev = kfd_topology_device_by_proximity_domain_no_lock(id_to);
1284		if (!to_dev)
1285			return -ENODEV;
1286		/* same everything but the other direction */
1287		props2 = kmemdup(props, sizeof(*props2), GFP_KERNEL);
1288		if (!props2)
1289			return -ENOMEM;
1290
1291		props2->node_from = id_to;
1292		props2->node_to = id_from;
1293		props2->kobj = NULL;
1294		to_dev->node_props.io_links_count++;
1295		list_add_tail(&props2->list, &to_dev->io_link_props);
1296	}
1297
1298	return 0;
1299}
1300
1301/* kfd_parse_subtype - parse subtypes and attach it to correct topology device
1302 * present in the device_list
1303 *	@sub_type_hdr - subtype section of crat_image
1304 *	@device_list - list of topology devices present in this crat_image
1305 */
1306static int kfd_parse_subtype(struct crat_subtype_generic *sub_type_hdr,
1307				struct list_head *device_list)
1308{
1309	struct crat_subtype_computeunit *cu;
1310	struct crat_subtype_memory *mem;
1311	struct crat_subtype_cache *cache;
1312	struct crat_subtype_iolink *iolink;
1313	int ret = 0;
1314
1315	switch (sub_type_hdr->type) {
1316	case CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY:
1317		cu = (struct crat_subtype_computeunit *)sub_type_hdr;
1318		ret = kfd_parse_subtype_cu(cu, device_list);
1319		break;
1320	case CRAT_SUBTYPE_MEMORY_AFFINITY:
1321		mem = (struct crat_subtype_memory *)sub_type_hdr;
1322		ret = kfd_parse_subtype_mem(mem, device_list);
1323		break;
1324	case CRAT_SUBTYPE_CACHE_AFFINITY:
1325		cache = (struct crat_subtype_cache *)sub_type_hdr;
1326		ret = kfd_parse_subtype_cache(cache, device_list);
1327		break;
1328	case CRAT_SUBTYPE_TLB_AFFINITY:
1329		/*
1330		 * For now, nothing to do here
1331		 */
1332		pr_debug("Found TLB entry in CRAT table (not processing)\n");
1333		break;
1334	case CRAT_SUBTYPE_CCOMPUTE_AFFINITY:
1335		/*
1336		 * For now, nothing to do here
1337		 */
1338		pr_debug("Found CCOMPUTE entry in CRAT table (not processing)\n");
1339		break;
1340	case CRAT_SUBTYPE_IOLINK_AFFINITY:
1341		iolink = (struct crat_subtype_iolink *)sub_type_hdr;
1342		ret = kfd_parse_subtype_iolink(iolink, device_list);
1343		break;
1344	default:
1345		pr_warn("Unknown subtype %d in CRAT\n",
1346				sub_type_hdr->type);
1347	}
1348
1349	return ret;
1350}
1351
1352/* kfd_parse_crat_table - parse CRAT table. For each node present in CRAT
1353 * create a kfd_topology_device and add in to device_list. Also parse
1354 * CRAT subtypes and attach it to appropriate kfd_topology_device
1355 *	@crat_image - input image containing CRAT
1356 *	@device_list - [OUT] list of kfd_topology_device generated after
1357 *		       parsing crat_image
1358 *	@proximity_domain - Proximity domain of the first device in the table
1359 *
1360 *	Return - 0 if successful else -ve value
1361 */
1362int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
1363			 uint32_t proximity_domain)
1364{
1365	struct kfd_topology_device *top_dev = NULL;
1366	struct crat_subtype_generic *sub_type_hdr;
1367	uint16_t node_id;
1368	int ret = 0;
1369	struct crat_header *crat_table = (struct crat_header *)crat_image;
1370	uint16_t num_nodes;
1371	uint32_t image_len;
1372
1373	if (!crat_image)
1374		return -EINVAL;
1375
1376	if (!list_empty(device_list)) {
1377		pr_warn("Error device list should be empty\n");
1378		return -EINVAL;
1379	}
1380
1381	num_nodes = crat_table->num_domains;
1382	image_len = crat_table->length;
1383
1384	pr_debug("Parsing CRAT table with %d nodes\n", num_nodes);
1385
1386	for (node_id = 0; node_id < num_nodes; node_id++) {
1387		top_dev = kfd_create_topology_device(device_list);
1388		if (!top_dev)
1389			break;
1390		top_dev->proximity_domain = proximity_domain++;
1391	}
1392
1393	if (!top_dev) {
1394		ret = -ENOMEM;
1395		goto err;
1396	}
1397
1398	memcpy(top_dev->oem_id, crat_table->oem_id, CRAT_OEMID_LENGTH);
1399	memcpy(top_dev->oem_table_id, crat_table->oem_table_id,
1400			CRAT_OEMTABLEID_LENGTH);
1401	top_dev->oem_revision = crat_table->oem_revision;
1402
1403	sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
1404	while ((char *)sub_type_hdr + sizeof(struct crat_subtype_generic) <
1405			((char *)crat_image) + image_len) {
1406		if (sub_type_hdr->flags & CRAT_SUBTYPE_FLAGS_ENABLED) {
1407			ret = kfd_parse_subtype(sub_type_hdr, device_list);
1408			if (ret)
1409				break;
1410		}
1411
1412		sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1413				sub_type_hdr->length);
1414	}
1415
1416err:
1417	if (ret)
1418		kfd_release_topology_device_list(device_list);
1419
1420	return ret;
1421}
1422
1423
1424static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
1425						   struct kfd_gpu_cache_info *pcache_info)
1426{
1427	struct amdgpu_device *adev = kdev->adev;
1428	int i = 0;
1429
1430	/* TCP L1 Cache per CU */
1431	if (adev->gfx.config.gc_tcp_l1_size) {
1432		pcache_info[i].cache_size = adev->gfx.config.gc_tcp_l1_size;
1433		pcache_info[i].cache_level = 1;
1434		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1435					CRAT_CACHE_FLAGS_DATA_CACHE |
1436					CRAT_CACHE_FLAGS_SIMD_CACHE);
1437		pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
1438		i++;
1439	}
1440	/* Scalar L1 Instruction Cache per SQC */
1441	if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
1442		pcache_info[i].cache_size =
1443			adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1444		pcache_info[i].cache_level = 1;
1445		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1446					CRAT_CACHE_FLAGS_INST_CACHE |
1447					CRAT_CACHE_FLAGS_SIMD_CACHE);
1448		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1449		i++;
1450	}
1451	/* Scalar L1 Data Cache per SQC */
1452	if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
1453		pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1454		pcache_info[i].cache_level = 1;
1455		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1456					CRAT_CACHE_FLAGS_DATA_CACHE |
1457					CRAT_CACHE_FLAGS_SIMD_CACHE);
1458		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
1459		i++;
1460	}
1461	/* GL1 Data Cache per SA */
1462	if (adev->gfx.config.gc_gl1c_per_sa &&
1463	    adev->gfx.config.gc_gl1c_size_per_instance) {
1464		pcache_info[i].cache_size = adev->gfx.config.gc_gl1c_per_sa *
1465			adev->gfx.config.gc_gl1c_size_per_instance;
1466		pcache_info[i].cache_level = 1;
1467		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1468					CRAT_CACHE_FLAGS_DATA_CACHE |
1469					CRAT_CACHE_FLAGS_SIMD_CACHE);
1470		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1471		i++;
1472	}
1473	/* L2 Data Cache per GPU (Total Tex Cache) */
1474	if (adev->gfx.config.gc_gl2c_per_gpu) {
1475		pcache_info[i].cache_size = adev->gfx.config.gc_gl2c_per_gpu;
1476		pcache_info[i].cache_level = 2;
1477		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1478					CRAT_CACHE_FLAGS_DATA_CACHE |
1479					CRAT_CACHE_FLAGS_SIMD_CACHE);
1480		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1481		i++;
1482	}
1483	/* L3 Data Cache per GPU */
1484	if (adev->gmc.mall_size) {
1485		pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
1486		pcache_info[i].cache_level = 3;
1487		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1488					CRAT_CACHE_FLAGS_DATA_CACHE |
1489					CRAT_CACHE_FLAGS_SIMD_CACHE);
1490		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1491		i++;
1492	}
1493	return i;
1494}
1495
1496static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
1497						   struct kfd_gpu_cache_info *pcache_info)
1498{
1499	struct amdgpu_device *adev = kdev->adev;
1500	int i = 0;
1501
1502	/* TCP L1 Cache per CU */
1503	if (adev->gfx.config.gc_tcp_size_per_cu) {
1504		pcache_info[i].cache_size = adev->gfx.config.gc_tcp_size_per_cu;
1505		pcache_info[i].cache_level = 1;
1506		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1507					CRAT_CACHE_FLAGS_DATA_CACHE |
1508					CRAT_CACHE_FLAGS_SIMD_CACHE);
1509		pcache_info[i].num_cu_shared = 1;
1510		i++;
1511	}
1512	/* Scalar L1 Instruction Cache per SQC */
1513	if (adev->gfx.config.gc_l1_instruction_cache_size_per_sqc) {
1514		pcache_info[i].cache_size =
1515			adev->gfx.config.gc_l1_instruction_cache_size_per_sqc;
1516		pcache_info[i].cache_level = 1;
1517		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1518					CRAT_CACHE_FLAGS_INST_CACHE |
1519					CRAT_CACHE_FLAGS_SIMD_CACHE);
1520		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
1521		i++;
1522	}
1523	/* Scalar L1 Data Cache per SQC */
1524	if (adev->gfx.config.gc_l1_data_cache_size_per_sqc) {
1525		pcache_info[i].cache_size = adev->gfx.config.gc_l1_data_cache_size_per_sqc;
1526		pcache_info[i].cache_level = 1;
1527		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1528					CRAT_CACHE_FLAGS_DATA_CACHE |
1529					CRAT_CACHE_FLAGS_SIMD_CACHE);
1530		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_cu_per_sqc;
1531		i++;
1532	}
1533	/* L2 Data Cache per GPU (Total Tex Cache) */
1534	if (adev->gfx.config.gc_tcc_size) {
1535		pcache_info[i].cache_size = adev->gfx.config.gc_tcc_size;
1536		pcache_info[i].cache_level = 2;
1537		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1538					CRAT_CACHE_FLAGS_DATA_CACHE |
1539					CRAT_CACHE_FLAGS_SIMD_CACHE);
1540		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1541		i++;
1542	}
1543	/* L3 Data Cache per GPU */
1544	if (adev->gmc.mall_size) {
1545		pcache_info[i].cache_size = adev->gmc.mall_size / 1024;
1546		pcache_info[i].cache_level = 3;
1547		pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED |
1548					CRAT_CACHE_FLAGS_DATA_CACHE |
1549					CRAT_CACHE_FLAGS_SIMD_CACHE);
1550		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
1551		i++;
1552	}
1553	return i;
1554}
1555
1556int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)
1557{
1558	int num_of_cache_types = 0;
1559
1560	switch (kdev->adev->asic_type) {
1561	case CHIP_KAVERI:
1562		*pcache_info = kaveri_cache_info;
1563		num_of_cache_types = ARRAY_SIZE(kaveri_cache_info);
1564		break;
1565	case CHIP_HAWAII:
1566		*pcache_info = hawaii_cache_info;
1567		num_of_cache_types = ARRAY_SIZE(hawaii_cache_info);
1568		break;
1569	case CHIP_CARRIZO:
1570		*pcache_info = carrizo_cache_info;
1571		num_of_cache_types = ARRAY_SIZE(carrizo_cache_info);
1572		break;
1573	case CHIP_TONGA:
1574		*pcache_info = tonga_cache_info;
1575		num_of_cache_types = ARRAY_SIZE(tonga_cache_info);
1576		break;
1577	case CHIP_FIJI:
1578		*pcache_info = fiji_cache_info;
1579		num_of_cache_types = ARRAY_SIZE(fiji_cache_info);
1580		break;
1581	case CHIP_POLARIS10:
1582		*pcache_info = polaris10_cache_info;
1583		num_of_cache_types = ARRAY_SIZE(polaris10_cache_info);
1584		break;
1585	case CHIP_POLARIS11:
1586		*pcache_info = polaris11_cache_info;
1587		num_of_cache_types = ARRAY_SIZE(polaris11_cache_info);
1588		break;
1589	case CHIP_POLARIS12:
1590		*pcache_info = polaris12_cache_info;
1591		num_of_cache_types = ARRAY_SIZE(polaris12_cache_info);
1592		break;
1593	case CHIP_VEGAM:
1594		*pcache_info = vegam_cache_info;
1595		num_of_cache_types = ARRAY_SIZE(vegam_cache_info);
1596		break;
1597	default:
1598		switch (KFD_GC_VERSION(kdev)) {
1599		case IP_VERSION(9, 0, 1):
1600			*pcache_info = vega10_cache_info;
1601			num_of_cache_types = ARRAY_SIZE(vega10_cache_info);
1602			break;
1603		case IP_VERSION(9, 2, 1):
1604			*pcache_info = vega12_cache_info;
1605			num_of_cache_types = ARRAY_SIZE(vega12_cache_info);
1606			break;
1607		case IP_VERSION(9, 4, 0):
1608		case IP_VERSION(9, 4, 1):
1609			*pcache_info = vega20_cache_info;
1610			num_of_cache_types = ARRAY_SIZE(vega20_cache_info);
1611			break;
1612		case IP_VERSION(9, 4, 2):
1613			*pcache_info = aldebaran_cache_info;
1614			num_of_cache_types = ARRAY_SIZE(aldebaran_cache_info);
1615			break;
1616		case IP_VERSION(9, 4, 3):
1617			num_of_cache_types =
1618				kfd_fill_gpu_cache_info_from_gfx_config_v2(kdev->kfd,
1619									*pcache_info);
1620			break;
1621		case IP_VERSION(9, 1, 0):
1622		case IP_VERSION(9, 2, 2):
1623			*pcache_info = raven_cache_info;
1624			num_of_cache_types = ARRAY_SIZE(raven_cache_info);
1625			break;
1626		case IP_VERSION(9, 3, 0):
1627			*pcache_info = renoir_cache_info;
1628			num_of_cache_types = ARRAY_SIZE(renoir_cache_info);
1629			break;
1630		case IP_VERSION(10, 1, 10):
1631		case IP_VERSION(10, 1, 2):
1632		case IP_VERSION(10, 1, 3):
1633		case IP_VERSION(10, 1, 4):
1634			*pcache_info = navi10_cache_info;
1635			num_of_cache_types = ARRAY_SIZE(navi10_cache_info);
1636			break;
1637		case IP_VERSION(10, 1, 1):
1638			*pcache_info = navi14_cache_info;
1639			num_of_cache_types = ARRAY_SIZE(navi14_cache_info);
1640			break;
1641		case IP_VERSION(10, 3, 0):
1642			*pcache_info = sienna_cichlid_cache_info;
1643			num_of_cache_types = ARRAY_SIZE(sienna_cichlid_cache_info);
1644			break;
1645		case IP_VERSION(10, 3, 2):
1646			*pcache_info = navy_flounder_cache_info;
1647			num_of_cache_types = ARRAY_SIZE(navy_flounder_cache_info);
1648			break;
1649		case IP_VERSION(10, 3, 4):
1650			*pcache_info = dimgrey_cavefish_cache_info;
1651			num_of_cache_types = ARRAY_SIZE(dimgrey_cavefish_cache_info);
1652			break;
1653		case IP_VERSION(10, 3, 1):
1654			*pcache_info = vangogh_cache_info;
1655			num_of_cache_types = ARRAY_SIZE(vangogh_cache_info);
1656			break;
1657		case IP_VERSION(10, 3, 5):
1658			*pcache_info = beige_goby_cache_info;
1659			num_of_cache_types = ARRAY_SIZE(beige_goby_cache_info);
1660			break;
1661		case IP_VERSION(10, 3, 3):
1662			*pcache_info = yellow_carp_cache_info;
1663			num_of_cache_types = ARRAY_SIZE(yellow_carp_cache_info);
1664			break;
1665		case IP_VERSION(10, 3, 6):
1666			*pcache_info = gc_10_3_6_cache_info;
1667			num_of_cache_types = ARRAY_SIZE(gc_10_3_6_cache_info);
1668			break;
1669		case IP_VERSION(10, 3, 7):
1670			*pcache_info = gfx1037_cache_info;
1671			num_of_cache_types = ARRAY_SIZE(gfx1037_cache_info);
1672			break;
1673		case IP_VERSION(11, 0, 0):
1674		case IP_VERSION(11, 0, 1):
1675		case IP_VERSION(11, 0, 2):
1676		case IP_VERSION(11, 0, 3):
1677		case IP_VERSION(11, 0, 4):
1678		case IP_VERSION(11, 5, 0):
1679		case IP_VERSION(11, 5, 1):
1680			num_of_cache_types =
1681				kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd, *pcache_info);
1682			break;
1683		default:
1684			*pcache_info = dummy_cache_info;
1685			num_of_cache_types = ARRAY_SIZE(dummy_cache_info);
1686			pr_warn("dummy cache info is used temporarily and real cache info need update later.\n");
1687			break;
1688		}
1689	}
1690	return num_of_cache_types;
1691}
1692
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1693/* Memory required to create Virtual CRAT.
1694 * Since there is no easy way to predict the amount of memory required, the
1695 * following amount is allocated for GPU Virtual CRAT. This is
1696 * expected to cover all known conditions. But to be safe additional check
1697 * is put in the code to ensure we don't overwrite.
1698 */
1699#define VCRAT_SIZE_FOR_GPU	(4 * PAGE_SIZE)
1700
1701/* kfd_fill_cu_for_cpu - Fill in Compute info for the given CPU NUMA node
1702 *
1703 *	@numa_node_id: CPU NUMA node id
1704 *	@avail_size: Available size in the memory
1705 *	@sub_type_hdr: Memory into which compute info will be filled in
1706 *
1707 *	Return 0 if successful else return -ve value
1708 */
1709static int kfd_fill_cu_for_cpu(int numa_node_id, int *avail_size,
1710				int proximity_domain,
1711				struct crat_subtype_computeunit *sub_type_hdr)
1712{
1713	const struct cpumask *cpumask;
1714
1715	*avail_size -= sizeof(struct crat_subtype_computeunit);
1716	if (*avail_size < 0)
1717		return -ENOMEM;
1718
1719	memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
1720
1721	/* Fill in subtype header data */
1722	sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
1723	sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
1724	sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1725
1726	cpumask = cpumask_of_node(numa_node_id);
1727
1728	/* Fill in CU data */
1729	sub_type_hdr->flags |= CRAT_CU_FLAGS_CPU_PRESENT;
1730	sub_type_hdr->proximity_domain = proximity_domain;
1731	sub_type_hdr->processor_id_low = kfd_numa_node_to_apic_id(numa_node_id);
1732	if (sub_type_hdr->processor_id_low == -1)
1733		return -EINVAL;
1734
1735	sub_type_hdr->num_cpu_cores = cpumask_weight(cpumask);
1736
1737	return 0;
1738}
1739
1740/* kfd_fill_mem_info_for_cpu - Fill in Memory info for the given CPU NUMA node
1741 *
1742 *	@numa_node_id: CPU NUMA node id
1743 *	@avail_size: Available size in the memory
1744 *	@sub_type_hdr: Memory into which compute info will be filled in
1745 *
1746 *	Return 0 if successful else return -ve value
1747 */
1748static int kfd_fill_mem_info_for_cpu(int numa_node_id, int *avail_size,
1749			int proximity_domain,
1750			struct crat_subtype_memory *sub_type_hdr)
1751{
1752	uint64_t mem_in_bytes = 0;
1753	pg_data_t *pgdat;
1754	int zone_type;
1755
1756	*avail_size -= sizeof(struct crat_subtype_memory);
1757	if (*avail_size < 0)
1758		return -ENOMEM;
1759
1760	memset(sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1761
1762	/* Fill in subtype header data */
1763	sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1764	sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1765	sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1766
1767	/* Fill in Memory Subunit data */
1768
1769	/* Unlike si_meminfo, si_meminfo_node is not exported. So
1770	 * the following lines are duplicated from si_meminfo_node
1771	 * function
1772	 */
1773	pgdat = NODE_DATA(numa_node_id);
1774	for (zone_type = 0; zone_type < MAX_NR_ZONES; zone_type++)
1775		mem_in_bytes += zone_managed_pages(&pgdat->node_zones[zone_type]);
1776	mem_in_bytes <<= PAGE_SHIFT;
1777
1778	sub_type_hdr->length_low = lower_32_bits(mem_in_bytes);
1779	sub_type_hdr->length_high = upper_32_bits(mem_in_bytes);
1780	sub_type_hdr->proximity_domain = proximity_domain;
1781
1782	return 0;
1783}
1784
1785#ifdef CONFIG_X86_64
1786static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size,
1787				uint32_t *num_entries,
1788				struct crat_subtype_iolink *sub_type_hdr)
1789{
1790	int nid;
1791	struct cpuinfo_x86 *c = &cpu_data(0);
1792	uint8_t link_type;
1793
1794	if (c->x86_vendor == X86_VENDOR_AMD)
1795		link_type = CRAT_IOLINK_TYPE_HYPERTRANSPORT;
1796	else
1797		link_type = CRAT_IOLINK_TYPE_QPI_1_1;
1798
1799	*num_entries = 0;
1800
1801	/* Create IO links from this node to other CPU nodes */
1802	for_each_online_node(nid) {
1803		if (nid == numa_node_id) /* node itself */
1804			continue;
1805
1806		*avail_size -= sizeof(struct crat_subtype_iolink);
1807		if (*avail_size < 0)
1808			return -ENOMEM;
1809
1810		memset(sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
1811
1812		/* Fill in subtype header data */
1813		sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
1814		sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
1815		sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
1816
1817		/* Fill in IO link data */
1818		sub_type_hdr->proximity_domain_from = numa_node_id;
1819		sub_type_hdr->proximity_domain_to = nid;
1820		sub_type_hdr->io_interface_type = link_type;
1821
1822		(*num_entries)++;
1823		sub_type_hdr++;
1824	}
1825
1826	return 0;
1827}
1828#endif
1829
1830/* kfd_create_vcrat_image_cpu - Create Virtual CRAT for CPU
1831 *
1832 *	@pcrat_image: Fill in VCRAT for CPU
1833 *	@size:	[IN] allocated size of crat_image.
1834 *		[OUT] actual size of data filled in crat_image
1835 */
1836static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size)
1837{
1838	struct crat_header *crat_table = (struct crat_header *)pcrat_image;
1839	struct acpi_table_header *acpi_table;
1840	acpi_status status;
1841	struct crat_subtype_generic *sub_type_hdr;
1842	int avail_size = *size;
1843	int numa_node_id;
1844#ifdef CONFIG_X86_64
1845	uint32_t entries = 0;
1846#endif
1847	int ret = 0;
1848
1849	if (!pcrat_image)
1850		return -EINVAL;
1851
1852	/* Fill in CRAT Header.
1853	 * Modify length and total_entries as subunits are added.
1854	 */
1855	avail_size -= sizeof(struct crat_header);
1856	if (avail_size < 0)
1857		return -ENOMEM;
1858
1859	memset(crat_table, 0, sizeof(struct crat_header));
1860	memcpy(&crat_table->signature, CRAT_SIGNATURE,
1861			sizeof(crat_table->signature));
1862	crat_table->length = sizeof(struct crat_header);
1863
1864	status = acpi_get_table("DSDT", 0, &acpi_table);
1865	if (status != AE_OK)
1866		pr_warn("DSDT table not found for OEM information\n");
1867	else {
1868		crat_table->oem_revision = acpi_table->revision;
1869		memcpy(crat_table->oem_id, acpi_table->oem_id,
1870				CRAT_OEMID_LENGTH);
1871		memcpy(crat_table->oem_table_id, acpi_table->oem_table_id,
1872				CRAT_OEMTABLEID_LENGTH);
1873		acpi_put_table(acpi_table);
1874	}
1875	crat_table->total_entries = 0;
1876	crat_table->num_domains = 0;
1877
1878	sub_type_hdr = (struct crat_subtype_generic *)(crat_table+1);
1879
1880	for_each_online_node(numa_node_id) {
1881		if (kfd_numa_node_to_apic_id(numa_node_id) == -1)
1882			continue;
1883
1884		/* Fill in Subtype: Compute Unit */
1885		ret = kfd_fill_cu_for_cpu(numa_node_id, &avail_size,
1886			crat_table->num_domains,
1887			(struct crat_subtype_computeunit *)sub_type_hdr);
1888		if (ret < 0)
1889			return ret;
1890		crat_table->length += sub_type_hdr->length;
1891		crat_table->total_entries++;
1892
1893		sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1894			sub_type_hdr->length);
1895
1896		/* Fill in Subtype: Memory */
1897		ret = kfd_fill_mem_info_for_cpu(numa_node_id, &avail_size,
1898			crat_table->num_domains,
1899			(struct crat_subtype_memory *)sub_type_hdr);
1900		if (ret < 0)
1901			return ret;
1902		crat_table->length += sub_type_hdr->length;
1903		crat_table->total_entries++;
1904
1905		sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1906			sub_type_hdr->length);
1907
1908		/* Fill in Subtype: IO Link */
1909#ifdef CONFIG_X86_64
1910		ret = kfd_fill_iolink_info_for_cpu(numa_node_id, &avail_size,
1911				&entries,
1912				(struct crat_subtype_iolink *)sub_type_hdr);
1913		if (ret < 0)
1914			return ret;
1915
1916		if (entries) {
1917			crat_table->length += (sub_type_hdr->length * entries);
1918			crat_table->total_entries += entries;
1919
1920			sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
1921					sub_type_hdr->length * entries);
1922		}
1923#else
1924		pr_info("IO link not available for non x86 platforms\n");
1925#endif
1926
1927		crat_table->num_domains++;
1928	}
1929
1930	/* TODO: Add cache Subtype for CPU.
1931	 * Currently, CPU cache information is available in function
1932	 * detect_cache_attributes(cpu) defined in the file
1933	 * ./arch/x86/kernel/cpu/intel_cacheinfo.c. This function is not
1934	 * exported and to get the same information the code needs to be
1935	 * duplicated.
1936	 */
1937
1938	*size = crat_table->length;
1939	pr_info("Virtual CRAT table created for CPU\n");
1940
1941	return 0;
1942}
1943
1944static int kfd_fill_gpu_memory_affinity(int *avail_size,
1945		struct kfd_node *kdev, uint8_t type, uint64_t size,
1946		struct crat_subtype_memory *sub_type_hdr,
1947		uint32_t proximity_domain,
1948		const struct kfd_local_mem_info *local_mem_info)
1949{
1950	*avail_size -= sizeof(struct crat_subtype_memory);
1951	if (*avail_size < 0)
1952		return -ENOMEM;
1953
1954	memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_memory));
1955	sub_type_hdr->type = CRAT_SUBTYPE_MEMORY_AFFINITY;
1956	sub_type_hdr->length = sizeof(struct crat_subtype_memory);
1957	sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
1958
1959	sub_type_hdr->proximity_domain = proximity_domain;
1960
1961	pr_debug("Fill gpu memory affinity - type 0x%x size 0x%llx\n",
1962			type, size);
1963
1964	sub_type_hdr->length_low = lower_32_bits(size);
1965	sub_type_hdr->length_high = upper_32_bits(size);
1966
1967	sub_type_hdr->width = local_mem_info->vram_width;
1968	sub_type_hdr->visibility_type = type;
1969
1970	return 0;
1971}
1972
1973#ifdef CONFIG_ACPI_NUMA
1974static void kfd_find_numa_node_in_srat(struct kfd_node *kdev)
1975{
1976	struct acpi_table_header *table_header = NULL;
1977	struct acpi_subtable_header *sub_header = NULL;
1978	unsigned long table_end, subtable_len;
1979	u32 pci_id = pci_domain_nr(kdev->adev->pdev->bus) << 16 |
1980			pci_dev_id(kdev->adev->pdev);
1981	u32 bdf;
1982	acpi_status status;
1983	struct acpi_srat_cpu_affinity *cpu;
1984	struct acpi_srat_generic_affinity *gpu;
1985	int pxm = 0, max_pxm = 0;
1986	int numa_node = NUMA_NO_NODE;
1987	bool found = false;
1988
1989	/* Fetch the SRAT table from ACPI */
1990	status = acpi_get_table(ACPI_SIG_SRAT, 0, &table_header);
1991	if (status == AE_NOT_FOUND) {
1992		pr_warn("SRAT table not found\n");
1993		return;
1994	} else if (ACPI_FAILURE(status)) {
1995		const char *err = acpi_format_exception(status);
1996		pr_err("SRAT table error: %s\n", err);
1997		return;
1998	}
1999
2000	table_end = (unsigned long)table_header + table_header->length;
2001
2002	/* Parse all entries looking for a match. */
2003	sub_header = (struct acpi_subtable_header *)
2004			((unsigned long)table_header +
2005			sizeof(struct acpi_table_srat));
2006	subtable_len = sub_header->length;
2007
2008	while (((unsigned long)sub_header) + subtable_len  < table_end) {
2009		/*
2010		 * If length is 0, break from this loop to avoid
2011		 * infinite loop.
2012		 */
2013		if (subtable_len == 0) {
2014			pr_err("SRAT invalid zero length\n");
2015			break;
2016		}
2017
2018		switch (sub_header->type) {
2019		case ACPI_SRAT_TYPE_CPU_AFFINITY:
2020			cpu = (struct acpi_srat_cpu_affinity *)sub_header;
2021			pxm = *((u32 *)cpu->proximity_domain_hi) << 8 |
2022					cpu->proximity_domain_lo;
2023			if (pxm > max_pxm)
2024				max_pxm = pxm;
2025			break;
2026		case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
2027			gpu = (struct acpi_srat_generic_affinity *)sub_header;
2028			bdf = *((u16 *)(&gpu->device_handle[0])) << 16 |
2029					*((u16 *)(&gpu->device_handle[2]));
2030			if (bdf == pci_id) {
2031				found = true;
2032				numa_node = pxm_to_node(gpu->proximity_domain);
2033			}
2034			break;
2035		default:
2036			break;
2037		}
2038
2039		if (found)
2040			break;
2041
2042		sub_header = (struct acpi_subtable_header *)
2043				((unsigned long)sub_header + subtable_len);
2044		subtable_len = sub_header->length;
2045	}
2046
2047	acpi_put_table(table_header);
2048
2049	/* Workaround bad cpu-gpu binding case */
2050	if (found && (numa_node < 0 ||
2051			numa_node > pxm_to_node(max_pxm)))
2052		numa_node = 0;
2053
2054	if (numa_node != NUMA_NO_NODE)
2055		set_dev_node(&kdev->adev->pdev->dev, numa_node);
2056}
2057#endif
2058
2059#define KFD_CRAT_INTRA_SOCKET_WEIGHT	13
2060#define KFD_CRAT_XGMI_WEIGHT		15
2061
2062/* kfd_fill_gpu_direct_io_link - Fill in direct io link from GPU
2063 * to its NUMA node
2064 *	@avail_size: Available size in the memory
2065 *	@kdev - [IN] GPU device
2066 *	@sub_type_hdr: Memory into which io link info will be filled in
2067 *	@proximity_domain - proximity domain of the GPU node
2068 *
2069 *	Return 0 if successful else return -ve value
2070 */
2071static int kfd_fill_gpu_direct_io_link_to_cpu(int *avail_size,
2072			struct kfd_node *kdev,
2073			struct crat_subtype_iolink *sub_type_hdr,
2074			uint32_t proximity_domain)
2075{
2076	*avail_size -= sizeof(struct crat_subtype_iolink);
2077	if (*avail_size < 0)
2078		return -ENOMEM;
2079
2080	memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
2081
2082	/* Fill in subtype header data */
2083	sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
2084	sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
2085	sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED;
2086	if (kfd_dev_is_large_bar(kdev))
2087		sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2088
2089	/* Fill in IOLINK subtype.
2090	 * TODO: Fill-in other fields of iolink subtype
2091	 */
2092	if (kdev->adev->gmc.xgmi.connected_to_cpu ||
2093	    (KFD_GC_VERSION(kdev) == IP_VERSION(9, 4, 3) &&
2094	     kdev->adev->smuio.funcs->get_pkg_type(kdev->adev) ==
2095	     AMDGPU_PKG_TYPE_APU)) {
2096		bool ext_cpu = KFD_GC_VERSION(kdev) != IP_VERSION(9, 4, 3);
2097		int mem_bw = 819200, weight = ext_cpu ? KFD_CRAT_XGMI_WEIGHT :
2098							KFD_CRAT_INTRA_SOCKET_WEIGHT;
2099		uint32_t bandwidth = ext_cpu ? amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(
2100							kdev->adev, NULL, true) : mem_bw;
2101
2102		/*
2103		 * with host gpu xgmi link, host can access gpu memory whether
2104		 * or not pcie bar type is large, so always create bidirectional
2105		 * io link.
2106		 */
2107		sub_type_hdr->flags |= CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2108		sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
2109		sub_type_hdr->weight_xgmi = weight;
2110		sub_type_hdr->minimum_bandwidth_mbs = bandwidth;
2111		sub_type_hdr->maximum_bandwidth_mbs = bandwidth;
 
 
 
 
 
2112	} else {
2113		sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_PCIEXPRESS;
2114		sub_type_hdr->minimum_bandwidth_mbs =
2115				amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, true);
2116		sub_type_hdr->maximum_bandwidth_mbs =
2117				amdgpu_amdkfd_get_pcie_bandwidth_mbytes(kdev->adev, false);
2118	}
2119
2120	sub_type_hdr->proximity_domain_from = proximity_domain;
2121
2122#ifdef CONFIG_ACPI_NUMA
2123	if (kdev->adev->pdev->dev.numa_node == NUMA_NO_NODE &&
2124	    num_possible_nodes() > 1)
2125		kfd_find_numa_node_in_srat(kdev);
2126#endif
2127#ifdef CONFIG_NUMA
2128	if (kdev->adev->pdev->dev.numa_node == NUMA_NO_NODE)
2129		sub_type_hdr->proximity_domain_to = 0;
2130	else
2131		sub_type_hdr->proximity_domain_to = kdev->adev->pdev->dev.numa_node;
2132#else
2133	sub_type_hdr->proximity_domain_to = 0;
2134#endif
2135	return 0;
2136}
2137
2138static int kfd_fill_gpu_xgmi_link_to_gpu(int *avail_size,
2139			struct kfd_node *kdev,
2140			struct kfd_node *peer_kdev,
2141			struct crat_subtype_iolink *sub_type_hdr,
2142			uint32_t proximity_domain_from,
2143			uint32_t proximity_domain_to)
2144{
2145	bool use_ta_info = kdev->kfd->num_nodes == 1;
2146
2147	*avail_size -= sizeof(struct crat_subtype_iolink);
2148	if (*avail_size < 0)
2149		return -ENOMEM;
2150
2151	memset((void *)sub_type_hdr, 0, sizeof(struct crat_subtype_iolink));
2152
2153	sub_type_hdr->type = CRAT_SUBTYPE_IOLINK_AFFINITY;
2154	sub_type_hdr->length = sizeof(struct crat_subtype_iolink);
2155	sub_type_hdr->flags |= CRAT_SUBTYPE_FLAGS_ENABLED |
2156			       CRAT_IOLINK_FLAGS_BI_DIRECTIONAL;
2157
2158	sub_type_hdr->io_interface_type = CRAT_IOLINK_TYPE_XGMI;
2159	sub_type_hdr->proximity_domain_from = proximity_domain_from;
2160	sub_type_hdr->proximity_domain_to = proximity_domain_to;
2161
2162	if (use_ta_info) {
2163		sub_type_hdr->weight_xgmi = KFD_CRAT_XGMI_WEIGHT *
2164			amdgpu_amdkfd_get_xgmi_hops_count(kdev->adev, peer_kdev->adev);
2165		sub_type_hdr->maximum_bandwidth_mbs =
2166			amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->adev,
2167							peer_kdev->adev, false);
2168		sub_type_hdr->minimum_bandwidth_mbs = sub_type_hdr->maximum_bandwidth_mbs ?
2169			amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(kdev->adev, NULL, true) : 0;
2170	} else {
2171		bool is_single_hop = kdev->kfd == peer_kdev->kfd;
2172		int weight = is_single_hop ? KFD_CRAT_INTRA_SOCKET_WEIGHT :
2173			(2 * KFD_CRAT_INTRA_SOCKET_WEIGHT) + KFD_CRAT_XGMI_WEIGHT;
2174		int mem_bw = 819200;
2175
2176		sub_type_hdr->weight_xgmi = weight;
2177		sub_type_hdr->maximum_bandwidth_mbs = is_single_hop ? mem_bw : 0;
2178		sub_type_hdr->minimum_bandwidth_mbs = is_single_hop ? mem_bw : 0;
2179	}
2180
2181	return 0;
2182}
2183
2184/* kfd_create_vcrat_image_gpu - Create Virtual CRAT for CPU
2185 *
2186 *	@pcrat_image: Fill in VCRAT for GPU
2187 *	@size:	[IN] allocated size of crat_image.
2188 *		[OUT] actual size of data filled in crat_image
2189 */
2190static int kfd_create_vcrat_image_gpu(void *pcrat_image,
2191				      size_t *size, struct kfd_node *kdev,
2192				      uint32_t proximity_domain)
2193{
2194	struct crat_header *crat_table = (struct crat_header *)pcrat_image;
2195	struct amdgpu_gfx_config *gfx_info = &kdev->adev->gfx.config;
2196	struct amdgpu_cu_info *cu_info = &kdev->adev->gfx.cu_info;
2197	struct crat_subtype_generic *sub_type_hdr;
2198	struct kfd_local_mem_info local_mem_info;
2199	struct kfd_topology_device *peer_dev;
2200	struct crat_subtype_computeunit *cu;
 
2201	int avail_size = *size;
2202	uint32_t total_num_of_cu;
2203	uint32_t nid = 0;
2204	int ret = 0;
2205
2206	if (!pcrat_image || avail_size < VCRAT_SIZE_FOR_GPU)
2207		return -EINVAL;
2208
2209	/* Fill the CRAT Header.
2210	 * Modify length and total_entries as subunits are added.
2211	 */
2212	avail_size -= sizeof(struct crat_header);
2213	if (avail_size < 0)
2214		return -ENOMEM;
2215
2216	memset(crat_table, 0, sizeof(struct crat_header));
2217
2218	memcpy(&crat_table->signature, CRAT_SIGNATURE,
2219			sizeof(crat_table->signature));
2220	/* Change length as we add more subtypes*/
2221	crat_table->length = sizeof(struct crat_header);
2222	crat_table->num_domains = 1;
2223	crat_table->total_entries = 0;
2224
2225	/* Fill in Subtype: Compute Unit
2226	 * First fill in the sub type header and then sub type data
2227	 */
2228	avail_size -= sizeof(struct crat_subtype_computeunit);
2229	if (avail_size < 0)
2230		return -ENOMEM;
2231
2232	sub_type_hdr = (struct crat_subtype_generic *)(crat_table + 1);
2233	memset(sub_type_hdr, 0, sizeof(struct crat_subtype_computeunit));
2234
2235	sub_type_hdr->type = CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY;
2236	sub_type_hdr->length = sizeof(struct crat_subtype_computeunit);
2237	sub_type_hdr->flags = CRAT_SUBTYPE_FLAGS_ENABLED;
2238
2239	/* Fill CU subtype data */
2240	cu = (struct crat_subtype_computeunit *)sub_type_hdr;
2241	cu->flags |= CRAT_CU_FLAGS_GPU_PRESENT;
2242	cu->proximity_domain = proximity_domain;
2243
2244	cu->num_simd_per_cu = cu_info->simd_per_cu;
2245	cu->num_simd_cores = cu_info->simd_per_cu *
2246			(cu_info->number / kdev->kfd->num_nodes);
2247	cu->max_waves_simd = cu_info->max_waves_per_simd;
2248
2249	cu->wave_front_size = cu_info->wave_front_size;
2250	cu->array_count = gfx_info->max_sh_per_se *
2251		gfx_info->max_shader_engines;
2252	total_num_of_cu = (cu->array_count * gfx_info->max_cu_per_sh);
2253	cu->processor_id_low = get_and_inc_gpu_processor_id(total_num_of_cu);
2254	cu->num_cu_per_array = gfx_info->max_cu_per_sh;
2255	cu->max_slots_scatch_cu = cu_info->max_scratch_slots_per_cu;
2256	cu->num_banks = gfx_info->max_shader_engines;
2257	cu->lds_size_in_kb = cu_info->lds_size;
2258
2259	cu->hsa_capability = 0;
2260
 
 
 
 
 
 
2261	crat_table->length += sub_type_hdr->length;
2262	crat_table->total_entries++;
2263
2264	/* Fill in Subtype: Memory. Only on systems with large BAR (no
2265	 * private FB), report memory as public. On other systems
2266	 * report the total FB size (public+private) as a single
2267	 * private heap.
2268	 */
2269	local_mem_info = kdev->local_mem_info;
2270	sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
2271			sub_type_hdr->length);
2272
2273	if (kdev->adev->debug_largebar)
2274		local_mem_info.local_mem_size_private = 0;
2275
2276	if (local_mem_info.local_mem_size_private == 0)
2277		ret = kfd_fill_gpu_memory_affinity(&avail_size,
2278				kdev, HSA_MEM_HEAP_TYPE_FB_PUBLIC,
2279				local_mem_info.local_mem_size_public,
2280				(struct crat_subtype_memory *)sub_type_hdr,
2281				proximity_domain,
2282				&local_mem_info);
2283	else
2284		ret = kfd_fill_gpu_memory_affinity(&avail_size,
2285				kdev, HSA_MEM_HEAP_TYPE_FB_PRIVATE,
2286				local_mem_info.local_mem_size_public +
2287				local_mem_info.local_mem_size_private,
2288				(struct crat_subtype_memory *)sub_type_hdr,
2289				proximity_domain,
2290				&local_mem_info);
2291	if (ret < 0)
2292		return ret;
2293
2294	crat_table->length += sizeof(struct crat_subtype_memory);
2295	crat_table->total_entries++;
2296
2297	/* Fill in Subtype: IO_LINKS
2298	 *  Only direct links are added here which is Link from GPU to
2299	 *  its NUMA node. Indirect links are added by userspace.
2300	 */
2301	sub_type_hdr = (typeof(sub_type_hdr))((char *)sub_type_hdr +
2302		sub_type_hdr->length);
2303	ret = kfd_fill_gpu_direct_io_link_to_cpu(&avail_size, kdev,
2304		(struct crat_subtype_iolink *)sub_type_hdr, proximity_domain);
2305
2306	if (ret < 0)
2307		return ret;
2308
2309	crat_table->length += sub_type_hdr->length;
2310	crat_table->total_entries++;
2311
2312
2313	/* Fill in Subtype: IO_LINKS
2314	 * Direct links from GPU to other GPUs through xGMI.
2315	 * We will loop GPUs that already be processed (with lower value
2316	 * of proximity_domain), add the link for the GPUs with same
2317	 * hive id (from this GPU to other GPU) . The reversed iolink
2318	 * (from other GPU to this GPU) will be added
2319	 * in kfd_parse_subtype_iolink.
2320	 */
2321	if (kdev->kfd->hive_id) {
2322		for (nid = 0; nid < proximity_domain; ++nid) {
2323			peer_dev = kfd_topology_device_by_proximity_domain_no_lock(nid);
2324			if (!peer_dev->gpu)
2325				continue;
2326			if (peer_dev->gpu->kfd->hive_id != kdev->kfd->hive_id)
2327				continue;
2328			sub_type_hdr = (typeof(sub_type_hdr))(
2329				(char *)sub_type_hdr +
2330				sizeof(struct crat_subtype_iolink));
2331			ret = kfd_fill_gpu_xgmi_link_to_gpu(
2332				&avail_size, kdev, peer_dev->gpu,
2333				(struct crat_subtype_iolink *)sub_type_hdr,
2334				proximity_domain, nid);
2335			if (ret < 0)
2336				return ret;
2337			crat_table->length += sub_type_hdr->length;
2338			crat_table->total_entries++;
2339		}
2340	}
2341	*size = crat_table->length;
2342	pr_info("Virtual CRAT table created for GPU\n");
2343
2344	return ret;
2345}
2346
2347/* kfd_create_crat_image_virtual - Allocates memory for CRAT image and
2348 *		creates a Virtual CRAT (VCRAT) image
2349 *
2350 * NOTE: Call kfd_destroy_crat_image to free CRAT image memory
2351 *
2352 *	@crat_image: VCRAT image created because ACPI does not have a
2353 *		     CRAT for this device
2354 *	@size: [OUT] size of virtual crat_image
2355 *	@flags:	COMPUTE_UNIT_CPU - Create VCRAT for CPU device
2356 *		COMPUTE_UNIT_GPU - Create VCRAT for GPU
2357 *		(COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU) - Create VCRAT for APU
2358 *			-- this option is not currently implemented.
2359 *			The assumption is that all AMD APUs will have CRAT
2360 *	@kdev: Valid kfd_node required if flags contain COMPUTE_UNIT_GPU
2361 *
2362 *	Return 0 if successful else return -ve value
2363 */
2364int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
2365				  int flags, struct kfd_node *kdev,
2366				  uint32_t proximity_domain)
2367{
2368	void *pcrat_image = NULL;
2369	int ret = 0, num_nodes;
2370	size_t dyn_size;
2371
2372	if (!crat_image)
2373		return -EINVAL;
2374
2375	*crat_image = NULL;
2376
2377	/* Allocate the CPU Virtual CRAT size based on the number of online
2378	 * nodes. Allocate VCRAT_SIZE_FOR_GPU for GPU virtual CRAT image.
2379	 * This should cover all the current conditions. A check is put not
2380	 * to overwrite beyond allocated size for GPUs
2381	 */
2382	switch (flags) {
2383	case COMPUTE_UNIT_CPU:
2384		num_nodes = num_online_nodes();
2385		dyn_size = sizeof(struct crat_header) +
2386			num_nodes * (sizeof(struct crat_subtype_computeunit) +
2387			sizeof(struct crat_subtype_memory) +
2388			(num_nodes - 1) * sizeof(struct crat_subtype_iolink));
2389		pcrat_image = kvmalloc(dyn_size, GFP_KERNEL);
2390		if (!pcrat_image)
2391			return -ENOMEM;
2392		*size = dyn_size;
2393		pr_debug("CRAT size is %ld", dyn_size);
2394		ret = kfd_create_vcrat_image_cpu(pcrat_image, size);
2395		break;
2396	case COMPUTE_UNIT_GPU:
2397		if (!kdev)
2398			return -EINVAL;
2399		pcrat_image = kvmalloc(VCRAT_SIZE_FOR_GPU, GFP_KERNEL);
2400		if (!pcrat_image)
2401			return -ENOMEM;
2402		*size = VCRAT_SIZE_FOR_GPU;
2403		ret = kfd_create_vcrat_image_gpu(pcrat_image, size, kdev,
2404						 proximity_domain);
2405		break;
2406	case (COMPUTE_UNIT_CPU | COMPUTE_UNIT_GPU):
2407		/* TODO: */
2408		ret = -EINVAL;
2409		pr_err("VCRAT not implemented for APU\n");
2410		break;
2411	default:
2412		ret = -EINVAL;
2413	}
2414
2415	if (!ret)
2416		*crat_image = pcrat_image;
2417	else
2418		kvfree(pcrat_image);
2419
2420	return ret;
2421}
2422
2423
2424/* kfd_destroy_crat_image
2425 *
2426 *	@crat_image: [IN] - crat_image from kfd_create_crat_image_xxx(..)
2427 *
2428 */
2429void kfd_destroy_crat_image(void *crat_image)
2430{
2431	kvfree(crat_image);
2432}