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1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu_ras.h"
24#include "amdgpu.h"
25#include "amdgpu_mca.h"
26
27#define smnMCMP0_STATUST0 0x03830408
28#define smnMCMP1_STATUST0 0x03b30408
29#define smnMCMPIO_STATUST0 0x0c930408
30
31
32static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
33 void *ras_error_status)
34{
35 amdgpu_mca_query_ras_error_count(adev,
36 smnMCMP0_STATUST0,
37 ras_error_status);
38}
39
40static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
41 enum amdgpu_ras_block block, uint32_t sub_block_index)
42{
43 if (!block_obj)
44 return -EINVAL;
45
46 if ((block_obj->ras_comm.block == block) &&
47 (block_obj->ras_comm.sub_block_index == sub_block_index)) {
48 return 0;
49 }
50
51 return -EINVAL;
52}
53
54static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
55 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
56 .query_ras_error_address = NULL,
57};
58
59struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
60 .ras_block = {
61 .hw_ops = &mca_v3_0_mp0_hw_ops,
62 .ras_block_match = mca_v3_0_ras_block_match,
63 },
64};
65
66static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
67 void *ras_error_status)
68{
69 amdgpu_mca_query_ras_error_count(adev,
70 smnMCMP1_STATUST0,
71 ras_error_status);
72}
73
74static const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
75 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
76 .query_ras_error_address = NULL,
77};
78
79struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
80 .ras_block = {
81 .hw_ops = &mca_v3_0_mp1_hw_ops,
82 .ras_block_match = mca_v3_0_ras_block_match,
83 },
84};
85
86static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
87 void *ras_error_status)
88{
89 amdgpu_mca_query_ras_error_count(adev,
90 smnMCMPIO_STATUST0,
91 ras_error_status);
92}
93
94static const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
95 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
96 .query_ras_error_address = NULL,
97};
98
99struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
100 .ras_block = {
101 .hw_ops = &mca_v3_0_mpio_hw_ops,
102 .ras_block_match = mca_v3_0_ras_block_match,
103 },
104};
1/*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu_ras.h"
24#include "amdgpu.h"
25#include "amdgpu_mca.h"
26
27#define smnMCMP0_STATUST0 0x03830408
28#define smnMCMP1_STATUST0 0x03b30408
29#define smnMCMPIO_STATUST0 0x0c930408
30
31
32static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
33 void *ras_error_status)
34{
35 amdgpu_mca_query_ras_error_count(adev,
36 smnMCMP0_STATUST0,
37 ras_error_status);
38}
39
40static int mca_v3_0_ras_block_match(struct amdgpu_ras_block_object *block_obj,
41 enum amdgpu_ras_block block, uint32_t sub_block_index)
42{
43 if (!block_obj)
44 return -EINVAL;
45
46 if ((block_obj->ras_comm.block == block) &&
47 (block_obj->ras_comm.sub_block_index == sub_block_index)) {
48 return 0;
49 }
50
51 return -EINVAL;
52}
53
54const struct amdgpu_ras_block_hw_ops mca_v3_0_mp0_hw_ops = {
55 .query_ras_error_count = mca_v3_0_mp0_query_ras_error_count,
56 .query_ras_error_address = NULL,
57};
58
59struct amdgpu_mca_ras_block mca_v3_0_mp0_ras = {
60 .ras_block = {
61 .ras_comm = {
62 .block = AMDGPU_RAS_BLOCK__MCA,
63 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP0,
64 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
65 .name = "mp0",
66 },
67 .hw_ops = &mca_v3_0_mp0_hw_ops,
68 .ras_block_match = mca_v3_0_ras_block_match,
69 },
70};
71
72static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
73 void *ras_error_status)
74{
75 amdgpu_mca_query_ras_error_count(adev,
76 smnMCMP1_STATUST0,
77 ras_error_status);
78}
79
80const struct amdgpu_ras_block_hw_ops mca_v3_0_mp1_hw_ops = {
81 .query_ras_error_count = mca_v3_0_mp1_query_ras_error_count,
82 .query_ras_error_address = NULL,
83};
84
85struct amdgpu_mca_ras_block mca_v3_0_mp1_ras = {
86 .ras_block = {
87 .ras_comm = {
88 .block = AMDGPU_RAS_BLOCK__MCA,
89 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MP1,
90 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
91 .name = "mp1",
92 },
93 .hw_ops = &mca_v3_0_mp1_hw_ops,
94 .ras_block_match = mca_v3_0_ras_block_match,
95 },
96};
97
98static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
99 void *ras_error_status)
100{
101 amdgpu_mca_query_ras_error_count(adev,
102 smnMCMPIO_STATUST0,
103 ras_error_status);
104}
105
106const struct amdgpu_ras_block_hw_ops mca_v3_0_mpio_hw_ops = {
107 .query_ras_error_count = mca_v3_0_mpio_query_ras_error_count,
108 .query_ras_error_address = NULL,
109};
110
111struct amdgpu_mca_ras_block mca_v3_0_mpio_ras = {
112 .ras_block = {
113 .ras_comm = {
114 .block = AMDGPU_RAS_BLOCK__MCA,
115 .sub_block_index = AMDGPU_RAS_MCA_BLOCK__MPIO,
116 .type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,
117 .name = "mpio",
118 },
119 .hw_ops = &mca_v3_0_mpio_hw_ops,
120 .ras_block_match = mca_v3_0_ras_block_match,
121 },
122};
123
124
125static void mca_v3_0_init(struct amdgpu_device *adev)
126{
127 struct amdgpu_mca *mca = &adev->mca;
128
129 mca->mp0.ras = &mca_v3_0_mp0_ras;
130 mca->mp1.ras = &mca_v3_0_mp1_ras;
131 mca->mpio.ras = &mca_v3_0_mpio_ras;
132 amdgpu_ras_register_ras_block(adev, &mca->mp0.ras->ras_block);
133 amdgpu_ras_register_ras_block(adev, &mca->mp1.ras->ras_block);
134 amdgpu_ras_register_ras_block(adev, &mca->mpio.ras->ras_block);
135 mca->mp0.ras_if = &mca->mp0.ras->ras_block.ras_comm;
136 mca->mp1.ras_if = &mca->mp1.ras->ras_block.ras_comm;
137 mca->mpio.ras_if = &mca->mpio.ras->ras_block.ras_comm;
138}
139
140const struct amdgpu_mca_funcs mca_v3_0_funcs = {
141 .init = mca_v3_0_init,
142};