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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_edid.h>
25#include <drm/drm_fourcc.h>
26#include <drm/drm_modeset_helper.h>
27#include <drm/drm_modeset_helper_vtables.h>
28#include <drm/drm_vblank.h>
29
30#include "amdgpu.h"
31#include "amdgpu_pm.h"
32#include "amdgpu_i2c.h"
33#include "vid.h"
34#include "atom.h"
35#include "amdgpu_atombios.h"
36#include "atombios_crtc.h"
37#include "atombios_encoders.h"
38#include "amdgpu_pll.h"
39#include "amdgpu_connectors.h"
40#include "amdgpu_display.h"
41#include "dce_v10_0.h"
42
43#include "dce/dce_10_0_d.h"
44#include "dce/dce_10_0_sh_mask.h"
45#include "dce/dce_10_0_enum.h"
46#include "oss/oss_3_0_d.h"
47#include "oss/oss_3_0_sh_mask.h"
48#include "gmc/gmc_8_1_d.h"
49#include "gmc/gmc_8_1_sh_mask.h"
50
51#include "ivsrcid/ivsrcid_vislands30.h"
52
53static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
54static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
55static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev, int hpd);
56
57static const u32 crtc_offsets[] = {
58 CRTC0_REGISTER_OFFSET,
59 CRTC1_REGISTER_OFFSET,
60 CRTC2_REGISTER_OFFSET,
61 CRTC3_REGISTER_OFFSET,
62 CRTC4_REGISTER_OFFSET,
63 CRTC5_REGISTER_OFFSET,
64 CRTC6_REGISTER_OFFSET
65};
66
67static const u32 hpd_offsets[] = {
68 HPD0_REGISTER_OFFSET,
69 HPD1_REGISTER_OFFSET,
70 HPD2_REGISTER_OFFSET,
71 HPD3_REGISTER_OFFSET,
72 HPD4_REGISTER_OFFSET,
73 HPD5_REGISTER_OFFSET
74};
75
76static const uint32_t dig_offsets[] = {
77 DIG0_REGISTER_OFFSET,
78 DIG1_REGISTER_OFFSET,
79 DIG2_REGISTER_OFFSET,
80 DIG3_REGISTER_OFFSET,
81 DIG4_REGISTER_OFFSET,
82 DIG5_REGISTER_OFFSET,
83 DIG6_REGISTER_OFFSET
84};
85
86static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92} interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97}, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102}, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107}, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112}, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117}, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122} };
123
124static const u32 golden_settings_tonga_a11[] = {
125 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
127 mmFBC_MISC, 0x1f311fff, 0x12300000,
128 mmHDMI_CONTROL, 0x31000111, 0x00000011,
129};
130
131static const u32 tonga_mgcg_cgcg_init[] = {
132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134};
135
136static const u32 golden_settings_fiji_a10[] = {
137 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
138 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
139 mmFBC_MISC, 0x1f311fff, 0x12300000,
140 mmHDMI_CONTROL, 0x31000111, 0x00000011,
141};
142
143static const u32 fiji_mgcg_cgcg_init[] = {
144 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
145 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
146};
147
148static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
149{
150 switch (adev->asic_type) {
151 case CHIP_FIJI:
152 amdgpu_device_program_register_sequence(adev,
153 fiji_mgcg_cgcg_init,
154 ARRAY_SIZE(fiji_mgcg_cgcg_init));
155 amdgpu_device_program_register_sequence(adev,
156 golden_settings_fiji_a10,
157 ARRAY_SIZE(golden_settings_fiji_a10));
158 break;
159 case CHIP_TONGA:
160 amdgpu_device_program_register_sequence(adev,
161 tonga_mgcg_cgcg_init,
162 ARRAY_SIZE(tonga_mgcg_cgcg_init));
163 amdgpu_device_program_register_sequence(adev,
164 golden_settings_tonga_a11,
165 ARRAY_SIZE(golden_settings_tonga_a11));
166 break;
167 default:
168 break;
169 }
170}
171
172static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
173 u32 block_offset, u32 reg)
174{
175 unsigned long flags;
176 u32 r;
177
178 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
179 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
180 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
181 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
182
183 return r;
184}
185
186static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
187 u32 block_offset, u32 reg, u32 v)
188{
189 unsigned long flags;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195}
196
197static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
198{
199 if (crtc >= adev->mode_info.num_crtc)
200 return 0;
201 else
202 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
203}
204
205static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
206{
207 unsigned i;
208
209 /* Enable pflip interrupts */
210 for (i = 0; i < adev->mode_info.num_crtc; i++)
211 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
212}
213
214static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
215{
216 unsigned i;
217
218 /* Disable pflip interrupts */
219 for (i = 0; i < adev->mode_info.num_crtc; i++)
220 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
221}
222
223/**
224 * dce_v10_0_page_flip - pageflip callback.
225 *
226 * @adev: amdgpu_device pointer
227 * @crtc_id: crtc to cleanup pageflip on
228 * @crtc_base: new address of the crtc (GPU MC address)
229 * @async: asynchronous flip
230 *
231 * Triggers the actual pageflip by updating the primary
232 * surface base address.
233 */
234static void dce_v10_0_page_flip(struct amdgpu_device *adev,
235 int crtc_id, u64 crtc_base, bool async)
236{
237 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
238 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
239 u32 tmp;
240
241 /* flip at hsync for async, default is vsync */
242 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
243 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
244 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
245 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
246 /* update pitch */
247 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
248 fb->pitches[0] / fb->format->cpp[0]);
249 /* update the primary scanout address */
250 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
251 upper_32_bits(crtc_base));
252 /* writing to the low address triggers the update */
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
254 lower_32_bits(crtc_base));
255 /* post the write */
256 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
257}
258
259static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
260 u32 *vbl, u32 *position)
261{
262 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
263 return -EINVAL;
264
265 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
266 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
267
268 return 0;
269}
270
271/**
272 * dce_v10_0_hpd_sense - hpd sense callback.
273 *
274 * @adev: amdgpu_device pointer
275 * @hpd: hpd (hotplug detect) pin
276 *
277 * Checks if a digital monitor is connected (evergreen+).
278 * Returns true if connected, false if not connected.
279 */
280static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
281 enum amdgpu_hpd_id hpd)
282{
283 bool connected = false;
284
285 if (hpd >= adev->mode_info.num_hpd)
286 return connected;
287
288 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
289 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
290 connected = true;
291
292 return connected;
293}
294
295/**
296 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
297 *
298 * @adev: amdgpu_device pointer
299 * @hpd: hpd (hotplug detect) pin
300 *
301 * Set the polarity of the hpd pin (evergreen+).
302 */
303static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
304 enum amdgpu_hpd_id hpd)
305{
306 u32 tmp;
307 bool connected = dce_v10_0_hpd_sense(adev, hpd);
308
309 if (hpd >= adev->mode_info.num_hpd)
310 return;
311
312 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
313 if (connected)
314 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
315 else
316 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
317 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
318}
319
320/**
321 * dce_v10_0_hpd_init - hpd setup callback.
322 *
323 * @adev: amdgpu_device pointer
324 *
325 * Setup the hpd pins used by the card (evergreen+).
326 * Enable the pin, set the polarity, and enable the hpd interrupts.
327 */
328static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
329{
330 struct drm_device *dev = adev_to_drm(adev);
331 struct drm_connector *connector;
332 struct drm_connector_list_iter iter;
333 u32 tmp;
334
335 drm_connector_list_iter_begin(dev, &iter);
336 drm_for_each_connector_iter(connector, &iter) {
337 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
338
339 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
340 continue;
341
342 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
343 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
344 /* don't try to enable hpd on eDP or LVDS avoid breaking the
345 * aux dp channel on imac and help (but not completely fix)
346 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
347 * also avoid interrupt storms during dpms.
348 */
349 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
350 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
351 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
352 continue;
353 }
354
355 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
357 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358
359 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
361 DC_HPD_CONNECT_INT_DELAY,
362 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
363 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
364 DC_HPD_DISCONNECT_INT_DELAY,
365 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
366 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
367
368 dce_v10_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
369 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
370 amdgpu_irq_get(adev, &adev->hpd_irq,
371 amdgpu_connector->hpd.hpd);
372 }
373 drm_connector_list_iter_end(&iter);
374}
375
376/**
377 * dce_v10_0_hpd_fini - hpd tear down callback.
378 *
379 * @adev: amdgpu_device pointer
380 *
381 * Tear down the hpd pins used by the card (evergreen+).
382 * Disable the hpd interrupts.
383 */
384static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
385{
386 struct drm_device *dev = adev_to_drm(adev);
387 struct drm_connector *connector;
388 struct drm_connector_list_iter iter;
389 u32 tmp;
390
391 drm_connector_list_iter_begin(dev, &iter);
392 drm_for_each_connector_iter(connector, &iter) {
393 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
394
395 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
396 continue;
397
398 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
399 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
400 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
401
402 amdgpu_irq_put(adev, &adev->hpd_irq,
403 amdgpu_connector->hpd.hpd);
404 }
405 drm_connector_list_iter_end(&iter);
406}
407
408static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
409{
410 return mmDC_GPIO_HPD_A;
411}
412
413static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
414{
415 u32 crtc_hung = 0;
416 u32 crtc_status[6];
417 u32 i, j, tmp;
418
419 for (i = 0; i < adev->mode_info.num_crtc; i++) {
420 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
421 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
422 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
423 crtc_hung |= (1 << i);
424 }
425 }
426
427 for (j = 0; j < 10; j++) {
428 for (i = 0; i < adev->mode_info.num_crtc; i++) {
429 if (crtc_hung & (1 << i)) {
430 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
431 if (tmp != crtc_status[i])
432 crtc_hung &= ~(1 << i);
433 }
434 }
435 if (crtc_hung == 0)
436 return false;
437 udelay(100);
438 }
439
440 return true;
441}
442
443static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
444 bool render)
445{
446 u32 tmp;
447
448 /* Lockout access through VGA aperture*/
449 tmp = RREG32(mmVGA_HDP_CONTROL);
450 if (render)
451 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
452 else
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
454 WREG32(mmVGA_HDP_CONTROL, tmp);
455
456 /* disable VGA render */
457 tmp = RREG32(mmVGA_RENDER_CONTROL);
458 if (render)
459 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
460 else
461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
462 WREG32(mmVGA_RENDER_CONTROL, tmp);
463}
464
465static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
466{
467 int num_crtc = 0;
468
469 switch (adev->asic_type) {
470 case CHIP_FIJI:
471 case CHIP_TONGA:
472 num_crtc = 6;
473 break;
474 default:
475 num_crtc = 0;
476 }
477 return num_crtc;
478}
479
480void dce_v10_0_disable_dce(struct amdgpu_device *adev)
481{
482 /*Disable VGA render and enabled crtc, if has DCE engine*/
483 if (amdgpu_atombios_has_dce_engine_info(adev)) {
484 u32 tmp;
485 int crtc_enabled, i;
486
487 dce_v10_0_set_vga_render_state(adev, false);
488
489 /*Disable crtc*/
490 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
491 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
492 CRTC_CONTROL, CRTC_MASTER_EN);
493 if (crtc_enabled) {
494 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
495 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
496 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
497 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
498 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
499 }
500 }
501 }
502}
503
504static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
505{
506 struct drm_device *dev = encoder->dev;
507 struct amdgpu_device *adev = drm_to_adev(dev);
508 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
509 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
510 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
511 int bpc = 0;
512 u32 tmp = 0;
513 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
514
515 if (connector) {
516 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
517 bpc = amdgpu_connector_get_monitor_bpc(connector);
518 dither = amdgpu_connector->dither;
519 }
520
521 /* LVDS/eDP FMT is set up by atom */
522 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
523 return;
524
525 /* not needed for analog */
526 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
527 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
528 return;
529
530 if (bpc == 0)
531 return;
532
533 switch (bpc) {
534 case 6:
535 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
536 /* XXX sort out optimal dither settings */
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
538 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
541 } else {
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
544 }
545 break;
546 case 8:
547 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
548 /* XXX sort out optimal dither settings */
549 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
554 } else {
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
556 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
557 }
558 break;
559 case 10:
560 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
561 /* XXX sort out optimal dither settings */
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
570 }
571 break;
572 default:
573 /* not needed */
574 break;
575 }
576
577 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
578}
579
580
581/* display watermark setup */
582/**
583 * dce_v10_0_line_buffer_adjust - Set up the line buffer
584 *
585 * @adev: amdgpu_device pointer
586 * @amdgpu_crtc: the selected display controller
587 * @mode: the current display mode on the selected display
588 * controller
589 *
590 * Setup up the line buffer allocation for
591 * the selected display controller (CIK).
592 * Returns the line buffer size in pixels.
593 */
594static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
595 struct amdgpu_crtc *amdgpu_crtc,
596 struct drm_display_mode *mode)
597{
598 u32 tmp, buffer_alloc, i, mem_cfg;
599 u32 pipe_offset = amdgpu_crtc->crtc_id;
600 /*
601 * Line Buffer Setup
602 * There are 6 line buffers, one for each display controllers.
603 * There are 3 partitions per LB. Select the number of partitions
604 * to enable based on the display width. For display widths larger
605 * than 4096, you need use to use 2 display controllers and combine
606 * them using the stereo blender.
607 */
608 if (amdgpu_crtc->base.enabled && mode) {
609 if (mode->crtc_hdisplay < 1920) {
610 mem_cfg = 1;
611 buffer_alloc = 2;
612 } else if (mode->crtc_hdisplay < 2560) {
613 mem_cfg = 2;
614 buffer_alloc = 2;
615 } else if (mode->crtc_hdisplay < 4096) {
616 mem_cfg = 0;
617 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
618 } else {
619 DRM_DEBUG_KMS("Mode too big for LB!\n");
620 mem_cfg = 0;
621 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
622 }
623 } else {
624 mem_cfg = 1;
625 buffer_alloc = 0;
626 }
627
628 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
629 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
630 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
631
632 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
633 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
634 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
635
636 for (i = 0; i < adev->usec_timeout; i++) {
637 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
638 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
639 break;
640 udelay(1);
641 }
642
643 if (amdgpu_crtc->base.enabled && mode) {
644 switch (mem_cfg) {
645 case 0:
646 default:
647 return 4096 * 2;
648 case 1:
649 return 1920 * 2;
650 case 2:
651 return 2560 * 2;
652 }
653 }
654
655 /* controller not enabled, so no lb used */
656 return 0;
657}
658
659/**
660 * cik_get_number_of_dram_channels - get the number of dram channels
661 *
662 * @adev: amdgpu_device pointer
663 *
664 * Look up the number of video ram channels (CIK).
665 * Used for display watermark bandwidth calculations
666 * Returns the number of dram channels
667 */
668static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
669{
670 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
671
672 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
673 case 0:
674 default:
675 return 1;
676 case 1:
677 return 2;
678 case 2:
679 return 4;
680 case 3:
681 return 8;
682 case 4:
683 return 3;
684 case 5:
685 return 6;
686 case 6:
687 return 10;
688 case 7:
689 return 12;
690 case 8:
691 return 16;
692 }
693}
694
695struct dce10_wm_params {
696 u32 dram_channels; /* number of dram channels */
697 u32 yclk; /* bandwidth per dram data pin in kHz */
698 u32 sclk; /* engine clock in kHz */
699 u32 disp_clk; /* display clock in kHz */
700 u32 src_width; /* viewport width */
701 u32 active_time; /* active display time in ns */
702 u32 blank_time; /* blank time in ns */
703 bool interlaced; /* mode is interlaced */
704 fixed20_12 vsc; /* vertical scale ratio */
705 u32 num_heads; /* number of active crtcs */
706 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
707 u32 lb_size; /* line buffer allocated to pipe */
708 u32 vtaps; /* vertical scaler taps */
709};
710
711/**
712 * dce_v10_0_dram_bandwidth - get the dram bandwidth
713 *
714 * @wm: watermark calculation data
715 *
716 * Calculate the raw dram bandwidth (CIK).
717 * Used for display watermark bandwidth calculations
718 * Returns the dram bandwidth in MBytes/s
719 */
720static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
721{
722 /* Calculate raw DRAM Bandwidth */
723 fixed20_12 dram_efficiency; /* 0.7 */
724 fixed20_12 yclk, dram_channels, bandwidth;
725 fixed20_12 a;
726
727 a.full = dfixed_const(1000);
728 yclk.full = dfixed_const(wm->yclk);
729 yclk.full = dfixed_div(yclk, a);
730 dram_channels.full = dfixed_const(wm->dram_channels * 4);
731 a.full = dfixed_const(10);
732 dram_efficiency.full = dfixed_const(7);
733 dram_efficiency.full = dfixed_div(dram_efficiency, a);
734 bandwidth.full = dfixed_mul(dram_channels, yclk);
735 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
736
737 return dfixed_trunc(bandwidth);
738}
739
740/**
741 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
742 *
743 * @wm: watermark calculation data
744 *
745 * Calculate the dram bandwidth used for display (CIK).
746 * Used for display watermark bandwidth calculations
747 * Returns the dram bandwidth for display in MBytes/s
748 */
749static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
750{
751 /* Calculate DRAM Bandwidth and the part allocated to display. */
752 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
753 fixed20_12 yclk, dram_channels, bandwidth;
754 fixed20_12 a;
755
756 a.full = dfixed_const(1000);
757 yclk.full = dfixed_const(wm->yclk);
758 yclk.full = dfixed_div(yclk, a);
759 dram_channels.full = dfixed_const(wm->dram_channels * 4);
760 a.full = dfixed_const(10);
761 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
762 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
763 bandwidth.full = dfixed_mul(dram_channels, yclk);
764 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
765
766 return dfixed_trunc(bandwidth);
767}
768
769/**
770 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
771 *
772 * @wm: watermark calculation data
773 *
774 * Calculate the data return bandwidth used for display (CIK).
775 * Used for display watermark bandwidth calculations
776 * Returns the data return bandwidth in MBytes/s
777 */
778static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
779{
780 /* Calculate the display Data return Bandwidth */
781 fixed20_12 return_efficiency; /* 0.8 */
782 fixed20_12 sclk, bandwidth;
783 fixed20_12 a;
784
785 a.full = dfixed_const(1000);
786 sclk.full = dfixed_const(wm->sclk);
787 sclk.full = dfixed_div(sclk, a);
788 a.full = dfixed_const(10);
789 return_efficiency.full = dfixed_const(8);
790 return_efficiency.full = dfixed_div(return_efficiency, a);
791 a.full = dfixed_const(32);
792 bandwidth.full = dfixed_mul(a, sclk);
793 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
794
795 return dfixed_trunc(bandwidth);
796}
797
798/**
799 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
800 *
801 * @wm: watermark calculation data
802 *
803 * Calculate the dmif bandwidth used for display (CIK).
804 * Used for display watermark bandwidth calculations
805 * Returns the dmif bandwidth in MBytes/s
806 */
807static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
808{
809 /* Calculate the DMIF Request Bandwidth */
810 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
811 fixed20_12 disp_clk, bandwidth;
812 fixed20_12 a, b;
813
814 a.full = dfixed_const(1000);
815 disp_clk.full = dfixed_const(wm->disp_clk);
816 disp_clk.full = dfixed_div(disp_clk, a);
817 a.full = dfixed_const(32);
818 b.full = dfixed_mul(a, disp_clk);
819
820 a.full = dfixed_const(10);
821 disp_clk_request_efficiency.full = dfixed_const(8);
822 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
823
824 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
825
826 return dfixed_trunc(bandwidth);
827}
828
829/**
830 * dce_v10_0_available_bandwidth - get the min available bandwidth
831 *
832 * @wm: watermark calculation data
833 *
834 * Calculate the min available bandwidth used for display (CIK).
835 * Used for display watermark bandwidth calculations
836 * Returns the min available bandwidth in MBytes/s
837 */
838static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
839{
840 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
841 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
842 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
843 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
844
845 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
846}
847
848/**
849 * dce_v10_0_average_bandwidth - get the average available bandwidth
850 *
851 * @wm: watermark calculation data
852 *
853 * Calculate the average available bandwidth used for display (CIK).
854 * Used for display watermark bandwidth calculations
855 * Returns the average available bandwidth in MBytes/s
856 */
857static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
858{
859 /* Calculate the display mode Average Bandwidth
860 * DisplayMode should contain the source and destination dimensions,
861 * timing, etc.
862 */
863 fixed20_12 bpp;
864 fixed20_12 line_time;
865 fixed20_12 src_width;
866 fixed20_12 bandwidth;
867 fixed20_12 a;
868
869 a.full = dfixed_const(1000);
870 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
871 line_time.full = dfixed_div(line_time, a);
872 bpp.full = dfixed_const(wm->bytes_per_pixel);
873 src_width.full = dfixed_const(wm->src_width);
874 bandwidth.full = dfixed_mul(src_width, bpp);
875 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
876 bandwidth.full = dfixed_div(bandwidth, line_time);
877
878 return dfixed_trunc(bandwidth);
879}
880
881/**
882 * dce_v10_0_latency_watermark - get the latency watermark
883 *
884 * @wm: watermark calculation data
885 *
886 * Calculate the latency watermark (CIK).
887 * Used for display watermark bandwidth calculations
888 * Returns the latency watermark in ns
889 */
890static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
891{
892 /* First calculate the latency in ns */
893 u32 mc_latency = 2000; /* 2000 ns. */
894 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
895 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
896 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
897 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
898 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
899 (wm->num_heads * cursor_line_pair_return_time);
900 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
901 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
902 u32 tmp, dmif_size = 12288;
903 fixed20_12 a, b, c;
904
905 if (wm->num_heads == 0)
906 return 0;
907
908 a.full = dfixed_const(2);
909 b.full = dfixed_const(1);
910 if ((wm->vsc.full > a.full) ||
911 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
912 (wm->vtaps >= 5) ||
913 ((wm->vsc.full >= a.full) && wm->interlaced))
914 max_src_lines_per_dst_line = 4;
915 else
916 max_src_lines_per_dst_line = 2;
917
918 a.full = dfixed_const(available_bandwidth);
919 b.full = dfixed_const(wm->num_heads);
920 a.full = dfixed_div(a, b);
921 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
922 tmp = min(dfixed_trunc(a), tmp);
923
924 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
925
926 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
927 b.full = dfixed_const(1000);
928 c.full = dfixed_const(lb_fill_bw);
929 b.full = dfixed_div(c, b);
930 a.full = dfixed_div(a, b);
931 line_fill_time = dfixed_trunc(a);
932
933 if (line_fill_time < wm->active_time)
934 return latency;
935 else
936 return latency + (line_fill_time - wm->active_time);
937
938}
939
940/**
941 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
942 * average and available dram bandwidth
943 *
944 * @wm: watermark calculation data
945 *
946 * Check if the display average bandwidth fits in the display
947 * dram bandwidth (CIK).
948 * Used for display watermark bandwidth calculations
949 * Returns true if the display fits, false if not.
950 */
951static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
952{
953 if (dce_v10_0_average_bandwidth(wm) <=
954 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
955 return true;
956 else
957 return false;
958}
959
960/**
961 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
962 * average and available bandwidth
963 *
964 * @wm: watermark calculation data
965 *
966 * Check if the display average bandwidth fits in the display
967 * available bandwidth (CIK).
968 * Used for display watermark bandwidth calculations
969 * Returns true if the display fits, false if not.
970 */
971static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
972{
973 if (dce_v10_0_average_bandwidth(wm) <=
974 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
975 return true;
976 else
977 return false;
978}
979
980/**
981 * dce_v10_0_check_latency_hiding - check latency hiding
982 *
983 * @wm: watermark calculation data
984 *
985 * Check latency hiding (CIK).
986 * Used for display watermark bandwidth calculations
987 * Returns true if the display fits, false if not.
988 */
989static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
990{
991 u32 lb_partitions = wm->lb_size / wm->src_width;
992 u32 line_time = wm->active_time + wm->blank_time;
993 u32 latency_tolerant_lines;
994 u32 latency_hiding;
995 fixed20_12 a;
996
997 a.full = dfixed_const(1);
998 if (wm->vsc.full > a.full)
999 latency_tolerant_lines = 1;
1000 else {
1001 if (lb_partitions <= (wm->vtaps + 1))
1002 latency_tolerant_lines = 1;
1003 else
1004 latency_tolerant_lines = 2;
1005 }
1006
1007 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1008
1009 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1010 return true;
1011 else
1012 return false;
1013}
1014
1015/**
1016 * dce_v10_0_program_watermarks - program display watermarks
1017 *
1018 * @adev: amdgpu_device pointer
1019 * @amdgpu_crtc: the selected display controller
1020 * @lb_size: line buffer size
1021 * @num_heads: number of display controllers in use
1022 *
1023 * Calculate and program the display watermarks for the
1024 * selected display controller (CIK).
1025 */
1026static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1027 struct amdgpu_crtc *amdgpu_crtc,
1028 u32 lb_size, u32 num_heads)
1029{
1030 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1031 struct dce10_wm_params wm_low, wm_high;
1032 u32 active_time;
1033 u32 line_time = 0;
1034 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1035 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1036
1037 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1038 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1039 (u32)mode->clock);
1040 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1041 (u32)mode->clock);
1042 line_time = min_t(u32, line_time, 65535);
1043
1044 /* watermark for high clocks */
1045 if (adev->pm.dpm_enabled) {
1046 wm_high.yclk =
1047 amdgpu_dpm_get_mclk(adev, false) * 10;
1048 wm_high.sclk =
1049 amdgpu_dpm_get_sclk(adev, false) * 10;
1050 } else {
1051 wm_high.yclk = adev->pm.current_mclk * 10;
1052 wm_high.sclk = adev->pm.current_sclk * 10;
1053 }
1054
1055 wm_high.disp_clk = mode->clock;
1056 wm_high.src_width = mode->crtc_hdisplay;
1057 wm_high.active_time = active_time;
1058 wm_high.blank_time = line_time - wm_high.active_time;
1059 wm_high.interlaced = false;
1060 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1061 wm_high.interlaced = true;
1062 wm_high.vsc = amdgpu_crtc->vsc;
1063 wm_high.vtaps = 1;
1064 if (amdgpu_crtc->rmx_type != RMX_OFF)
1065 wm_high.vtaps = 2;
1066 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1067 wm_high.lb_size = lb_size;
1068 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1069 wm_high.num_heads = num_heads;
1070
1071 /* set for high clocks */
1072 latency_watermark_a = min_t(u32, dce_v10_0_latency_watermark(&wm_high), 65535);
1073
1074 /* possibly force display priority to high */
1075 /* should really do this at mode validation time... */
1076 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1077 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1078 !dce_v10_0_check_latency_hiding(&wm_high) ||
1079 (adev->mode_info.disp_priority == 2)) {
1080 DRM_DEBUG_KMS("force priority to high\n");
1081 }
1082
1083 /* watermark for low clocks */
1084 if (adev->pm.dpm_enabled) {
1085 wm_low.yclk =
1086 amdgpu_dpm_get_mclk(adev, true) * 10;
1087 wm_low.sclk =
1088 amdgpu_dpm_get_sclk(adev, true) * 10;
1089 } else {
1090 wm_low.yclk = adev->pm.current_mclk * 10;
1091 wm_low.sclk = adev->pm.current_sclk * 10;
1092 }
1093
1094 wm_low.disp_clk = mode->clock;
1095 wm_low.src_width = mode->crtc_hdisplay;
1096 wm_low.active_time = active_time;
1097 wm_low.blank_time = line_time - wm_low.active_time;
1098 wm_low.interlaced = false;
1099 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1100 wm_low.interlaced = true;
1101 wm_low.vsc = amdgpu_crtc->vsc;
1102 wm_low.vtaps = 1;
1103 if (amdgpu_crtc->rmx_type != RMX_OFF)
1104 wm_low.vtaps = 2;
1105 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1106 wm_low.lb_size = lb_size;
1107 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1108 wm_low.num_heads = num_heads;
1109
1110 /* set for low clocks */
1111 latency_watermark_b = min_t(u32, dce_v10_0_latency_watermark(&wm_low), 65535);
1112
1113 /* possibly force display priority to high */
1114 /* should really do this at mode validation time... */
1115 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1116 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1117 !dce_v10_0_check_latency_hiding(&wm_low) ||
1118 (adev->mode_info.disp_priority == 2)) {
1119 DRM_DEBUG_KMS("force priority to high\n");
1120 }
1121 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1122 }
1123
1124 /* select wm A */
1125 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1126 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1127 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1128 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1129 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1130 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1131 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1132 /* select wm B */
1133 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1134 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1135 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1136 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1137 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1138 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1139 /* restore original selection */
1140 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1141
1142 /* save values for DPM */
1143 amdgpu_crtc->line_time = line_time;
1144 amdgpu_crtc->wm_high = latency_watermark_a;
1145 amdgpu_crtc->wm_low = latency_watermark_b;
1146 /* Save number of lines the linebuffer leads before the scanout */
1147 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1148}
1149
1150/**
1151 * dce_v10_0_bandwidth_update - program display watermarks
1152 *
1153 * @adev: amdgpu_device pointer
1154 *
1155 * Calculate and program the display watermarks and line
1156 * buffer allocation (CIK).
1157 */
1158static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1159{
1160 struct drm_display_mode *mode = NULL;
1161 u32 num_heads = 0, lb_size;
1162 int i;
1163
1164 amdgpu_display_update_priority(adev);
1165
1166 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1167 if (adev->mode_info.crtcs[i]->base.enabled)
1168 num_heads++;
1169 }
1170 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1171 mode = &adev->mode_info.crtcs[i]->base.mode;
1172 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1173 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1174 lb_size, num_heads);
1175 }
1176}
1177
1178static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1179{
1180 int i;
1181 u32 offset, tmp;
1182
1183 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1184 offset = adev->mode_info.audio.pin[i].offset;
1185 tmp = RREG32_AUDIO_ENDPT(offset,
1186 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1187 if (((tmp &
1188 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1189 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1190 adev->mode_info.audio.pin[i].connected = false;
1191 else
1192 adev->mode_info.audio.pin[i].connected = true;
1193 }
1194}
1195
1196static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1197{
1198 int i;
1199
1200 dce_v10_0_audio_get_connected_pins(adev);
1201
1202 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1203 if (adev->mode_info.audio.pin[i].connected)
1204 return &adev->mode_info.audio.pin[i];
1205 }
1206 DRM_ERROR("No connected audio pins found!\n");
1207 return NULL;
1208}
1209
1210static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1211{
1212 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1213 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1214 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1215 u32 tmp;
1216
1217 if (!dig || !dig->afmt || !dig->afmt->pin)
1218 return;
1219
1220 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1221 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1222 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1223}
1224
1225static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1226 struct drm_display_mode *mode)
1227{
1228 struct drm_device *dev = encoder->dev;
1229 struct amdgpu_device *adev = drm_to_adev(dev);
1230 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1231 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1232 struct drm_connector *connector;
1233 struct drm_connector_list_iter iter;
1234 struct amdgpu_connector *amdgpu_connector = NULL;
1235 u32 tmp;
1236 int interlace = 0;
1237
1238 if (!dig || !dig->afmt || !dig->afmt->pin)
1239 return;
1240
1241 drm_connector_list_iter_begin(dev, &iter);
1242 drm_for_each_connector_iter(connector, &iter) {
1243 if (connector->encoder == encoder) {
1244 amdgpu_connector = to_amdgpu_connector(connector);
1245 break;
1246 }
1247 }
1248 drm_connector_list_iter_end(&iter);
1249
1250 if (!amdgpu_connector) {
1251 DRM_ERROR("Couldn't find encoder's connector\n");
1252 return;
1253 }
1254
1255 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1256 interlace = 1;
1257 if (connector->latency_present[interlace]) {
1258 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1259 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1260 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1261 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1262 } else {
1263 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1264 VIDEO_LIPSYNC, 0);
1265 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1266 AUDIO_LIPSYNC, 0);
1267 }
1268 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1269 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1270}
1271
1272static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1273{
1274 struct drm_device *dev = encoder->dev;
1275 struct amdgpu_device *adev = drm_to_adev(dev);
1276 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1277 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1278 struct drm_connector *connector;
1279 struct drm_connector_list_iter iter;
1280 struct amdgpu_connector *amdgpu_connector = NULL;
1281 u32 tmp;
1282 u8 *sadb = NULL;
1283 int sad_count;
1284
1285 if (!dig || !dig->afmt || !dig->afmt->pin)
1286 return;
1287
1288 drm_connector_list_iter_begin(dev, &iter);
1289 drm_for_each_connector_iter(connector, &iter) {
1290 if (connector->encoder == encoder) {
1291 amdgpu_connector = to_amdgpu_connector(connector);
1292 break;
1293 }
1294 }
1295 drm_connector_list_iter_end(&iter);
1296
1297 if (!amdgpu_connector) {
1298 DRM_ERROR("Couldn't find encoder's connector\n");
1299 return;
1300 }
1301
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1303 if (sad_count < 0) {
1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 sad_count = 0;
1306 }
1307
1308 /* program the speaker allocation */
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1310 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1311 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 DP_CONNECTION, 0);
1313 /* set HDMI mode */
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 HDMI_CONNECTION, 1);
1316 if (sad_count)
1317 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 SPEAKER_ALLOCATION, sadb[0]);
1319 else
1320 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1321 SPEAKER_ALLOCATION, 5); /* stereo */
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1323 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1324
1325 kfree(sadb);
1326}
1327
1328static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1329{
1330 struct drm_device *dev = encoder->dev;
1331 struct amdgpu_device *adev = drm_to_adev(dev);
1332 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1333 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1334 struct drm_connector *connector;
1335 struct drm_connector_list_iter iter;
1336 struct amdgpu_connector *amdgpu_connector = NULL;
1337 struct cea_sad *sads;
1338 int i, sad_count;
1339
1340 static const u16 eld_reg_to_type[][2] = {
1341 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1342 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1353 };
1354
1355 if (!dig || !dig->afmt || !dig->afmt->pin)
1356 return;
1357
1358 drm_connector_list_iter_begin(dev, &iter);
1359 drm_for_each_connector_iter(connector, &iter) {
1360 if (connector->encoder == encoder) {
1361 amdgpu_connector = to_amdgpu_connector(connector);
1362 break;
1363 }
1364 }
1365 drm_connector_list_iter_end(&iter);
1366
1367 if (!amdgpu_connector) {
1368 DRM_ERROR("Couldn't find encoder's connector\n");
1369 return;
1370 }
1371
1372 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1373 if (sad_count < 0)
1374 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1375 if (sad_count <= 0)
1376 return;
1377 BUG_ON(!sads);
1378
1379 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1380 u32 tmp = 0;
1381 u8 stereo_freqs = 0;
1382 int max_channels = -1;
1383 int j;
1384
1385 for (j = 0; j < sad_count; j++) {
1386 struct cea_sad *sad = &sads[j];
1387
1388 if (sad->format == eld_reg_to_type[i][1]) {
1389 if (sad->channels > max_channels) {
1390 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391 MAX_CHANNELS, sad->channels);
1392 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393 DESCRIPTOR_BYTE_2, sad->byte2);
1394 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1395 SUPPORTED_FREQUENCIES, sad->freq);
1396 max_channels = sad->channels;
1397 }
1398
1399 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1400 stereo_freqs |= sad->freq;
1401 else
1402 break;
1403 }
1404 }
1405
1406 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1407 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1408 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1409 }
1410
1411 kfree(sads);
1412}
1413
1414static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1415 struct amdgpu_audio_pin *pin,
1416 bool enable)
1417{
1418 if (!pin)
1419 return;
1420
1421 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1422 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1423}
1424
1425static const u32 pin_offsets[] = {
1426 AUD0_REGISTER_OFFSET,
1427 AUD1_REGISTER_OFFSET,
1428 AUD2_REGISTER_OFFSET,
1429 AUD3_REGISTER_OFFSET,
1430 AUD4_REGISTER_OFFSET,
1431 AUD5_REGISTER_OFFSET,
1432 AUD6_REGISTER_OFFSET,
1433};
1434
1435static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1436{
1437 int i;
1438
1439 if (!amdgpu_audio)
1440 return 0;
1441
1442 adev->mode_info.audio.enabled = true;
1443
1444 adev->mode_info.audio.num_pins = 7;
1445
1446 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1447 adev->mode_info.audio.pin[i].channels = -1;
1448 adev->mode_info.audio.pin[i].rate = -1;
1449 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1450 adev->mode_info.audio.pin[i].status_bits = 0;
1451 adev->mode_info.audio.pin[i].category_code = 0;
1452 adev->mode_info.audio.pin[i].connected = false;
1453 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1454 adev->mode_info.audio.pin[i].id = i;
1455 /* disable audio. it will be set up later */
1456 /* XXX remove once we switch to ip funcs */
1457 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1458 }
1459
1460 return 0;
1461}
1462
1463static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1464{
1465 int i;
1466
1467 if (!amdgpu_audio)
1468 return;
1469
1470 if (!adev->mode_info.audio.enabled)
1471 return;
1472
1473 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1474 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1475
1476 adev->mode_info.audio.enabled = false;
1477}
1478
1479/*
1480 * update the N and CTS parameters for a given pixel clock rate
1481 */
1482static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1483{
1484 struct drm_device *dev = encoder->dev;
1485 struct amdgpu_device *adev = drm_to_adev(dev);
1486 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1487 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1488 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1489 u32 tmp;
1490
1491 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1492 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1493 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1494 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1496 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1497
1498 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1499 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1500 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1501 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1503 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1504
1505 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1506 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1507 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1508 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1510 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1511
1512}
1513
1514/*
1515 * build a HDMI Video Info Frame
1516 */
1517static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1518 void *buffer, size_t size)
1519{
1520 struct drm_device *dev = encoder->dev;
1521 struct amdgpu_device *adev = drm_to_adev(dev);
1522 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1523 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1524 uint8_t *frame = buffer + 3;
1525 uint8_t *header = buffer;
1526
1527 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1528 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1529 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1530 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1531 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1532 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1533 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1534 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1535}
1536
1537static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1538{
1539 struct drm_device *dev = encoder->dev;
1540 struct amdgpu_device *adev = drm_to_adev(dev);
1541 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1542 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1543 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1544 u32 dto_phase = 24 * 1000;
1545 u32 dto_modulo = clock;
1546 u32 tmp;
1547
1548 if (!dig || !dig->afmt)
1549 return;
1550
1551 /* XXX two dtos; generally use dto0 for hdmi */
1552 /* Express [24MHz / target pixel clock] as an exact rational
1553 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1554 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1555 */
1556 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1557 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1558 amdgpu_crtc->crtc_id);
1559 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1560 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1561 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1562}
1563
1564/*
1565 * update the info frames with the data from the current display mode
1566 */
1567static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1568 struct drm_display_mode *mode)
1569{
1570 struct drm_device *dev = encoder->dev;
1571 struct amdgpu_device *adev = drm_to_adev(dev);
1572 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1573 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1574 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1575 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1576 struct hdmi_avi_infoframe frame;
1577 ssize_t err;
1578 u32 tmp;
1579 int bpc = 8;
1580
1581 if (!dig || !dig->afmt)
1582 return;
1583
1584 /* Silent, r600_hdmi_enable will raise WARN for us */
1585 if (!dig->afmt->enabled)
1586 return;
1587
1588 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1589 if (encoder->crtc) {
1590 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1591 bpc = amdgpu_crtc->bpc;
1592 }
1593
1594 /* disable audio prior to setting up hw */
1595 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1596 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1597
1598 dce_v10_0_audio_set_dto(encoder, mode->clock);
1599
1600 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1601 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1602 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1603
1604 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1605
1606 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1607 switch (bpc) {
1608 case 0:
1609 case 6:
1610 case 8:
1611 case 16:
1612 default:
1613 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1614 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1615 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1616 connector->name, bpc);
1617 break;
1618 case 10:
1619 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1620 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1621 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1622 connector->name);
1623 break;
1624 case 12:
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1627 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1628 connector->name);
1629 break;
1630 }
1631 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1632
1633 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1634 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1635 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1636 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1637 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1638
1639 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1640 /* enable audio info frames (frames won't be set until audio is enabled) */
1641 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1642 /* required for audio info values to be updated */
1643 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1644 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1645
1646 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1647 /* required for audio info values to be updated */
1648 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1649 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1650
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1652 /* anything other than 0 */
1653 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1654 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1655
1656 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1657
1658 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1659 /* set the default audio delay */
1660 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1661 /* should be suffient for all audio modes and small enough for all hblanks */
1662 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1663 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1664
1665 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1666 /* allow 60958 channel status fields to be updated */
1667 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1668 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1669
1670 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1671 if (bpc > 8)
1672 /* clear SW CTS value */
1673 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1674 else
1675 /* select SW CTS value */
1676 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1677 /* allow hw to sent ACR packets when required */
1678 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1679 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1680
1681 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1682
1683 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1684 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1685 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1686
1687 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1688 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1689 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1690
1691 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1692 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1693 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1694 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1695 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1696 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1697 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1698 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1699
1700 dce_v10_0_audio_write_speaker_allocation(encoder);
1701
1702 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1703 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1704
1705 dce_v10_0_afmt_audio_select_pin(encoder);
1706 dce_v10_0_audio_write_sad_regs(encoder);
1707 dce_v10_0_audio_write_latency_fields(encoder, mode);
1708
1709 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1710 if (err < 0) {
1711 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1712 return;
1713 }
1714
1715 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1716 if (err < 0) {
1717 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1718 return;
1719 }
1720
1721 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1722
1723 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1724 /* enable AVI info frames */
1725 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1726 /* required for audio info values to be updated */
1727 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1728 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1729
1730 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1731 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1732 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1733
1734 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1735 /* send audio packets */
1736 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1737 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1738
1739 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1740 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1741 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1742 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1743
1744 /* enable audio after to setting up hw */
1745 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1746}
1747
1748static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1749{
1750 struct drm_device *dev = encoder->dev;
1751 struct amdgpu_device *adev = drm_to_adev(dev);
1752 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1753 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1754
1755 if (!dig || !dig->afmt)
1756 return;
1757
1758 /* Silent, r600_hdmi_enable will raise WARN for us */
1759 if (enable && dig->afmt->enabled)
1760 return;
1761 if (!enable && !dig->afmt->enabled)
1762 return;
1763
1764 if (!enable && dig->afmt->pin) {
1765 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1766 dig->afmt->pin = NULL;
1767 }
1768
1769 dig->afmt->enabled = enable;
1770
1771 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1772 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1773}
1774
1775static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1776{
1777 int i;
1778
1779 for (i = 0; i < adev->mode_info.num_dig; i++)
1780 adev->mode_info.afmt[i] = NULL;
1781
1782 /* DCE10 has audio blocks tied to DIG encoders */
1783 for (i = 0; i < adev->mode_info.num_dig; i++) {
1784 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1785 if (adev->mode_info.afmt[i]) {
1786 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1787 adev->mode_info.afmt[i]->id = i;
1788 } else {
1789 int j;
1790 for (j = 0; j < i; j++) {
1791 kfree(adev->mode_info.afmt[j]);
1792 adev->mode_info.afmt[j] = NULL;
1793 }
1794 return -ENOMEM;
1795 }
1796 }
1797 return 0;
1798}
1799
1800static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1801{
1802 int i;
1803
1804 for (i = 0; i < adev->mode_info.num_dig; i++) {
1805 kfree(adev->mode_info.afmt[i]);
1806 adev->mode_info.afmt[i] = NULL;
1807 }
1808}
1809
1810static const u32 vga_control_regs[6] = {
1811 mmD1VGA_CONTROL,
1812 mmD2VGA_CONTROL,
1813 mmD3VGA_CONTROL,
1814 mmD4VGA_CONTROL,
1815 mmD5VGA_CONTROL,
1816 mmD6VGA_CONTROL,
1817};
1818
1819static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1820{
1821 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1822 struct drm_device *dev = crtc->dev;
1823 struct amdgpu_device *adev = drm_to_adev(dev);
1824 u32 vga_control;
1825
1826 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1827 if (enable)
1828 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1829 else
1830 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1831}
1832
1833static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1834{
1835 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1836 struct drm_device *dev = crtc->dev;
1837 struct amdgpu_device *adev = drm_to_adev(dev);
1838
1839 if (enable)
1840 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1841 else
1842 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1843}
1844
1845static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1846 struct drm_framebuffer *fb,
1847 int x, int y, int atomic)
1848{
1849 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1850 struct drm_device *dev = crtc->dev;
1851 struct amdgpu_device *adev = drm_to_adev(dev);
1852 struct drm_framebuffer *target_fb;
1853 struct drm_gem_object *obj;
1854 struct amdgpu_bo *abo;
1855 uint64_t fb_location, tiling_flags;
1856 uint32_t fb_format, fb_pitch_pixels;
1857 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1858 u32 pipe_config;
1859 u32 tmp, viewport_w, viewport_h;
1860 int r;
1861 bool bypass_lut = false;
1862
1863 /* no fb bound */
1864 if (!atomic && !crtc->primary->fb) {
1865 DRM_DEBUG_KMS("No FB bound\n");
1866 return 0;
1867 }
1868
1869 if (atomic)
1870 target_fb = fb;
1871 else
1872 target_fb = crtc->primary->fb;
1873
1874 /* If atomic, assume fb object is pinned & idle & fenced and
1875 * just update base pointers
1876 */
1877 obj = target_fb->obj[0];
1878 abo = gem_to_amdgpu_bo(obj);
1879 r = amdgpu_bo_reserve(abo, false);
1880 if (unlikely(r != 0))
1881 return r;
1882
1883 if (!atomic) {
1884 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1885 if (unlikely(r != 0)) {
1886 amdgpu_bo_unreserve(abo);
1887 return -EINVAL;
1888 }
1889 }
1890 fb_location = amdgpu_bo_gpu_offset(abo);
1891
1892 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1893 amdgpu_bo_unreserve(abo);
1894
1895 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1896
1897 switch (target_fb->format->format) {
1898 case DRM_FORMAT_C8:
1899 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1900 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1901 break;
1902 case DRM_FORMAT_XRGB4444:
1903 case DRM_FORMAT_ARGB4444:
1904 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1905 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1906#ifdef __BIG_ENDIAN
1907 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1908 ENDIAN_8IN16);
1909#endif
1910 break;
1911 case DRM_FORMAT_XRGB1555:
1912 case DRM_FORMAT_ARGB1555:
1913 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1914 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1915#ifdef __BIG_ENDIAN
1916 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1917 ENDIAN_8IN16);
1918#endif
1919 break;
1920 case DRM_FORMAT_BGRX5551:
1921 case DRM_FORMAT_BGRA5551:
1922 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1923 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1924#ifdef __BIG_ENDIAN
1925 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1926 ENDIAN_8IN16);
1927#endif
1928 break;
1929 case DRM_FORMAT_RGB565:
1930 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1931 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1932#ifdef __BIG_ENDIAN
1933 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1934 ENDIAN_8IN16);
1935#endif
1936 break;
1937 case DRM_FORMAT_XRGB8888:
1938 case DRM_FORMAT_ARGB8888:
1939 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1940 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1941#ifdef __BIG_ENDIAN
1942 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1943 ENDIAN_8IN32);
1944#endif
1945 break;
1946 case DRM_FORMAT_XRGB2101010:
1947 case DRM_FORMAT_ARGB2101010:
1948 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1949 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1950#ifdef __BIG_ENDIAN
1951 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1952 ENDIAN_8IN32);
1953#endif
1954 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1955 bypass_lut = true;
1956 break;
1957 case DRM_FORMAT_BGRX1010102:
1958 case DRM_FORMAT_BGRA1010102:
1959 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1960 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1961#ifdef __BIG_ENDIAN
1962 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1963 ENDIAN_8IN32);
1964#endif
1965 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1966 bypass_lut = true;
1967 break;
1968 case DRM_FORMAT_XBGR8888:
1969 case DRM_FORMAT_ABGR8888:
1970 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1971 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1972 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1973 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1974#ifdef __BIG_ENDIAN
1975 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1976 ENDIAN_8IN32);
1977#endif
1978 break;
1979 default:
1980 DRM_ERROR("Unsupported screen format %p4cc\n",
1981 &target_fb->format->format);
1982 return -EINVAL;
1983 }
1984
1985 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1986 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1987
1988 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1989 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1990 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1991 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1992 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1993
1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1995 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
1996 ARRAY_2D_TILED_THIN1);
1997 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
1998 tile_split);
1999 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2000 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2001 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2002 mtaspect);
2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2004 ADDR_SURF_MICRO_TILING_DISPLAY);
2005 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2006 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2007 ARRAY_1D_TILED_THIN1);
2008 }
2009
2010 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2011 pipe_config);
2012
2013 dce_v10_0_vga_enable(crtc, false);
2014
2015 /* Make sure surface address is updated at vertical blank rather than
2016 * horizontal blank
2017 */
2018 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2019 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2020 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2021 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2022
2023 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2024 upper_32_bits(fb_location));
2025 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2026 upper_32_bits(fb_location));
2027 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2028 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2029 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2030 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2031 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2032 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2033
2034 /*
2035 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2036 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2037 * retain the full precision throughout the pipeline.
2038 */
2039 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2040 if (bypass_lut)
2041 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2042 else
2043 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2044 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2045
2046 if (bypass_lut)
2047 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2048
2049 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2050 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2051 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2052 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2053 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2054 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2055
2056 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2057 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2058
2059 dce_v10_0_grph_enable(crtc, true);
2060
2061 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2062 target_fb->height);
2063
2064 x &= ~3;
2065 y &= ~1;
2066 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2067 (x << 16) | y);
2068 viewport_w = crtc->mode.hdisplay;
2069 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2070 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2071 (viewport_w << 16) | viewport_h);
2072
2073 /* set pageflip to happen anywhere in vblank interval */
2074 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2075
2076 if (!atomic && fb && fb != crtc->primary->fb) {
2077 abo = gem_to_amdgpu_bo(fb->obj[0]);
2078 r = amdgpu_bo_reserve(abo, true);
2079 if (unlikely(r != 0))
2080 return r;
2081 amdgpu_bo_unpin(abo);
2082 amdgpu_bo_unreserve(abo);
2083 }
2084
2085 /* Bytes per pixel may have changed */
2086 dce_v10_0_bandwidth_update(adev);
2087
2088 return 0;
2089}
2090
2091static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2092 struct drm_display_mode *mode)
2093{
2094 struct drm_device *dev = crtc->dev;
2095 struct amdgpu_device *adev = drm_to_adev(dev);
2096 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2097 u32 tmp;
2098
2099 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2100 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2101 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2102 else
2103 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2104 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2105}
2106
2107static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2108{
2109 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2110 struct drm_device *dev = crtc->dev;
2111 struct amdgpu_device *adev = drm_to_adev(dev);
2112 u16 *r, *g, *b;
2113 int i;
2114 u32 tmp;
2115
2116 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2117
2118 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2119 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2120 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2121 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2122
2123 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2124 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2125 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2126
2127 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2128 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2129 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2130
2131 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2132 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2133 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2134 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2135
2136 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2137
2138 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2139 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2140 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2141
2142 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2143 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2144 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2145
2146 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2147 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2148
2149 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2150 r = crtc->gamma_store;
2151 g = r + crtc->gamma_size;
2152 b = g + crtc->gamma_size;
2153 for (i = 0; i < 256; i++) {
2154 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2155 ((*r++ & 0xffc0) << 14) |
2156 ((*g++ & 0xffc0) << 4) |
2157 (*b++ >> 6));
2158 }
2159
2160 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2161 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2162 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2163 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2164 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2165
2166 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2167 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2168 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2169 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170
2171 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2172 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2173 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2174 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2175
2176 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2177 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2178 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2179 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2180
2181 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2182 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2183 /* XXX this only needs to be programmed once per crtc at startup,
2184 * not sure where the best place for it is
2185 */
2186 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2187 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2188 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2189}
2190
2191static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2192{
2193 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2194 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2195
2196 switch (amdgpu_encoder->encoder_id) {
2197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2198 if (dig->linkb)
2199 return 1;
2200 else
2201 return 0;
2202 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2203 if (dig->linkb)
2204 return 3;
2205 else
2206 return 2;
2207 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2208 if (dig->linkb)
2209 return 5;
2210 else
2211 return 4;
2212 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2213 return 6;
2214 default:
2215 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2216 return 0;
2217 }
2218}
2219
2220/**
2221 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2222 *
2223 * @crtc: drm crtc
2224 *
2225 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2226 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2227 * monitors a dedicated PPLL must be used. If a particular board has
2228 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2229 * as there is no need to program the PLL itself. If we are not able to
2230 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2231 * avoid messing up an existing monitor.
2232 *
2233 * Asic specific PLL information
2234 *
2235 * DCE 10.x
2236 * Tonga
2237 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2238 * CI
2239 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2240 *
2241 */
2242static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2243{
2244 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2245 struct drm_device *dev = crtc->dev;
2246 struct amdgpu_device *adev = drm_to_adev(dev);
2247 u32 pll_in_use;
2248 int pll;
2249
2250 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2251 if (adev->clock.dp_extclk)
2252 /* skip PPLL programming if using ext clock */
2253 return ATOM_PPLL_INVALID;
2254 else {
2255 /* use the same PPLL for all DP monitors */
2256 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2257 if (pll != ATOM_PPLL_INVALID)
2258 return pll;
2259 }
2260 } else {
2261 /* use the same PPLL for all monitors with the same clock */
2262 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2263 if (pll != ATOM_PPLL_INVALID)
2264 return pll;
2265 }
2266
2267 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2268 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2269 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2270 return ATOM_PPLL2;
2271 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2272 return ATOM_PPLL1;
2273 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2274 return ATOM_PPLL0;
2275 DRM_ERROR("unable to allocate a PPLL\n");
2276 return ATOM_PPLL_INVALID;
2277}
2278
2279static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2280{
2281 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2282 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2283 uint32_t cur_lock;
2284
2285 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2286 if (lock)
2287 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2288 else
2289 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2290 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2291}
2292
2293static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2294{
2295 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2296 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2297 u32 tmp;
2298
2299 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2300 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2301 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2302}
2303
2304static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2305{
2306 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2307 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2308 u32 tmp;
2309
2310 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2311 upper_32_bits(amdgpu_crtc->cursor_addr));
2312 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2313 lower_32_bits(amdgpu_crtc->cursor_addr));
2314
2315 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2316 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2317 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2318 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2319}
2320
2321static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2322 int x, int y)
2323{
2324 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2325 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2326 int xorigin = 0, yorigin = 0;
2327
2328 amdgpu_crtc->cursor_x = x;
2329 amdgpu_crtc->cursor_y = y;
2330
2331 /* avivo cursor are offset into the total surface */
2332 x += crtc->x;
2333 y += crtc->y;
2334 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2335
2336 if (x < 0) {
2337 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2338 x = 0;
2339 }
2340 if (y < 0) {
2341 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2342 y = 0;
2343 }
2344
2345 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2346 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2347 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2348 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2349
2350 return 0;
2351}
2352
2353static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2354 int x, int y)
2355{
2356 int ret;
2357
2358 dce_v10_0_lock_cursor(crtc, true);
2359 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2360 dce_v10_0_lock_cursor(crtc, false);
2361
2362 return ret;
2363}
2364
2365static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2366 struct drm_file *file_priv,
2367 uint32_t handle,
2368 uint32_t width,
2369 uint32_t height,
2370 int32_t hot_x,
2371 int32_t hot_y)
2372{
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374 struct drm_gem_object *obj;
2375 struct amdgpu_bo *aobj;
2376 int ret;
2377
2378 if (!handle) {
2379 /* turn off cursor */
2380 dce_v10_0_hide_cursor(crtc);
2381 obj = NULL;
2382 goto unpin;
2383 }
2384
2385 if ((width > amdgpu_crtc->max_cursor_width) ||
2386 (height > amdgpu_crtc->max_cursor_height)) {
2387 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2388 return -EINVAL;
2389 }
2390
2391 obj = drm_gem_object_lookup(file_priv, handle);
2392 if (!obj) {
2393 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2394 return -ENOENT;
2395 }
2396
2397 aobj = gem_to_amdgpu_bo(obj);
2398 ret = amdgpu_bo_reserve(aobj, false);
2399 if (ret != 0) {
2400 drm_gem_object_put(obj);
2401 return ret;
2402 }
2403
2404 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2405 amdgpu_bo_unreserve(aobj);
2406 if (ret) {
2407 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2408 drm_gem_object_put(obj);
2409 return ret;
2410 }
2411 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2412
2413 dce_v10_0_lock_cursor(crtc, true);
2414
2415 if (width != amdgpu_crtc->cursor_width ||
2416 height != amdgpu_crtc->cursor_height ||
2417 hot_x != amdgpu_crtc->cursor_hot_x ||
2418 hot_y != amdgpu_crtc->cursor_hot_y) {
2419 int x, y;
2420
2421 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2422 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2423
2424 dce_v10_0_cursor_move_locked(crtc, x, y);
2425
2426 amdgpu_crtc->cursor_width = width;
2427 amdgpu_crtc->cursor_height = height;
2428 amdgpu_crtc->cursor_hot_x = hot_x;
2429 amdgpu_crtc->cursor_hot_y = hot_y;
2430 }
2431
2432 dce_v10_0_show_cursor(crtc);
2433 dce_v10_0_lock_cursor(crtc, false);
2434
2435unpin:
2436 if (amdgpu_crtc->cursor_bo) {
2437 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2438 ret = amdgpu_bo_reserve(aobj, true);
2439 if (likely(ret == 0)) {
2440 amdgpu_bo_unpin(aobj);
2441 amdgpu_bo_unreserve(aobj);
2442 }
2443 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2444 }
2445
2446 amdgpu_crtc->cursor_bo = obj;
2447 return 0;
2448}
2449
2450static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2451{
2452 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2453
2454 if (amdgpu_crtc->cursor_bo) {
2455 dce_v10_0_lock_cursor(crtc, true);
2456
2457 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2458 amdgpu_crtc->cursor_y);
2459
2460 dce_v10_0_show_cursor(crtc);
2461
2462 dce_v10_0_lock_cursor(crtc, false);
2463 }
2464}
2465
2466static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2467 u16 *blue, uint32_t size,
2468 struct drm_modeset_acquire_ctx *ctx)
2469{
2470 dce_v10_0_crtc_load_lut(crtc);
2471
2472 return 0;
2473}
2474
2475static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2476{
2477 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2478
2479 drm_crtc_cleanup(crtc);
2480 kfree(amdgpu_crtc);
2481}
2482
2483static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2484 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2485 .cursor_move = dce_v10_0_crtc_cursor_move,
2486 .gamma_set = dce_v10_0_crtc_gamma_set,
2487 .set_config = amdgpu_display_crtc_set_config,
2488 .destroy = dce_v10_0_crtc_destroy,
2489 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2490 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2491 .enable_vblank = amdgpu_enable_vblank_kms,
2492 .disable_vblank = amdgpu_disable_vblank_kms,
2493 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2494};
2495
2496static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2497{
2498 struct drm_device *dev = crtc->dev;
2499 struct amdgpu_device *adev = drm_to_adev(dev);
2500 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2501 unsigned type;
2502
2503 switch (mode) {
2504 case DRM_MODE_DPMS_ON:
2505 amdgpu_crtc->enabled = true;
2506 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2507 dce_v10_0_vga_enable(crtc, true);
2508 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2509 dce_v10_0_vga_enable(crtc, false);
2510 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2511 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2512 amdgpu_crtc->crtc_id);
2513 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2514 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2515 drm_crtc_vblank_on(crtc);
2516 dce_v10_0_crtc_load_lut(crtc);
2517 break;
2518 case DRM_MODE_DPMS_STANDBY:
2519 case DRM_MODE_DPMS_SUSPEND:
2520 case DRM_MODE_DPMS_OFF:
2521 drm_crtc_vblank_off(crtc);
2522 if (amdgpu_crtc->enabled) {
2523 dce_v10_0_vga_enable(crtc, true);
2524 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2525 dce_v10_0_vga_enable(crtc, false);
2526 }
2527 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2528 amdgpu_crtc->enabled = false;
2529 break;
2530 }
2531 /* adjust pm to dpms */
2532 amdgpu_dpm_compute_clocks(adev);
2533}
2534
2535static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2536{
2537 /* disable crtc pair power gating before programming */
2538 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2539 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2540 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2541}
2542
2543static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2544{
2545 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2546 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2547}
2548
2549static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2550{
2551 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2552 struct drm_device *dev = crtc->dev;
2553 struct amdgpu_device *adev = drm_to_adev(dev);
2554 struct amdgpu_atom_ss ss;
2555 int i;
2556
2557 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2558 if (crtc->primary->fb) {
2559 int r;
2560 struct amdgpu_bo *abo;
2561
2562 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2563 r = amdgpu_bo_reserve(abo, true);
2564 if (unlikely(r))
2565 DRM_ERROR("failed to reserve abo before unpin\n");
2566 else {
2567 amdgpu_bo_unpin(abo);
2568 amdgpu_bo_unreserve(abo);
2569 }
2570 }
2571 /* disable the GRPH */
2572 dce_v10_0_grph_enable(crtc, false);
2573
2574 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2575
2576 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2577 if (adev->mode_info.crtcs[i] &&
2578 adev->mode_info.crtcs[i]->enabled &&
2579 i != amdgpu_crtc->crtc_id &&
2580 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2581 /* one other crtc is using this pll don't turn
2582 * off the pll
2583 */
2584 goto done;
2585 }
2586 }
2587
2588 switch (amdgpu_crtc->pll_id) {
2589 case ATOM_PPLL0:
2590 case ATOM_PPLL1:
2591 case ATOM_PPLL2:
2592 /* disable the ppll */
2593 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2594 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2595 break;
2596 default:
2597 break;
2598 }
2599done:
2600 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2601 amdgpu_crtc->adjusted_clock = 0;
2602 amdgpu_crtc->encoder = NULL;
2603 amdgpu_crtc->connector = NULL;
2604}
2605
2606static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2607 struct drm_display_mode *mode,
2608 struct drm_display_mode *adjusted_mode,
2609 int x, int y, struct drm_framebuffer *old_fb)
2610{
2611 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2612
2613 if (!amdgpu_crtc->adjusted_clock)
2614 return -EINVAL;
2615
2616 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2617 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2618 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2619 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2620 amdgpu_atombios_crtc_scaler_setup(crtc);
2621 dce_v10_0_cursor_reset(crtc);
2622 /* update the hw version fpr dpm */
2623 amdgpu_crtc->hw_mode = *adjusted_mode;
2624
2625 return 0;
2626}
2627
2628static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2629 const struct drm_display_mode *mode,
2630 struct drm_display_mode *adjusted_mode)
2631{
2632 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2633 struct drm_device *dev = crtc->dev;
2634 struct drm_encoder *encoder;
2635
2636 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2637 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2638 if (encoder->crtc == crtc) {
2639 amdgpu_crtc->encoder = encoder;
2640 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2641 break;
2642 }
2643 }
2644 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2645 amdgpu_crtc->encoder = NULL;
2646 amdgpu_crtc->connector = NULL;
2647 return false;
2648 }
2649 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2650 return false;
2651 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2652 return false;
2653 /* pick pll */
2654 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2655 /* if we can't get a PPLL for a non-DP encoder, fail */
2656 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2657 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2658 return false;
2659
2660 return true;
2661}
2662
2663static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2664 struct drm_framebuffer *old_fb)
2665{
2666 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2667}
2668
2669static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2670 struct drm_framebuffer *fb,
2671 int x, int y, enum mode_set_atomic state)
2672{
2673 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2674}
2675
2676static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2677 .dpms = dce_v10_0_crtc_dpms,
2678 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2679 .mode_set = dce_v10_0_crtc_mode_set,
2680 .mode_set_base = dce_v10_0_crtc_set_base,
2681 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2682 .prepare = dce_v10_0_crtc_prepare,
2683 .commit = dce_v10_0_crtc_commit,
2684 .disable = dce_v10_0_crtc_disable,
2685 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2686};
2687
2688static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2689{
2690 struct amdgpu_crtc *amdgpu_crtc;
2691
2692 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2693 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2694 if (amdgpu_crtc == NULL)
2695 return -ENOMEM;
2696
2697 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2698
2699 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2700 amdgpu_crtc->crtc_id = index;
2701 adev->mode_info.crtcs[index] = amdgpu_crtc;
2702
2703 amdgpu_crtc->max_cursor_width = 128;
2704 amdgpu_crtc->max_cursor_height = 128;
2705 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2706 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2707
2708 switch (amdgpu_crtc->crtc_id) {
2709 case 0:
2710 default:
2711 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2712 break;
2713 case 1:
2714 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2715 break;
2716 case 2:
2717 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2718 break;
2719 case 3:
2720 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2721 break;
2722 case 4:
2723 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2724 break;
2725 case 5:
2726 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2727 break;
2728 }
2729
2730 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2731 amdgpu_crtc->adjusted_clock = 0;
2732 amdgpu_crtc->encoder = NULL;
2733 amdgpu_crtc->connector = NULL;
2734 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2735
2736 return 0;
2737}
2738
2739static int dce_v10_0_early_init(void *handle)
2740{
2741 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2742
2743 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2744 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2745
2746 dce_v10_0_set_display_funcs(adev);
2747
2748 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2749
2750 switch (adev->asic_type) {
2751 case CHIP_FIJI:
2752 case CHIP_TONGA:
2753 adev->mode_info.num_hpd = 6;
2754 adev->mode_info.num_dig = 7;
2755 break;
2756 default:
2757 /* FIXME: not supported yet */
2758 return -EINVAL;
2759 }
2760
2761 dce_v10_0_set_irq_funcs(adev);
2762
2763 return 0;
2764}
2765
2766static int dce_v10_0_sw_init(void *handle)
2767{
2768 int r, i;
2769 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2770
2771 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2772 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2773 if (r)
2774 return r;
2775 }
2776
2777 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2778 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2779 if (r)
2780 return r;
2781 }
2782
2783 /* HPD hotplug */
2784 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2785 if (r)
2786 return r;
2787
2788 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2789
2790 adev_to_drm(adev)->mode_config.async_page_flip = true;
2791
2792 adev_to_drm(adev)->mode_config.max_width = 16384;
2793 adev_to_drm(adev)->mode_config.max_height = 16384;
2794
2795 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2796 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2797
2798 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2799
2800 r = amdgpu_display_modeset_create_props(adev);
2801 if (r)
2802 return r;
2803
2804 adev_to_drm(adev)->mode_config.max_width = 16384;
2805 adev_to_drm(adev)->mode_config.max_height = 16384;
2806
2807 /* allocate crtcs */
2808 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2809 r = dce_v10_0_crtc_init(adev, i);
2810 if (r)
2811 return r;
2812 }
2813
2814 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2815 amdgpu_display_print_display_setup(adev_to_drm(adev));
2816 else
2817 return -EINVAL;
2818
2819 /* setup afmt */
2820 r = dce_v10_0_afmt_init(adev);
2821 if (r)
2822 return r;
2823
2824 r = dce_v10_0_audio_init(adev);
2825 if (r)
2826 return r;
2827
2828 /* Disable vblank IRQs aggressively for power-saving */
2829 /* XXX: can this be enabled for DC? */
2830 adev_to_drm(adev)->vblank_disable_immediate = true;
2831
2832 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2833 if (r)
2834 return r;
2835
2836 INIT_DELAYED_WORK(&adev->hotplug_work,
2837 amdgpu_display_hotplug_work_func);
2838
2839 drm_kms_helper_poll_init(adev_to_drm(adev));
2840
2841 adev->mode_info.mode_config_initialized = true;
2842 return 0;
2843}
2844
2845static int dce_v10_0_sw_fini(void *handle)
2846{
2847 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2848
2849 kfree(adev->mode_info.bios_hardcoded_edid);
2850
2851 drm_kms_helper_poll_fini(adev_to_drm(adev));
2852
2853 dce_v10_0_audio_fini(adev);
2854
2855 dce_v10_0_afmt_fini(adev);
2856
2857 drm_mode_config_cleanup(adev_to_drm(adev));
2858 adev->mode_info.mode_config_initialized = false;
2859
2860 return 0;
2861}
2862
2863static int dce_v10_0_hw_init(void *handle)
2864{
2865 int i;
2866 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2867
2868 dce_v10_0_init_golden_registers(adev);
2869
2870 /* disable vga render */
2871 dce_v10_0_set_vga_render_state(adev, false);
2872 /* init dig PHYs, disp eng pll */
2873 amdgpu_atombios_encoder_init_dig(adev);
2874 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2875
2876 /* initialize hpd */
2877 dce_v10_0_hpd_init(adev);
2878
2879 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2880 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2881 }
2882
2883 dce_v10_0_pageflip_interrupt_init(adev);
2884
2885 return 0;
2886}
2887
2888static int dce_v10_0_hw_fini(void *handle)
2889{
2890 int i;
2891 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2892
2893 dce_v10_0_hpd_fini(adev);
2894
2895 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2896 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2897 }
2898
2899 dce_v10_0_pageflip_interrupt_fini(adev);
2900
2901 flush_delayed_work(&adev->hotplug_work);
2902
2903 return 0;
2904}
2905
2906static int dce_v10_0_suspend(void *handle)
2907{
2908 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2909 int r;
2910
2911 r = amdgpu_display_suspend_helper(adev);
2912 if (r)
2913 return r;
2914
2915 adev->mode_info.bl_level =
2916 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2917
2918 return dce_v10_0_hw_fini(handle);
2919}
2920
2921static int dce_v10_0_resume(void *handle)
2922{
2923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2924 int ret;
2925
2926 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2927 adev->mode_info.bl_level);
2928
2929 ret = dce_v10_0_hw_init(handle);
2930
2931 /* turn on the BL */
2932 if (adev->mode_info.bl_encoder) {
2933 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2934 adev->mode_info.bl_encoder);
2935 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2936 bl_level);
2937 }
2938 if (ret)
2939 return ret;
2940
2941 return amdgpu_display_resume_helper(adev);
2942}
2943
2944static bool dce_v10_0_is_idle(void *handle)
2945{
2946 return true;
2947}
2948
2949static int dce_v10_0_wait_for_idle(void *handle)
2950{
2951 return 0;
2952}
2953
2954static bool dce_v10_0_check_soft_reset(void *handle)
2955{
2956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2957
2958 return dce_v10_0_is_display_hung(adev);
2959}
2960
2961static int dce_v10_0_soft_reset(void *handle)
2962{
2963 u32 srbm_soft_reset = 0, tmp;
2964 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2965
2966 if (dce_v10_0_is_display_hung(adev))
2967 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2968
2969 if (srbm_soft_reset) {
2970 tmp = RREG32(mmSRBM_SOFT_RESET);
2971 tmp |= srbm_soft_reset;
2972 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2973 WREG32(mmSRBM_SOFT_RESET, tmp);
2974 tmp = RREG32(mmSRBM_SOFT_RESET);
2975
2976 udelay(50);
2977
2978 tmp &= ~srbm_soft_reset;
2979 WREG32(mmSRBM_SOFT_RESET, tmp);
2980 tmp = RREG32(mmSRBM_SOFT_RESET);
2981
2982 /* Wait a little for things to settle down */
2983 udelay(50);
2984 }
2985 return 0;
2986}
2987
2988static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2989 int crtc,
2990 enum amdgpu_interrupt_state state)
2991{
2992 u32 lb_interrupt_mask;
2993
2994 if (crtc >= adev->mode_info.num_crtc) {
2995 DRM_DEBUG("invalid crtc %d\n", crtc);
2996 return;
2997 }
2998
2999 switch (state) {
3000 case AMDGPU_IRQ_STATE_DISABLE:
3001 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3002 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3003 VBLANK_INTERRUPT_MASK, 0);
3004 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3005 break;
3006 case AMDGPU_IRQ_STATE_ENABLE:
3007 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3008 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3009 VBLANK_INTERRUPT_MASK, 1);
3010 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3011 break;
3012 default:
3013 break;
3014 }
3015}
3016
3017static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3018 int crtc,
3019 enum amdgpu_interrupt_state state)
3020{
3021 u32 lb_interrupt_mask;
3022
3023 if (crtc >= adev->mode_info.num_crtc) {
3024 DRM_DEBUG("invalid crtc %d\n", crtc);
3025 return;
3026 }
3027
3028 switch (state) {
3029 case AMDGPU_IRQ_STATE_DISABLE:
3030 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3031 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3032 VLINE_INTERRUPT_MASK, 0);
3033 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3034 break;
3035 case AMDGPU_IRQ_STATE_ENABLE:
3036 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3037 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3038 VLINE_INTERRUPT_MASK, 1);
3039 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3040 break;
3041 default:
3042 break;
3043 }
3044}
3045
3046static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3047 struct amdgpu_irq_src *source,
3048 unsigned hpd,
3049 enum amdgpu_interrupt_state state)
3050{
3051 u32 tmp;
3052
3053 if (hpd >= adev->mode_info.num_hpd) {
3054 DRM_DEBUG("invalid hdp %d\n", hpd);
3055 return 0;
3056 }
3057
3058 switch (state) {
3059 case AMDGPU_IRQ_STATE_DISABLE:
3060 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3061 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3062 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3063 break;
3064 case AMDGPU_IRQ_STATE_ENABLE:
3065 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3066 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3067 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3068 break;
3069 default:
3070 break;
3071 }
3072
3073 return 0;
3074}
3075
3076static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3077 struct amdgpu_irq_src *source,
3078 unsigned type,
3079 enum amdgpu_interrupt_state state)
3080{
3081 switch (type) {
3082 case AMDGPU_CRTC_IRQ_VBLANK1:
3083 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3084 break;
3085 case AMDGPU_CRTC_IRQ_VBLANK2:
3086 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3087 break;
3088 case AMDGPU_CRTC_IRQ_VBLANK3:
3089 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3090 break;
3091 case AMDGPU_CRTC_IRQ_VBLANK4:
3092 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3093 break;
3094 case AMDGPU_CRTC_IRQ_VBLANK5:
3095 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3096 break;
3097 case AMDGPU_CRTC_IRQ_VBLANK6:
3098 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3099 break;
3100 case AMDGPU_CRTC_IRQ_VLINE1:
3101 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3102 break;
3103 case AMDGPU_CRTC_IRQ_VLINE2:
3104 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3105 break;
3106 case AMDGPU_CRTC_IRQ_VLINE3:
3107 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3108 break;
3109 case AMDGPU_CRTC_IRQ_VLINE4:
3110 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3111 break;
3112 case AMDGPU_CRTC_IRQ_VLINE5:
3113 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3114 break;
3115 case AMDGPU_CRTC_IRQ_VLINE6:
3116 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3117 break;
3118 default:
3119 break;
3120 }
3121 return 0;
3122}
3123
3124static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3125 struct amdgpu_irq_src *src,
3126 unsigned type,
3127 enum amdgpu_interrupt_state state)
3128{
3129 u32 reg;
3130
3131 if (type >= adev->mode_info.num_crtc) {
3132 DRM_ERROR("invalid pageflip crtc %d\n", type);
3133 return -EINVAL;
3134 }
3135
3136 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3137 if (state == AMDGPU_IRQ_STATE_DISABLE)
3138 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3139 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3140 else
3141 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3142 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3143
3144 return 0;
3145}
3146
3147static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3148 struct amdgpu_irq_src *source,
3149 struct amdgpu_iv_entry *entry)
3150{
3151 unsigned long flags;
3152 unsigned crtc_id;
3153 struct amdgpu_crtc *amdgpu_crtc;
3154 struct amdgpu_flip_work *works;
3155
3156 crtc_id = (entry->src_id - 8) >> 1;
3157 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3158
3159 if (crtc_id >= adev->mode_info.num_crtc) {
3160 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3161 return -EINVAL;
3162 }
3163
3164 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3165 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3166 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3167 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3168
3169 /* IRQ could occur when in initial stage */
3170 if (amdgpu_crtc == NULL)
3171 return 0;
3172
3173 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3174 works = amdgpu_crtc->pflip_works;
3175 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3176 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3177 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3178 amdgpu_crtc->pflip_status,
3179 AMDGPU_FLIP_SUBMITTED);
3180 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3181 return 0;
3182 }
3183
3184 /* page flip completed. clean up */
3185 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3186 amdgpu_crtc->pflip_works = NULL;
3187
3188 /* wakeup usersapce */
3189 if (works->event)
3190 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3191
3192 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3193
3194 drm_crtc_vblank_put(&amdgpu_crtc->base);
3195 schedule_work(&works->unpin_work);
3196
3197 return 0;
3198}
3199
3200static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3201 int hpd)
3202{
3203 u32 tmp;
3204
3205 if (hpd >= adev->mode_info.num_hpd) {
3206 DRM_DEBUG("invalid hdp %d\n", hpd);
3207 return;
3208 }
3209
3210 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3211 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3212 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3213}
3214
3215static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3216 int crtc)
3217{
3218 u32 tmp;
3219
3220 if (crtc >= adev->mode_info.num_crtc) {
3221 DRM_DEBUG("invalid crtc %d\n", crtc);
3222 return;
3223 }
3224
3225 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3226 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3227 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3228}
3229
3230static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3231 int crtc)
3232{
3233 u32 tmp;
3234
3235 if (crtc >= adev->mode_info.num_crtc) {
3236 DRM_DEBUG("invalid crtc %d\n", crtc);
3237 return;
3238 }
3239
3240 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3241 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3242 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3243}
3244
3245static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3246 struct amdgpu_irq_src *source,
3247 struct amdgpu_iv_entry *entry)
3248{
3249 unsigned crtc = entry->src_id - 1;
3250 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3251 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3252
3253 switch (entry->src_data[0]) {
3254 case 0: /* vblank */
3255 if (disp_int & interrupt_status_offsets[crtc].vblank)
3256 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3257 else
3258 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3259
3260 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3261 drm_handle_vblank(adev_to_drm(adev), crtc);
3262 }
3263 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3264
3265 break;
3266 case 1: /* vline */
3267 if (disp_int & interrupt_status_offsets[crtc].vline)
3268 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3269 else
3270 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3271
3272 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3273
3274 break;
3275 default:
3276 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3277 break;
3278 }
3279
3280 return 0;
3281}
3282
3283static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3284 struct amdgpu_irq_src *source,
3285 struct amdgpu_iv_entry *entry)
3286{
3287 uint32_t disp_int, mask;
3288 unsigned hpd;
3289
3290 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3291 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3292 return 0;
3293 }
3294
3295 hpd = entry->src_data[0];
3296 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3297 mask = interrupt_status_offsets[hpd].hpd;
3298
3299 if (disp_int & mask) {
3300 dce_v10_0_hpd_int_ack(adev, hpd);
3301 schedule_delayed_work(&adev->hotplug_work, 0);
3302 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3303 }
3304
3305 return 0;
3306}
3307
3308static int dce_v10_0_set_clockgating_state(void *handle,
3309 enum amd_clockgating_state state)
3310{
3311 return 0;
3312}
3313
3314static int dce_v10_0_set_powergating_state(void *handle,
3315 enum amd_powergating_state state)
3316{
3317 return 0;
3318}
3319
3320static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3321 .name = "dce_v10_0",
3322 .early_init = dce_v10_0_early_init,
3323 .late_init = NULL,
3324 .sw_init = dce_v10_0_sw_init,
3325 .sw_fini = dce_v10_0_sw_fini,
3326 .hw_init = dce_v10_0_hw_init,
3327 .hw_fini = dce_v10_0_hw_fini,
3328 .suspend = dce_v10_0_suspend,
3329 .resume = dce_v10_0_resume,
3330 .is_idle = dce_v10_0_is_idle,
3331 .wait_for_idle = dce_v10_0_wait_for_idle,
3332 .check_soft_reset = dce_v10_0_check_soft_reset,
3333 .soft_reset = dce_v10_0_soft_reset,
3334 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3335 .set_powergating_state = dce_v10_0_set_powergating_state,
3336};
3337
3338static void
3339dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3340 struct drm_display_mode *mode,
3341 struct drm_display_mode *adjusted_mode)
3342{
3343 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3344
3345 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3346
3347 /* need to call this here rather than in prepare() since we need some crtc info */
3348 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3349
3350 /* set scaler clears this on some chips */
3351 dce_v10_0_set_interleave(encoder->crtc, mode);
3352
3353 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3354 dce_v10_0_afmt_enable(encoder, true);
3355 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3356 }
3357}
3358
3359static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3360{
3361 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3362 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3363 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3364
3365 if ((amdgpu_encoder->active_device &
3366 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3367 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3368 ENCODER_OBJECT_ID_NONE)) {
3369 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3370 if (dig) {
3371 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3372 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3373 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3374 }
3375 }
3376
3377 amdgpu_atombios_scratch_regs_lock(adev, true);
3378
3379 if (connector) {
3380 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3381
3382 /* select the clock/data port if it uses a router */
3383 if (amdgpu_connector->router.cd_valid)
3384 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3385
3386 /* turn eDP panel on for mode set */
3387 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3388 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3389 ATOM_TRANSMITTER_ACTION_POWER_ON);
3390 }
3391
3392 /* this is needed for the pll/ss setup to work correctly in some cases */
3393 amdgpu_atombios_encoder_set_crtc_source(encoder);
3394 /* set up the FMT blocks */
3395 dce_v10_0_program_fmt(encoder);
3396}
3397
3398static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3399{
3400 struct drm_device *dev = encoder->dev;
3401 struct amdgpu_device *adev = drm_to_adev(dev);
3402
3403 /* need to call this here as we need the crtc set up */
3404 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3405 amdgpu_atombios_scratch_regs_lock(adev, false);
3406}
3407
3408static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3409{
3410 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3411 struct amdgpu_encoder_atom_dig *dig;
3412
3413 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3414
3415 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3416 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3417 dce_v10_0_afmt_enable(encoder, false);
3418 dig = amdgpu_encoder->enc_priv;
3419 dig->dig_encoder = -1;
3420 }
3421 amdgpu_encoder->active_device = 0;
3422}
3423
3424/* these are handled by the primary encoders */
3425static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3426{
3427
3428}
3429
3430static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3431{
3432
3433}
3434
3435static void
3436dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3437 struct drm_display_mode *mode,
3438 struct drm_display_mode *adjusted_mode)
3439{
3440
3441}
3442
3443static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3444{
3445
3446}
3447
3448static void
3449dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3450{
3451
3452}
3453
3454static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3455 .dpms = dce_v10_0_ext_dpms,
3456 .prepare = dce_v10_0_ext_prepare,
3457 .mode_set = dce_v10_0_ext_mode_set,
3458 .commit = dce_v10_0_ext_commit,
3459 .disable = dce_v10_0_ext_disable,
3460 /* no detect for TMDS/LVDS yet */
3461};
3462
3463static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3464 .dpms = amdgpu_atombios_encoder_dpms,
3465 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3466 .prepare = dce_v10_0_encoder_prepare,
3467 .mode_set = dce_v10_0_encoder_mode_set,
3468 .commit = dce_v10_0_encoder_commit,
3469 .disable = dce_v10_0_encoder_disable,
3470 .detect = amdgpu_atombios_encoder_dig_detect,
3471};
3472
3473static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3474 .dpms = amdgpu_atombios_encoder_dpms,
3475 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3476 .prepare = dce_v10_0_encoder_prepare,
3477 .mode_set = dce_v10_0_encoder_mode_set,
3478 .commit = dce_v10_0_encoder_commit,
3479 .detect = amdgpu_atombios_encoder_dac_detect,
3480};
3481
3482static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3483{
3484 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3485 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3486 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3487 kfree(amdgpu_encoder->enc_priv);
3488 drm_encoder_cleanup(encoder);
3489 kfree(amdgpu_encoder);
3490}
3491
3492static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3493 .destroy = dce_v10_0_encoder_destroy,
3494};
3495
3496static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3497 uint32_t encoder_enum,
3498 uint32_t supported_device,
3499 u16 caps)
3500{
3501 struct drm_device *dev = adev_to_drm(adev);
3502 struct drm_encoder *encoder;
3503 struct amdgpu_encoder *amdgpu_encoder;
3504
3505 /* see if we already added it */
3506 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3507 amdgpu_encoder = to_amdgpu_encoder(encoder);
3508 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3509 amdgpu_encoder->devices |= supported_device;
3510 return;
3511 }
3512
3513 }
3514
3515 /* add a new one */
3516 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3517 if (!amdgpu_encoder)
3518 return;
3519
3520 encoder = &amdgpu_encoder->base;
3521 switch (adev->mode_info.num_crtc) {
3522 case 1:
3523 encoder->possible_crtcs = 0x1;
3524 break;
3525 case 2:
3526 default:
3527 encoder->possible_crtcs = 0x3;
3528 break;
3529 case 4:
3530 encoder->possible_crtcs = 0xf;
3531 break;
3532 case 6:
3533 encoder->possible_crtcs = 0x3f;
3534 break;
3535 }
3536
3537 amdgpu_encoder->enc_priv = NULL;
3538
3539 amdgpu_encoder->encoder_enum = encoder_enum;
3540 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3541 amdgpu_encoder->devices = supported_device;
3542 amdgpu_encoder->rmx_type = RMX_OFF;
3543 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3544 amdgpu_encoder->is_ext_encoder = false;
3545 amdgpu_encoder->caps = caps;
3546
3547 switch (amdgpu_encoder->encoder_id) {
3548 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3549 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3550 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3551 DRM_MODE_ENCODER_DAC, NULL);
3552 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3553 break;
3554 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3555 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3556 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3557 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3558 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3559 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3560 amdgpu_encoder->rmx_type = RMX_FULL;
3561 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3562 DRM_MODE_ENCODER_LVDS, NULL);
3563 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3564 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3565 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3566 DRM_MODE_ENCODER_DAC, NULL);
3567 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3568 } else {
3569 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3570 DRM_MODE_ENCODER_TMDS, NULL);
3571 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3572 }
3573 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3574 break;
3575 case ENCODER_OBJECT_ID_SI170B:
3576 case ENCODER_OBJECT_ID_CH7303:
3577 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3578 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3579 case ENCODER_OBJECT_ID_TITFP513:
3580 case ENCODER_OBJECT_ID_VT1623:
3581 case ENCODER_OBJECT_ID_HDMI_SI1930:
3582 case ENCODER_OBJECT_ID_TRAVIS:
3583 case ENCODER_OBJECT_ID_NUTMEG:
3584 /* these are handled by the primary encoders */
3585 amdgpu_encoder->is_ext_encoder = true;
3586 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3587 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3588 DRM_MODE_ENCODER_LVDS, NULL);
3589 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3590 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3591 DRM_MODE_ENCODER_DAC, NULL);
3592 else
3593 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3594 DRM_MODE_ENCODER_TMDS, NULL);
3595 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3596 break;
3597 }
3598}
3599
3600static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3601 .bandwidth_update = &dce_v10_0_bandwidth_update,
3602 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3603 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3604 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3605 .hpd_sense = &dce_v10_0_hpd_sense,
3606 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3607 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3608 .page_flip = &dce_v10_0_page_flip,
3609 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3610 .add_encoder = &dce_v10_0_encoder_add,
3611 .add_connector = &amdgpu_connector_add,
3612};
3613
3614static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3615{
3616 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3617}
3618
3619static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3620 .set = dce_v10_0_set_crtc_irq_state,
3621 .process = dce_v10_0_crtc_irq,
3622};
3623
3624static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3625 .set = dce_v10_0_set_pageflip_irq_state,
3626 .process = dce_v10_0_pageflip_irq,
3627};
3628
3629static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3630 .set = dce_v10_0_set_hpd_irq_state,
3631 .process = dce_v10_0_hpd_irq,
3632};
3633
3634static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3635{
3636 if (adev->mode_info.num_crtc > 0)
3637 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3638 else
3639 adev->crtc_irq.num_types = 0;
3640 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3641
3642 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3643 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3644
3645 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3646 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3647}
3648
3649const struct amdgpu_ip_block_version dce_v10_0_ip_block = {
3650 .type = AMD_IP_BLOCK_TYPE_DCE,
3651 .major = 10,
3652 .minor = 0,
3653 .rev = 0,
3654 .funcs = &dce_v10_0_ip_funcs,
3655};
3656
3657const struct amdgpu_ip_block_version dce_v10_1_ip_block = {
3658 .type = AMD_IP_BLOCK_TYPE_DCE,
3659 .major = 10,
3660 .minor = 1,
3661 .rev = 0,
3662 .funcs = &dce_v10_0_ip_funcs,
3663};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fb_helper.h>
25#include <drm/drm_fourcc.h>
26#include <drm/drm_vblank.h>
27
28#include "amdgpu.h"
29#include "amdgpu_pm.h"
30#include "amdgpu_i2c.h"
31#include "vid.h"
32#include "atom.h"
33#include "amdgpu_atombios.h"
34#include "atombios_crtc.h"
35#include "atombios_encoders.h"
36#include "amdgpu_pll.h"
37#include "amdgpu_connectors.h"
38#include "amdgpu_display.h"
39#include "dce_v10_0.h"
40
41#include "dce/dce_10_0_d.h"
42#include "dce/dce_10_0_sh_mask.h"
43#include "dce/dce_10_0_enum.h"
44#include "oss/oss_3_0_d.h"
45#include "oss/oss_3_0_sh_mask.h"
46#include "gmc/gmc_8_1_d.h"
47#include "gmc/gmc_8_1_sh_mask.h"
48
49#include "ivsrcid/ivsrcid_vislands30.h"
50
51static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev);
52static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev);
53
54static const u32 crtc_offsets[] =
55{
56 CRTC0_REGISTER_OFFSET,
57 CRTC1_REGISTER_OFFSET,
58 CRTC2_REGISTER_OFFSET,
59 CRTC3_REGISTER_OFFSET,
60 CRTC4_REGISTER_OFFSET,
61 CRTC5_REGISTER_OFFSET,
62 CRTC6_REGISTER_OFFSET
63};
64
65static const u32 hpd_offsets[] =
66{
67 HPD0_REGISTER_OFFSET,
68 HPD1_REGISTER_OFFSET,
69 HPD2_REGISTER_OFFSET,
70 HPD3_REGISTER_OFFSET,
71 HPD4_REGISTER_OFFSET,
72 HPD5_REGISTER_OFFSET
73};
74
75static const uint32_t dig_offsets[] = {
76 DIG0_REGISTER_OFFSET,
77 DIG1_REGISTER_OFFSET,
78 DIG2_REGISTER_OFFSET,
79 DIG3_REGISTER_OFFSET,
80 DIG4_REGISTER_OFFSET,
81 DIG5_REGISTER_OFFSET,
82 DIG6_REGISTER_OFFSET
83};
84
85static const struct {
86 uint32_t reg;
87 uint32_t vblank;
88 uint32_t vline;
89 uint32_t hpd;
90
91} interrupt_status_offsets[] = { {
92 .reg = mmDISP_INTERRUPT_STATUS,
93 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
116}, {
117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
119 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
121} };
122
123static const u32 golden_settings_tonga_a11[] =
124{
125 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
127 mmFBC_MISC, 0x1f311fff, 0x12300000,
128 mmHDMI_CONTROL, 0x31000111, 0x00000011,
129};
130
131static const u32 tonga_mgcg_cgcg_init[] =
132{
133 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
134 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
135};
136
137static const u32 golden_settings_fiji_a10[] =
138{
139 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
140 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
141 mmFBC_MISC, 0x1f311fff, 0x12300000,
142 mmHDMI_CONTROL, 0x31000111, 0x00000011,
143};
144
145static const u32 fiji_mgcg_cgcg_init[] =
146{
147 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
148 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
149};
150
151static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
152{
153 switch (adev->asic_type) {
154 case CHIP_FIJI:
155 amdgpu_device_program_register_sequence(adev,
156 fiji_mgcg_cgcg_init,
157 ARRAY_SIZE(fiji_mgcg_cgcg_init));
158 amdgpu_device_program_register_sequence(adev,
159 golden_settings_fiji_a10,
160 ARRAY_SIZE(golden_settings_fiji_a10));
161 break;
162 case CHIP_TONGA:
163 amdgpu_device_program_register_sequence(adev,
164 tonga_mgcg_cgcg_init,
165 ARRAY_SIZE(tonga_mgcg_cgcg_init));
166 amdgpu_device_program_register_sequence(adev,
167 golden_settings_tonga_a11,
168 ARRAY_SIZE(golden_settings_tonga_a11));
169 break;
170 default:
171 break;
172 }
173}
174
175static u32 dce_v10_0_audio_endpt_rreg(struct amdgpu_device *adev,
176 u32 block_offset, u32 reg)
177{
178 unsigned long flags;
179 u32 r;
180
181 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
182 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
183 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
184 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
185
186 return r;
187}
188
189static void dce_v10_0_audio_endpt_wreg(struct amdgpu_device *adev,
190 u32 block_offset, u32 reg, u32 v)
191{
192 unsigned long flags;
193
194 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
195 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
196 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
197 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
198}
199
200static u32 dce_v10_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
201{
202 if (crtc >= adev->mode_info.num_crtc)
203 return 0;
204 else
205 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
206}
207
208static void dce_v10_0_pageflip_interrupt_init(struct amdgpu_device *adev)
209{
210 unsigned i;
211
212 /* Enable pflip interrupts */
213 for (i = 0; i < adev->mode_info.num_crtc; i++)
214 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
215}
216
217static void dce_v10_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
218{
219 unsigned i;
220
221 /* Disable pflip interrupts */
222 for (i = 0; i < adev->mode_info.num_crtc; i++)
223 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
224}
225
226/**
227 * dce_v10_0_page_flip - pageflip callback.
228 *
229 * @adev: amdgpu_device pointer
230 * @crtc_id: crtc to cleanup pageflip on
231 * @crtc_base: new address of the crtc (GPU MC address)
232 * @async: asynchronous flip
233 *
234 * Triggers the actual pageflip by updating the primary
235 * surface base address.
236 */
237static void dce_v10_0_page_flip(struct amdgpu_device *adev,
238 int crtc_id, u64 crtc_base, bool async)
239{
240 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
241 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
242 u32 tmp;
243
244 /* flip at hsync for async, default is vsync */
245 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
246 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
247 GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0);
248 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
249 /* update pitch */
250 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
251 fb->pitches[0] / fb->format->cpp[0]);
252 /* update the primary scanout address */
253 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
254 upper_32_bits(crtc_base));
255 /* writing to the low address triggers the update */
256 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
257 lower_32_bits(crtc_base));
258 /* post the write */
259 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
260}
261
262static int dce_v10_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
263 u32 *vbl, u32 *position)
264{
265 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
266 return -EINVAL;
267
268 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
269 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
270
271 return 0;
272}
273
274/**
275 * dce_v10_0_hpd_sense - hpd sense callback.
276 *
277 * @adev: amdgpu_device pointer
278 * @hpd: hpd (hotplug detect) pin
279 *
280 * Checks if a digital monitor is connected (evergreen+).
281 * Returns true if connected, false if not connected.
282 */
283static bool dce_v10_0_hpd_sense(struct amdgpu_device *adev,
284 enum amdgpu_hpd_id hpd)
285{
286 bool connected = false;
287
288 if (hpd >= adev->mode_info.num_hpd)
289 return connected;
290
291 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
292 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
293 connected = true;
294
295 return connected;
296}
297
298/**
299 * dce_v10_0_hpd_set_polarity - hpd set polarity callback.
300 *
301 * @adev: amdgpu_device pointer
302 * @hpd: hpd (hotplug detect) pin
303 *
304 * Set the polarity of the hpd pin (evergreen+).
305 */
306static void dce_v10_0_hpd_set_polarity(struct amdgpu_device *adev,
307 enum amdgpu_hpd_id hpd)
308{
309 u32 tmp;
310 bool connected = dce_v10_0_hpd_sense(adev, hpd);
311
312 if (hpd >= adev->mode_info.num_hpd)
313 return;
314
315 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
316 if (connected)
317 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
318 else
319 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
320 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
321}
322
323/**
324 * dce_v10_0_hpd_init - hpd setup callback.
325 *
326 * @adev: amdgpu_device pointer
327 *
328 * Setup the hpd pins used by the card (evergreen+).
329 * Enable the pin, set the polarity, and enable the hpd interrupts.
330 */
331static void dce_v10_0_hpd_init(struct amdgpu_device *adev)
332{
333 struct drm_device *dev = adev_to_drm(adev);
334 struct drm_connector *connector;
335 struct drm_connector_list_iter iter;
336 u32 tmp;
337
338 drm_connector_list_iter_begin(dev, &iter);
339 drm_for_each_connector_iter(connector, &iter) {
340 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
341
342 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
343 continue;
344
345 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
346 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
347 /* don't try to enable hpd on eDP or LVDS avoid breaking the
348 * aux dp channel on imac and help (but not completely fix)
349 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
350 * also avoid interrupt storms during dpms.
351 */
352 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
353 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
354 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
355 continue;
356 }
357
358 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
359 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
360 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
361
362 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
363 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
364 DC_HPD_CONNECT_INT_DELAY,
365 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
366 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
367 DC_HPD_DISCONNECT_INT_DELAY,
368 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
369 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
370
371 dce_v10_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
372 amdgpu_irq_get(adev, &adev->hpd_irq,
373 amdgpu_connector->hpd.hpd);
374 }
375 drm_connector_list_iter_end(&iter);
376}
377
378/**
379 * dce_v10_0_hpd_fini - hpd tear down callback.
380 *
381 * @adev: amdgpu_device pointer
382 *
383 * Tear down the hpd pins used by the card (evergreen+).
384 * Disable the hpd interrupts.
385 */
386static void dce_v10_0_hpd_fini(struct amdgpu_device *adev)
387{
388 struct drm_device *dev = adev_to_drm(adev);
389 struct drm_connector *connector;
390 struct drm_connector_list_iter iter;
391 u32 tmp;
392
393 drm_connector_list_iter_begin(dev, &iter);
394 drm_for_each_connector_iter(connector, &iter) {
395 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
396
397 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
398 continue;
399
400 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
401 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
402 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
403
404 amdgpu_irq_put(adev, &adev->hpd_irq,
405 amdgpu_connector->hpd.hpd);
406 }
407 drm_connector_list_iter_end(&iter);
408}
409
410static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
411{
412 return mmDC_GPIO_HPD_A;
413}
414
415static bool dce_v10_0_is_display_hung(struct amdgpu_device *adev)
416{
417 u32 crtc_hung = 0;
418 u32 crtc_status[6];
419 u32 i, j, tmp;
420
421 for (i = 0; i < adev->mode_info.num_crtc; i++) {
422 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
423 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
424 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
425 crtc_hung |= (1 << i);
426 }
427 }
428
429 for (j = 0; j < 10; j++) {
430 for (i = 0; i < adev->mode_info.num_crtc; i++) {
431 if (crtc_hung & (1 << i)) {
432 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
433 if (tmp != crtc_status[i])
434 crtc_hung &= ~(1 << i);
435 }
436 }
437 if (crtc_hung == 0)
438 return false;
439 udelay(100);
440 }
441
442 return true;
443}
444
445static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
446 bool render)
447{
448 u32 tmp;
449
450 /* Lockout access through VGA aperture*/
451 tmp = RREG32(mmVGA_HDP_CONTROL);
452 if (render)
453 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
454 else
455 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
456 WREG32(mmVGA_HDP_CONTROL, tmp);
457
458 /* disable VGA render */
459 tmp = RREG32(mmVGA_RENDER_CONTROL);
460 if (render)
461 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
462 else
463 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
464 WREG32(mmVGA_RENDER_CONTROL, tmp);
465}
466
467static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
468{
469 int num_crtc = 0;
470
471 switch (adev->asic_type) {
472 case CHIP_FIJI:
473 case CHIP_TONGA:
474 num_crtc = 6;
475 break;
476 default:
477 num_crtc = 0;
478 }
479 return num_crtc;
480}
481
482void dce_v10_0_disable_dce(struct amdgpu_device *adev)
483{
484 /*Disable VGA render and enabled crtc, if has DCE engine*/
485 if (amdgpu_atombios_has_dce_engine_info(adev)) {
486 u32 tmp;
487 int crtc_enabled, i;
488
489 dce_v10_0_set_vga_render_state(adev, false);
490
491 /*Disable crtc*/
492 for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
493 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
494 CRTC_CONTROL, CRTC_MASTER_EN);
495 if (crtc_enabled) {
496 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
497 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
498 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
499 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
500 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
501 }
502 }
503 }
504}
505
506static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
507{
508 struct drm_device *dev = encoder->dev;
509 struct amdgpu_device *adev = drm_to_adev(dev);
510 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
511 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
512 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
513 int bpc = 0;
514 u32 tmp = 0;
515 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
516
517 if (connector) {
518 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
519 bpc = amdgpu_connector_get_monitor_bpc(connector);
520 dither = amdgpu_connector->dither;
521 }
522
523 /* LVDS/eDP FMT is set up by atom */
524 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
525 return;
526
527 /* not needed for analog */
528 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
529 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
530 return;
531
532 if (bpc == 0)
533 return;
534
535 switch (bpc) {
536 case 6:
537 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
538 /* XXX sort out optimal dither settings */
539 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
540 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
541 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
542 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
543 } else {
544 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
546 }
547 break;
548 case 8:
549 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
550 /* XXX sort out optimal dither settings */
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
552 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
553 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
554 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
555 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
556 } else {
557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
559 }
560 break;
561 case 10:
562 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
563 /* XXX sort out optimal dither settings */
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
567 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
569 } else {
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
572 }
573 break;
574 default:
575 /* not needed */
576 break;
577 }
578
579 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
580}
581
582
583/* display watermark setup */
584/**
585 * dce_v10_0_line_buffer_adjust - Set up the line buffer
586 *
587 * @adev: amdgpu_device pointer
588 * @amdgpu_crtc: the selected display controller
589 * @mode: the current display mode on the selected display
590 * controller
591 *
592 * Setup up the line buffer allocation for
593 * the selected display controller (CIK).
594 * Returns the line buffer size in pixels.
595 */
596static u32 dce_v10_0_line_buffer_adjust(struct amdgpu_device *adev,
597 struct amdgpu_crtc *amdgpu_crtc,
598 struct drm_display_mode *mode)
599{
600 u32 tmp, buffer_alloc, i, mem_cfg;
601 u32 pipe_offset = amdgpu_crtc->crtc_id;
602 /*
603 * Line Buffer Setup
604 * There are 6 line buffers, one for each display controllers.
605 * There are 3 partitions per LB. Select the number of partitions
606 * to enable based on the display width. For display widths larger
607 * than 4096, you need use to use 2 display controllers and combine
608 * them using the stereo blender.
609 */
610 if (amdgpu_crtc->base.enabled && mode) {
611 if (mode->crtc_hdisplay < 1920) {
612 mem_cfg = 1;
613 buffer_alloc = 2;
614 } else if (mode->crtc_hdisplay < 2560) {
615 mem_cfg = 2;
616 buffer_alloc = 2;
617 } else if (mode->crtc_hdisplay < 4096) {
618 mem_cfg = 0;
619 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
620 } else {
621 DRM_DEBUG_KMS("Mode too big for LB!\n");
622 mem_cfg = 0;
623 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
624 }
625 } else {
626 mem_cfg = 1;
627 buffer_alloc = 0;
628 }
629
630 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
631 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
632 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
633
634 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
635 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
636 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
637
638 for (i = 0; i < adev->usec_timeout; i++) {
639 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
640 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
641 break;
642 udelay(1);
643 }
644
645 if (amdgpu_crtc->base.enabled && mode) {
646 switch (mem_cfg) {
647 case 0:
648 default:
649 return 4096 * 2;
650 case 1:
651 return 1920 * 2;
652 case 2:
653 return 2560 * 2;
654 }
655 }
656
657 /* controller not enabled, so no lb used */
658 return 0;
659}
660
661/**
662 * cik_get_number_of_dram_channels - get the number of dram channels
663 *
664 * @adev: amdgpu_device pointer
665 *
666 * Look up the number of video ram channels (CIK).
667 * Used for display watermark bandwidth calculations
668 * Returns the number of dram channels
669 */
670static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
671{
672 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
673
674 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
675 case 0:
676 default:
677 return 1;
678 case 1:
679 return 2;
680 case 2:
681 return 4;
682 case 3:
683 return 8;
684 case 4:
685 return 3;
686 case 5:
687 return 6;
688 case 6:
689 return 10;
690 case 7:
691 return 12;
692 case 8:
693 return 16;
694 }
695}
696
697struct dce10_wm_params {
698 u32 dram_channels; /* number of dram channels */
699 u32 yclk; /* bandwidth per dram data pin in kHz */
700 u32 sclk; /* engine clock in kHz */
701 u32 disp_clk; /* display clock in kHz */
702 u32 src_width; /* viewport width */
703 u32 active_time; /* active display time in ns */
704 u32 blank_time; /* blank time in ns */
705 bool interlaced; /* mode is interlaced */
706 fixed20_12 vsc; /* vertical scale ratio */
707 u32 num_heads; /* number of active crtcs */
708 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
709 u32 lb_size; /* line buffer allocated to pipe */
710 u32 vtaps; /* vertical scaler taps */
711};
712
713/**
714 * dce_v10_0_dram_bandwidth - get the dram bandwidth
715 *
716 * @wm: watermark calculation data
717 *
718 * Calculate the raw dram bandwidth (CIK).
719 * Used for display watermark bandwidth calculations
720 * Returns the dram bandwidth in MBytes/s
721 */
722static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm)
723{
724 /* Calculate raw DRAM Bandwidth */
725 fixed20_12 dram_efficiency; /* 0.7 */
726 fixed20_12 yclk, dram_channels, bandwidth;
727 fixed20_12 a;
728
729 a.full = dfixed_const(1000);
730 yclk.full = dfixed_const(wm->yclk);
731 yclk.full = dfixed_div(yclk, a);
732 dram_channels.full = dfixed_const(wm->dram_channels * 4);
733 a.full = dfixed_const(10);
734 dram_efficiency.full = dfixed_const(7);
735 dram_efficiency.full = dfixed_div(dram_efficiency, a);
736 bandwidth.full = dfixed_mul(dram_channels, yclk);
737 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
738
739 return dfixed_trunc(bandwidth);
740}
741
742/**
743 * dce_v10_0_dram_bandwidth_for_display - get the dram bandwidth for display
744 *
745 * @wm: watermark calculation data
746 *
747 * Calculate the dram bandwidth used for display (CIK).
748 * Used for display watermark bandwidth calculations
749 * Returns the dram bandwidth for display in MBytes/s
750 */
751static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
752{
753 /* Calculate DRAM Bandwidth and the part allocated to display. */
754 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
755 fixed20_12 yclk, dram_channels, bandwidth;
756 fixed20_12 a;
757
758 a.full = dfixed_const(1000);
759 yclk.full = dfixed_const(wm->yclk);
760 yclk.full = dfixed_div(yclk, a);
761 dram_channels.full = dfixed_const(wm->dram_channels * 4);
762 a.full = dfixed_const(10);
763 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
764 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
765 bandwidth.full = dfixed_mul(dram_channels, yclk);
766 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
767
768 return dfixed_trunc(bandwidth);
769}
770
771/**
772 * dce_v10_0_data_return_bandwidth - get the data return bandwidth
773 *
774 * @wm: watermark calculation data
775 *
776 * Calculate the data return bandwidth used for display (CIK).
777 * Used for display watermark bandwidth calculations
778 * Returns the data return bandwidth in MBytes/s
779 */
780static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm)
781{
782 /* Calculate the display Data return Bandwidth */
783 fixed20_12 return_efficiency; /* 0.8 */
784 fixed20_12 sclk, bandwidth;
785 fixed20_12 a;
786
787 a.full = dfixed_const(1000);
788 sclk.full = dfixed_const(wm->sclk);
789 sclk.full = dfixed_div(sclk, a);
790 a.full = dfixed_const(10);
791 return_efficiency.full = dfixed_const(8);
792 return_efficiency.full = dfixed_div(return_efficiency, a);
793 a.full = dfixed_const(32);
794 bandwidth.full = dfixed_mul(a, sclk);
795 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
796
797 return dfixed_trunc(bandwidth);
798}
799
800/**
801 * dce_v10_0_dmif_request_bandwidth - get the dmif bandwidth
802 *
803 * @wm: watermark calculation data
804 *
805 * Calculate the dmif bandwidth used for display (CIK).
806 * Used for display watermark bandwidth calculations
807 * Returns the dmif bandwidth in MBytes/s
808 */
809static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
810{
811 /* Calculate the DMIF Request Bandwidth */
812 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
813 fixed20_12 disp_clk, bandwidth;
814 fixed20_12 a, b;
815
816 a.full = dfixed_const(1000);
817 disp_clk.full = dfixed_const(wm->disp_clk);
818 disp_clk.full = dfixed_div(disp_clk, a);
819 a.full = dfixed_const(32);
820 b.full = dfixed_mul(a, disp_clk);
821
822 a.full = dfixed_const(10);
823 disp_clk_request_efficiency.full = dfixed_const(8);
824 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
825
826 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
827
828 return dfixed_trunc(bandwidth);
829}
830
831/**
832 * dce_v10_0_available_bandwidth - get the min available bandwidth
833 *
834 * @wm: watermark calculation data
835 *
836 * Calculate the min available bandwidth used for display (CIK).
837 * Used for display watermark bandwidth calculations
838 * Returns the min available bandwidth in MBytes/s
839 */
840static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm)
841{
842 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
843 u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm);
844 u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm);
845 u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm);
846
847 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
848}
849
850/**
851 * dce_v10_0_average_bandwidth - get the average available bandwidth
852 *
853 * @wm: watermark calculation data
854 *
855 * Calculate the average available bandwidth used for display (CIK).
856 * Used for display watermark bandwidth calculations
857 * Returns the average available bandwidth in MBytes/s
858 */
859static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm)
860{
861 /* Calculate the display mode Average Bandwidth
862 * DisplayMode should contain the source and destination dimensions,
863 * timing, etc.
864 */
865 fixed20_12 bpp;
866 fixed20_12 line_time;
867 fixed20_12 src_width;
868 fixed20_12 bandwidth;
869 fixed20_12 a;
870
871 a.full = dfixed_const(1000);
872 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
873 line_time.full = dfixed_div(line_time, a);
874 bpp.full = dfixed_const(wm->bytes_per_pixel);
875 src_width.full = dfixed_const(wm->src_width);
876 bandwidth.full = dfixed_mul(src_width, bpp);
877 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
878 bandwidth.full = dfixed_div(bandwidth, line_time);
879
880 return dfixed_trunc(bandwidth);
881}
882
883/**
884 * dce_v10_0_latency_watermark - get the latency watermark
885 *
886 * @wm: watermark calculation data
887 *
888 * Calculate the latency watermark (CIK).
889 * Used for display watermark bandwidth calculations
890 * Returns the latency watermark in ns
891 */
892static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm)
893{
894 /* First calculate the latency in ns */
895 u32 mc_latency = 2000; /* 2000 ns. */
896 u32 available_bandwidth = dce_v10_0_available_bandwidth(wm);
897 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
898 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
899 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
900 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
901 (wm->num_heads * cursor_line_pair_return_time);
902 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
903 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
904 u32 tmp, dmif_size = 12288;
905 fixed20_12 a, b, c;
906
907 if (wm->num_heads == 0)
908 return 0;
909
910 a.full = dfixed_const(2);
911 b.full = dfixed_const(1);
912 if ((wm->vsc.full > a.full) ||
913 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
914 (wm->vtaps >= 5) ||
915 ((wm->vsc.full >= a.full) && wm->interlaced))
916 max_src_lines_per_dst_line = 4;
917 else
918 max_src_lines_per_dst_line = 2;
919
920 a.full = dfixed_const(available_bandwidth);
921 b.full = dfixed_const(wm->num_heads);
922 a.full = dfixed_div(a, b);
923 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
924 tmp = min(dfixed_trunc(a), tmp);
925
926 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
927
928 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
929 b.full = dfixed_const(1000);
930 c.full = dfixed_const(lb_fill_bw);
931 b.full = dfixed_div(c, b);
932 a.full = dfixed_div(a, b);
933 line_fill_time = dfixed_trunc(a);
934
935 if (line_fill_time < wm->active_time)
936 return latency;
937 else
938 return latency + (line_fill_time - wm->active_time);
939
940}
941
942/**
943 * dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display - check
944 * average and available dram bandwidth
945 *
946 * @wm: watermark calculation data
947 *
948 * Check if the display average bandwidth fits in the display
949 * dram bandwidth (CIK).
950 * Used for display watermark bandwidth calculations
951 * Returns true if the display fits, false if not.
952 */
953static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
954{
955 if (dce_v10_0_average_bandwidth(wm) <=
956 (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads))
957 return true;
958 else
959 return false;
960}
961
962/**
963 * dce_v10_0_average_bandwidth_vs_available_bandwidth - check
964 * average and available bandwidth
965 *
966 * @wm: watermark calculation data
967 *
968 * Check if the display average bandwidth fits in the display
969 * available bandwidth (CIK).
970 * Used for display watermark bandwidth calculations
971 * Returns true if the display fits, false if not.
972 */
973static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
974{
975 if (dce_v10_0_average_bandwidth(wm) <=
976 (dce_v10_0_available_bandwidth(wm) / wm->num_heads))
977 return true;
978 else
979 return false;
980}
981
982/**
983 * dce_v10_0_check_latency_hiding - check latency hiding
984 *
985 * @wm: watermark calculation data
986 *
987 * Check latency hiding (CIK).
988 * Used for display watermark bandwidth calculations
989 * Returns true if the display fits, false if not.
990 */
991static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm)
992{
993 u32 lb_partitions = wm->lb_size / wm->src_width;
994 u32 line_time = wm->active_time + wm->blank_time;
995 u32 latency_tolerant_lines;
996 u32 latency_hiding;
997 fixed20_12 a;
998
999 a.full = dfixed_const(1);
1000 if (wm->vsc.full > a.full)
1001 latency_tolerant_lines = 1;
1002 else {
1003 if (lb_partitions <= (wm->vtaps + 1))
1004 latency_tolerant_lines = 1;
1005 else
1006 latency_tolerant_lines = 2;
1007 }
1008
1009 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1010
1011 if (dce_v10_0_latency_watermark(wm) <= latency_hiding)
1012 return true;
1013 else
1014 return false;
1015}
1016
1017/**
1018 * dce_v10_0_program_watermarks - program display watermarks
1019 *
1020 * @adev: amdgpu_device pointer
1021 * @amdgpu_crtc: the selected display controller
1022 * @lb_size: line buffer size
1023 * @num_heads: number of display controllers in use
1024 *
1025 * Calculate and program the display watermarks for the
1026 * selected display controller (CIK).
1027 */
1028static void dce_v10_0_program_watermarks(struct amdgpu_device *adev,
1029 struct amdgpu_crtc *amdgpu_crtc,
1030 u32 lb_size, u32 num_heads)
1031{
1032 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1033 struct dce10_wm_params wm_low, wm_high;
1034 u32 active_time;
1035 u32 line_time = 0;
1036 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1037 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1038
1039 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1040 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1041 (u32)mode->clock);
1042 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1043 (u32)mode->clock);
1044 line_time = min(line_time, (u32)65535);
1045
1046 /* watermark for high clocks */
1047 if (adev->pm.dpm_enabled) {
1048 wm_high.yclk =
1049 amdgpu_dpm_get_mclk(adev, false) * 10;
1050 wm_high.sclk =
1051 amdgpu_dpm_get_sclk(adev, false) * 10;
1052 } else {
1053 wm_high.yclk = adev->pm.current_mclk * 10;
1054 wm_high.sclk = adev->pm.current_sclk * 10;
1055 }
1056
1057 wm_high.disp_clk = mode->clock;
1058 wm_high.src_width = mode->crtc_hdisplay;
1059 wm_high.active_time = active_time;
1060 wm_high.blank_time = line_time - wm_high.active_time;
1061 wm_high.interlaced = false;
1062 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1063 wm_high.interlaced = true;
1064 wm_high.vsc = amdgpu_crtc->vsc;
1065 wm_high.vtaps = 1;
1066 if (amdgpu_crtc->rmx_type != RMX_OFF)
1067 wm_high.vtaps = 2;
1068 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1069 wm_high.lb_size = lb_size;
1070 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1071 wm_high.num_heads = num_heads;
1072
1073 /* set for high clocks */
1074 latency_watermark_a = min(dce_v10_0_latency_watermark(&wm_high), (u32)65535);
1075
1076 /* possibly force display priority to high */
1077 /* should really do this at mode validation time... */
1078 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1079 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1080 !dce_v10_0_check_latency_hiding(&wm_high) ||
1081 (adev->mode_info.disp_priority == 2)) {
1082 DRM_DEBUG_KMS("force priority to high\n");
1083 }
1084
1085 /* watermark for low clocks */
1086 if (adev->pm.dpm_enabled) {
1087 wm_low.yclk =
1088 amdgpu_dpm_get_mclk(adev, true) * 10;
1089 wm_low.sclk =
1090 amdgpu_dpm_get_sclk(adev, true) * 10;
1091 } else {
1092 wm_low.yclk = adev->pm.current_mclk * 10;
1093 wm_low.sclk = adev->pm.current_sclk * 10;
1094 }
1095
1096 wm_low.disp_clk = mode->clock;
1097 wm_low.src_width = mode->crtc_hdisplay;
1098 wm_low.active_time = active_time;
1099 wm_low.blank_time = line_time - wm_low.active_time;
1100 wm_low.interlaced = false;
1101 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1102 wm_low.interlaced = true;
1103 wm_low.vsc = amdgpu_crtc->vsc;
1104 wm_low.vtaps = 1;
1105 if (amdgpu_crtc->rmx_type != RMX_OFF)
1106 wm_low.vtaps = 2;
1107 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1108 wm_low.lb_size = lb_size;
1109 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1110 wm_low.num_heads = num_heads;
1111
1112 /* set for low clocks */
1113 latency_watermark_b = min(dce_v10_0_latency_watermark(&wm_low), (u32)65535);
1114
1115 /* possibly force display priority to high */
1116 /* should really do this at mode validation time... */
1117 if (!dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1118 !dce_v10_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1119 !dce_v10_0_check_latency_hiding(&wm_low) ||
1120 (adev->mode_info.disp_priority == 2)) {
1121 DRM_DEBUG_KMS("force priority to high\n");
1122 }
1123 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1124 }
1125
1126 /* select wm A */
1127 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1128 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1129 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1130 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1131 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1132 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1133 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1134 /* select wm B */
1135 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1136 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1137 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1138 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1139 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1140 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1141 /* restore original selection */
1142 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1143
1144 /* save values for DPM */
1145 amdgpu_crtc->line_time = line_time;
1146 amdgpu_crtc->wm_high = latency_watermark_a;
1147 amdgpu_crtc->wm_low = latency_watermark_b;
1148 /* Save number of lines the linebuffer leads before the scanout */
1149 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1150}
1151
1152/**
1153 * dce_v10_0_bandwidth_update - program display watermarks
1154 *
1155 * @adev: amdgpu_device pointer
1156 *
1157 * Calculate and program the display watermarks and line
1158 * buffer allocation (CIK).
1159 */
1160static void dce_v10_0_bandwidth_update(struct amdgpu_device *adev)
1161{
1162 struct drm_display_mode *mode = NULL;
1163 u32 num_heads = 0, lb_size;
1164 int i;
1165
1166 amdgpu_display_update_priority(adev);
1167
1168 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1169 if (adev->mode_info.crtcs[i]->base.enabled)
1170 num_heads++;
1171 }
1172 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1173 mode = &adev->mode_info.crtcs[i]->base.mode;
1174 lb_size = dce_v10_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1175 dce_v10_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1176 lb_size, num_heads);
1177 }
1178}
1179
1180static void dce_v10_0_audio_get_connected_pins(struct amdgpu_device *adev)
1181{
1182 int i;
1183 u32 offset, tmp;
1184
1185 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1186 offset = adev->mode_info.audio.pin[i].offset;
1187 tmp = RREG32_AUDIO_ENDPT(offset,
1188 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1189 if (((tmp &
1190 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1191 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1192 adev->mode_info.audio.pin[i].connected = false;
1193 else
1194 adev->mode_info.audio.pin[i].connected = true;
1195 }
1196}
1197
1198static struct amdgpu_audio_pin *dce_v10_0_audio_get_pin(struct amdgpu_device *adev)
1199{
1200 int i;
1201
1202 dce_v10_0_audio_get_connected_pins(adev);
1203
1204 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1205 if (adev->mode_info.audio.pin[i].connected)
1206 return &adev->mode_info.audio.pin[i];
1207 }
1208 DRM_ERROR("No connected audio pins found!\n");
1209 return NULL;
1210}
1211
1212static void dce_v10_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1213{
1214 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1215 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1216 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1217 u32 tmp;
1218
1219 if (!dig || !dig->afmt || !dig->afmt->pin)
1220 return;
1221
1222 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1223 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1224 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1225}
1226
1227static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder,
1228 struct drm_display_mode *mode)
1229{
1230 struct drm_device *dev = encoder->dev;
1231 struct amdgpu_device *adev = drm_to_adev(dev);
1232 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1233 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1234 struct drm_connector *connector;
1235 struct drm_connector_list_iter iter;
1236 struct amdgpu_connector *amdgpu_connector = NULL;
1237 u32 tmp;
1238 int interlace = 0;
1239
1240 if (!dig || !dig->afmt || !dig->afmt->pin)
1241 return;
1242
1243 drm_connector_list_iter_begin(dev, &iter);
1244 drm_for_each_connector_iter(connector, &iter) {
1245 if (connector->encoder == encoder) {
1246 amdgpu_connector = to_amdgpu_connector(connector);
1247 break;
1248 }
1249 }
1250 drm_connector_list_iter_end(&iter);
1251
1252 if (!amdgpu_connector) {
1253 DRM_ERROR("Couldn't find encoder's connector\n");
1254 return;
1255 }
1256
1257 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1258 interlace = 1;
1259 if (connector->latency_present[interlace]) {
1260 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1261 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1262 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1264 } else {
1265 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1266 VIDEO_LIPSYNC, 0);
1267 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1268 AUDIO_LIPSYNC, 0);
1269 }
1270 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1271 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1272}
1273
1274static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1275{
1276 struct drm_device *dev = encoder->dev;
1277 struct amdgpu_device *adev = drm_to_adev(dev);
1278 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1279 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1280 struct drm_connector *connector;
1281 struct drm_connector_list_iter iter;
1282 struct amdgpu_connector *amdgpu_connector = NULL;
1283 u32 tmp;
1284 u8 *sadb = NULL;
1285 int sad_count;
1286
1287 if (!dig || !dig->afmt || !dig->afmt->pin)
1288 return;
1289
1290 drm_connector_list_iter_begin(dev, &iter);
1291 drm_for_each_connector_iter(connector, &iter) {
1292 if (connector->encoder == encoder) {
1293 amdgpu_connector = to_amdgpu_connector(connector);
1294 break;
1295 }
1296 }
1297 drm_connector_list_iter_end(&iter);
1298
1299 if (!amdgpu_connector) {
1300 DRM_ERROR("Couldn't find encoder's connector\n");
1301 return;
1302 }
1303
1304 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1305 if (sad_count < 0) {
1306 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1307 sad_count = 0;
1308 }
1309
1310 /* program the speaker allocation */
1311 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1312 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1313 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1314 DP_CONNECTION, 0);
1315 /* set HDMI mode */
1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1317 HDMI_CONNECTION, 1);
1318 if (sad_count)
1319 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1320 SPEAKER_ALLOCATION, sadb[0]);
1321 else
1322 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1323 SPEAKER_ALLOCATION, 5); /* stereo */
1324 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1325 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1326
1327 kfree(sadb);
1328}
1329
1330static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder)
1331{
1332 struct drm_device *dev = encoder->dev;
1333 struct amdgpu_device *adev = drm_to_adev(dev);
1334 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1335 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1336 struct drm_connector *connector;
1337 struct drm_connector_list_iter iter;
1338 struct amdgpu_connector *amdgpu_connector = NULL;
1339 struct cea_sad *sads;
1340 int i, sad_count;
1341
1342 static const u16 eld_reg_to_type[][2] = {
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1351 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1352 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1353 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1354 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1355 };
1356
1357 if (!dig || !dig->afmt || !dig->afmt->pin)
1358 return;
1359
1360 drm_connector_list_iter_begin(dev, &iter);
1361 drm_for_each_connector_iter(connector, &iter) {
1362 if (connector->encoder == encoder) {
1363 amdgpu_connector = to_amdgpu_connector(connector);
1364 break;
1365 }
1366 }
1367 drm_connector_list_iter_end(&iter);
1368
1369 if (!amdgpu_connector) {
1370 DRM_ERROR("Couldn't find encoder's connector\n");
1371 return;
1372 }
1373
1374 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1375 if (sad_count < 0)
1376 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1377 if (sad_count <= 0)
1378 return;
1379 BUG_ON(!sads);
1380
1381 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1382 u32 tmp = 0;
1383 u8 stereo_freqs = 0;
1384 int max_channels = -1;
1385 int j;
1386
1387 for (j = 0; j < sad_count; j++) {
1388 struct cea_sad *sad = &sads[j];
1389
1390 if (sad->format == eld_reg_to_type[i][1]) {
1391 if (sad->channels > max_channels) {
1392 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1393 MAX_CHANNELS, sad->channels);
1394 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1395 DESCRIPTOR_BYTE_2, sad->byte2);
1396 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1397 SUPPORTED_FREQUENCIES, sad->freq);
1398 max_channels = sad->channels;
1399 }
1400
1401 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1402 stereo_freqs |= sad->freq;
1403 else
1404 break;
1405 }
1406 }
1407
1408 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1409 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1410 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1411 }
1412
1413 kfree(sads);
1414}
1415
1416static void dce_v10_0_audio_enable(struct amdgpu_device *adev,
1417 struct amdgpu_audio_pin *pin,
1418 bool enable)
1419{
1420 if (!pin)
1421 return;
1422
1423 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1424 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1425}
1426
1427static const u32 pin_offsets[] =
1428{
1429 AUD0_REGISTER_OFFSET,
1430 AUD1_REGISTER_OFFSET,
1431 AUD2_REGISTER_OFFSET,
1432 AUD3_REGISTER_OFFSET,
1433 AUD4_REGISTER_OFFSET,
1434 AUD5_REGISTER_OFFSET,
1435 AUD6_REGISTER_OFFSET,
1436};
1437
1438static int dce_v10_0_audio_init(struct amdgpu_device *adev)
1439{
1440 int i;
1441
1442 if (!amdgpu_audio)
1443 return 0;
1444
1445 adev->mode_info.audio.enabled = true;
1446
1447 adev->mode_info.audio.num_pins = 7;
1448
1449 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1450 adev->mode_info.audio.pin[i].channels = -1;
1451 adev->mode_info.audio.pin[i].rate = -1;
1452 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1453 adev->mode_info.audio.pin[i].status_bits = 0;
1454 adev->mode_info.audio.pin[i].category_code = 0;
1455 adev->mode_info.audio.pin[i].connected = false;
1456 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1457 adev->mode_info.audio.pin[i].id = i;
1458 /* disable audio. it will be set up later */
1459 /* XXX remove once we switch to ip funcs */
1460 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1461 }
1462
1463 return 0;
1464}
1465
1466static void dce_v10_0_audio_fini(struct amdgpu_device *adev)
1467{
1468 int i;
1469
1470 if (!amdgpu_audio)
1471 return;
1472
1473 if (!adev->mode_info.audio.enabled)
1474 return;
1475
1476 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1477 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1478
1479 adev->mode_info.audio.enabled = false;
1480}
1481
1482/*
1483 * update the N and CTS parameters for a given pixel clock rate
1484 */
1485static void dce_v10_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1486{
1487 struct drm_device *dev = encoder->dev;
1488 struct amdgpu_device *adev = drm_to_adev(dev);
1489 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1490 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1491 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1492 u32 tmp;
1493
1494 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1495 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1496 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1497 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1498 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1499 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1500
1501 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1502 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1503 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1504 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1505 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1506 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1507
1508 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1509 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1510 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1511 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1512 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1513 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1514
1515}
1516
1517/*
1518 * build a HDMI Video Info Frame
1519 */
1520static void dce_v10_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1521 void *buffer, size_t size)
1522{
1523 struct drm_device *dev = encoder->dev;
1524 struct amdgpu_device *adev = drm_to_adev(dev);
1525 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1526 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1527 uint8_t *frame = buffer + 3;
1528 uint8_t *header = buffer;
1529
1530 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1531 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1532 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1533 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1534 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1535 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1536 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1537 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1538}
1539
1540static void dce_v10_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1541{
1542 struct drm_device *dev = encoder->dev;
1543 struct amdgpu_device *adev = drm_to_adev(dev);
1544 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1545 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1546 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1547 u32 dto_phase = 24 * 1000;
1548 u32 dto_modulo = clock;
1549 u32 tmp;
1550
1551 if (!dig || !dig->afmt)
1552 return;
1553
1554 /* XXX two dtos; generally use dto0 for hdmi */
1555 /* Express [24MHz / target pixel clock] as an exact rational
1556 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1557 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1558 */
1559 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1560 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1561 amdgpu_crtc->crtc_id);
1562 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1563 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1564 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1565}
1566
1567/*
1568 * update the info frames with the data from the current display mode
1569 */
1570static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder,
1571 struct drm_display_mode *mode)
1572{
1573 struct drm_device *dev = encoder->dev;
1574 struct amdgpu_device *adev = drm_to_adev(dev);
1575 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1576 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1577 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1578 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1579 struct hdmi_avi_infoframe frame;
1580 ssize_t err;
1581 u32 tmp;
1582 int bpc = 8;
1583
1584 if (!dig || !dig->afmt)
1585 return;
1586
1587 /* Silent, r600_hdmi_enable will raise WARN for us */
1588 if (!dig->afmt->enabled)
1589 return;
1590
1591 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1592 if (encoder->crtc) {
1593 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1594 bpc = amdgpu_crtc->bpc;
1595 }
1596
1597 /* disable audio prior to setting up hw */
1598 dig->afmt->pin = dce_v10_0_audio_get_pin(adev);
1599 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1600
1601 dce_v10_0_audio_set_dto(encoder, mode->clock);
1602
1603 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1604 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1605 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1606
1607 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1608
1609 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1610 switch (bpc) {
1611 case 0:
1612 case 6:
1613 case 8:
1614 case 16:
1615 default:
1616 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1617 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1618 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1619 connector->name, bpc);
1620 break;
1621 case 10:
1622 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1623 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1624 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1625 connector->name);
1626 break;
1627 case 12:
1628 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1629 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1630 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1631 connector->name);
1632 break;
1633 }
1634 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1635
1636 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1637 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1638 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1639 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1640 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1641
1642 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1643 /* enable audio info frames (frames won't be set until audio is enabled) */
1644 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1645 /* required for audio info values to be updated */
1646 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1647 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1648
1649 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1650 /* required for audio info values to be updated */
1651 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1652 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1653
1654 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1655 /* anything other than 0 */
1656 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1657 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1658
1659 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1660
1661 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1662 /* set the default audio delay */
1663 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1664 /* should be suffient for all audio modes and small enough for all hblanks */
1665 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1666 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1667
1668 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1669 /* allow 60958 channel status fields to be updated */
1670 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1671 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1672
1673 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1674 if (bpc > 8)
1675 /* clear SW CTS value */
1676 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1677 else
1678 /* select SW CTS value */
1679 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1680 /* allow hw to sent ACR packets when required */
1681 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1682 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1683
1684 dce_v10_0_afmt_update_ACR(encoder, mode->clock);
1685
1686 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1687 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1688 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1689
1690 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1691 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1692 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1693
1694 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1695 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1696 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1697 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1698 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1699 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1700 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1701 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1702
1703 dce_v10_0_audio_write_speaker_allocation(encoder);
1704
1705 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1706 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1707
1708 dce_v10_0_afmt_audio_select_pin(encoder);
1709 dce_v10_0_audio_write_sad_regs(encoder);
1710 dce_v10_0_audio_write_latency_fields(encoder, mode);
1711
1712 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1713 if (err < 0) {
1714 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1715 return;
1716 }
1717
1718 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1719 if (err < 0) {
1720 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1721 return;
1722 }
1723
1724 dce_v10_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1725
1726 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1727 /* enable AVI info frames */
1728 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1729 /* required for audio info values to be updated */
1730 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1731 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1732
1733 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1734 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1735 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1736
1737 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1738 /* send audio packets */
1739 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1740 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1741
1742 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1743 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1744 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1745 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1746
1747 /* enable audio after to setting up hw */
1748 dce_v10_0_audio_enable(adev, dig->afmt->pin, true);
1749}
1750
1751static void dce_v10_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1752{
1753 struct drm_device *dev = encoder->dev;
1754 struct amdgpu_device *adev = drm_to_adev(dev);
1755 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1756 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1757
1758 if (!dig || !dig->afmt)
1759 return;
1760
1761 /* Silent, r600_hdmi_enable will raise WARN for us */
1762 if (enable && dig->afmt->enabled)
1763 return;
1764 if (!enable && !dig->afmt->enabled)
1765 return;
1766
1767 if (!enable && dig->afmt->pin) {
1768 dce_v10_0_audio_enable(adev, dig->afmt->pin, false);
1769 dig->afmt->pin = NULL;
1770 }
1771
1772 dig->afmt->enabled = enable;
1773
1774 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1775 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1776}
1777
1778static int dce_v10_0_afmt_init(struct amdgpu_device *adev)
1779{
1780 int i;
1781
1782 for (i = 0; i < adev->mode_info.num_dig; i++)
1783 adev->mode_info.afmt[i] = NULL;
1784
1785 /* DCE10 has audio blocks tied to DIG encoders */
1786 for (i = 0; i < adev->mode_info.num_dig; i++) {
1787 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1788 if (adev->mode_info.afmt[i]) {
1789 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1790 adev->mode_info.afmt[i]->id = i;
1791 } else {
1792 int j;
1793 for (j = 0; j < i; j++) {
1794 kfree(adev->mode_info.afmt[j]);
1795 adev->mode_info.afmt[j] = NULL;
1796 }
1797 return -ENOMEM;
1798 }
1799 }
1800 return 0;
1801}
1802
1803static void dce_v10_0_afmt_fini(struct amdgpu_device *adev)
1804{
1805 int i;
1806
1807 for (i = 0; i < adev->mode_info.num_dig; i++) {
1808 kfree(adev->mode_info.afmt[i]);
1809 adev->mode_info.afmt[i] = NULL;
1810 }
1811}
1812
1813static const u32 vga_control_regs[6] =
1814{
1815 mmD1VGA_CONTROL,
1816 mmD2VGA_CONTROL,
1817 mmD3VGA_CONTROL,
1818 mmD4VGA_CONTROL,
1819 mmD5VGA_CONTROL,
1820 mmD6VGA_CONTROL,
1821};
1822
1823static void dce_v10_0_vga_enable(struct drm_crtc *crtc, bool enable)
1824{
1825 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1826 struct drm_device *dev = crtc->dev;
1827 struct amdgpu_device *adev = drm_to_adev(dev);
1828 u32 vga_control;
1829
1830 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1831 if (enable)
1832 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1833 else
1834 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1835}
1836
1837static void dce_v10_0_grph_enable(struct drm_crtc *crtc, bool enable)
1838{
1839 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1840 struct drm_device *dev = crtc->dev;
1841 struct amdgpu_device *adev = drm_to_adev(dev);
1842
1843 if (enable)
1844 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1845 else
1846 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1847}
1848
1849static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
1850 struct drm_framebuffer *fb,
1851 int x, int y, int atomic)
1852{
1853 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1854 struct drm_device *dev = crtc->dev;
1855 struct amdgpu_device *adev = drm_to_adev(dev);
1856 struct drm_framebuffer *target_fb;
1857 struct drm_gem_object *obj;
1858 struct amdgpu_bo *abo;
1859 uint64_t fb_location, tiling_flags;
1860 uint32_t fb_format, fb_pitch_pixels;
1861 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1862 u32 pipe_config;
1863 u32 tmp, viewport_w, viewport_h;
1864 int r;
1865 bool bypass_lut = false;
1866
1867 /* no fb bound */
1868 if (!atomic && !crtc->primary->fb) {
1869 DRM_DEBUG_KMS("No FB bound\n");
1870 return 0;
1871 }
1872
1873 if (atomic)
1874 target_fb = fb;
1875 else
1876 target_fb = crtc->primary->fb;
1877
1878 /* If atomic, assume fb object is pinned & idle & fenced and
1879 * just update base pointers
1880 */
1881 obj = target_fb->obj[0];
1882 abo = gem_to_amdgpu_bo(obj);
1883 r = amdgpu_bo_reserve(abo, false);
1884 if (unlikely(r != 0))
1885 return r;
1886
1887 if (!atomic) {
1888 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1889 if (unlikely(r != 0)) {
1890 amdgpu_bo_unreserve(abo);
1891 return -EINVAL;
1892 }
1893 }
1894 fb_location = amdgpu_bo_gpu_offset(abo);
1895
1896 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1897 amdgpu_bo_unreserve(abo);
1898
1899 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1900
1901 switch (target_fb->format->format) {
1902 case DRM_FORMAT_C8:
1903 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1904 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1905 break;
1906 case DRM_FORMAT_XRGB4444:
1907 case DRM_FORMAT_ARGB4444:
1908 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1909 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1910#ifdef __BIG_ENDIAN
1911 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1912 ENDIAN_8IN16);
1913#endif
1914 break;
1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1918 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1919#ifdef __BIG_ENDIAN
1920 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1921 ENDIAN_8IN16);
1922#endif
1923 break;
1924 case DRM_FORMAT_BGRX5551:
1925 case DRM_FORMAT_BGRA5551:
1926 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1927 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1928#ifdef __BIG_ENDIAN
1929 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1930 ENDIAN_8IN16);
1931#endif
1932 break;
1933 case DRM_FORMAT_RGB565:
1934 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1935 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1936#ifdef __BIG_ENDIAN
1937 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1938 ENDIAN_8IN16);
1939#endif
1940 break;
1941 case DRM_FORMAT_XRGB8888:
1942 case DRM_FORMAT_ARGB8888:
1943 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1944 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1945#ifdef __BIG_ENDIAN
1946 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1947 ENDIAN_8IN32);
1948#endif
1949 break;
1950 case DRM_FORMAT_XRGB2101010:
1951 case DRM_FORMAT_ARGB2101010:
1952 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1953 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1954#ifdef __BIG_ENDIAN
1955 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1956 ENDIAN_8IN32);
1957#endif
1958 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1959 bypass_lut = true;
1960 break;
1961 case DRM_FORMAT_BGRX1010102:
1962 case DRM_FORMAT_BGRA1010102:
1963 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1964 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1965#ifdef __BIG_ENDIAN
1966 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1967 ENDIAN_8IN32);
1968#endif
1969 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1970 bypass_lut = true;
1971 break;
1972 case DRM_FORMAT_XBGR8888:
1973 case DRM_FORMAT_ABGR8888:
1974 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1975 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1976 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
1977 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
1978#ifdef __BIG_ENDIAN
1979 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1980 ENDIAN_8IN32);
1981#endif
1982 break;
1983 default:
1984 DRM_ERROR("Unsupported screen format %p4cc\n",
1985 &target_fb->format->format);
1986 return -EINVAL;
1987 }
1988
1989 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1990 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1991
1992 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1993 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1994 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1995 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1996 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1997
1998 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
1999 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2000 ARRAY_2D_TILED_THIN1);
2001 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2002 tile_split);
2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2004 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2006 mtaspect);
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2008 ADDR_SURF_MICRO_TILING_DISPLAY);
2009 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2010 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2011 ARRAY_1D_TILED_THIN1);
2012 }
2013
2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2015 pipe_config);
2016
2017 dce_v10_0_vga_enable(crtc, false);
2018
2019 /* Make sure surface address is updated at vertical blank rather than
2020 * horizontal blank
2021 */
2022 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2023 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2024 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2025 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2026
2027 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2028 upper_32_bits(fb_location));
2029 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2030 upper_32_bits(fb_location));
2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2032 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2034 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2035 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2036 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2037
2038 /*
2039 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2040 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2041 * retain the full precision throughout the pipeline.
2042 */
2043 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2044 if (bypass_lut)
2045 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2046 else
2047 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2048 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2049
2050 if (bypass_lut)
2051 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2052
2053 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2054 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2055 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2056 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2057 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2058 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2059
2060 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2061 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2062
2063 dce_v10_0_grph_enable(crtc, true);
2064
2065 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2066 target_fb->height);
2067
2068 x &= ~3;
2069 y &= ~1;
2070 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2071 (x << 16) | y);
2072 viewport_w = crtc->mode.hdisplay;
2073 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2074 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2075 (viewport_w << 16) | viewport_h);
2076
2077 /* set pageflip to happen anywhere in vblank interval */
2078 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2079
2080 if (!atomic && fb && fb != crtc->primary->fb) {
2081 abo = gem_to_amdgpu_bo(fb->obj[0]);
2082 r = amdgpu_bo_reserve(abo, true);
2083 if (unlikely(r != 0))
2084 return r;
2085 amdgpu_bo_unpin(abo);
2086 amdgpu_bo_unreserve(abo);
2087 }
2088
2089 /* Bytes per pixel may have changed */
2090 dce_v10_0_bandwidth_update(adev);
2091
2092 return 0;
2093}
2094
2095static void dce_v10_0_set_interleave(struct drm_crtc *crtc,
2096 struct drm_display_mode *mode)
2097{
2098 struct drm_device *dev = crtc->dev;
2099 struct amdgpu_device *adev = drm_to_adev(dev);
2100 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2101 u32 tmp;
2102
2103 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2104 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2105 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2106 else
2107 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2108 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2109}
2110
2111static void dce_v10_0_crtc_load_lut(struct drm_crtc *crtc)
2112{
2113 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2114 struct drm_device *dev = crtc->dev;
2115 struct amdgpu_device *adev = drm_to_adev(dev);
2116 u16 *r, *g, *b;
2117 int i;
2118 u32 tmp;
2119
2120 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2121
2122 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2123 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2124 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_OVL_MODE, 0);
2125 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2126
2127 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2128 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2129 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2130
2131 tmp = RREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset);
2132 tmp = REG_SET_FIELD(tmp, PRESCALE_OVL_CONTROL, OVL_PRESCALE_BYPASS, 1);
2133 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2134
2135 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2136 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2137 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, OVL_INPUT_GAMMA_MODE, 0);
2138 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2139
2140 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2141
2142 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2143 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2144 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2145
2146 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2147 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2148 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2149
2150 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2151 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2152
2153 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2154 r = crtc->gamma_store;
2155 g = r + crtc->gamma_size;
2156 b = g + crtc->gamma_size;
2157 for (i = 0; i < 256; i++) {
2158 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2159 ((*r++ & 0xffc0) << 14) |
2160 ((*g++ & 0xffc0) << 4) |
2161 (*b++ >> 6));
2162 }
2163
2164 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2165 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2166 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, OVL_DEGAMMA_MODE, 0);
2167 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2168 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2169
2170 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2171 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2172 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, OVL_GAMUT_REMAP_MODE, 0);
2173 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174
2175 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2176 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2177 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, OVL_REGAMMA_MODE, 0);
2178 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2179
2180 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2181 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2182 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_OVL_MODE, 0);
2183 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2184
2185 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2186 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2187 /* XXX this only needs to be programmed once per crtc at startup,
2188 * not sure where the best place for it is
2189 */
2190 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2191 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2192 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2193}
2194
2195static int dce_v10_0_pick_dig_encoder(struct drm_encoder *encoder)
2196{
2197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2199
2200 switch (amdgpu_encoder->encoder_id) {
2201 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2202 if (dig->linkb)
2203 return 1;
2204 else
2205 return 0;
2206 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2207 if (dig->linkb)
2208 return 3;
2209 else
2210 return 2;
2211 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2212 if (dig->linkb)
2213 return 5;
2214 else
2215 return 4;
2216 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2217 return 6;
2218 default:
2219 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2220 return 0;
2221 }
2222}
2223
2224/**
2225 * dce_v10_0_pick_pll - Allocate a PPLL for use by the crtc.
2226 *
2227 * @crtc: drm crtc
2228 *
2229 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2230 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2231 * monitors a dedicated PPLL must be used. If a particular board has
2232 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2233 * as there is no need to program the PLL itself. If we are not able to
2234 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2235 * avoid messing up an existing monitor.
2236 *
2237 * Asic specific PLL information
2238 *
2239 * DCE 10.x
2240 * Tonga
2241 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2242 * CI
2243 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2244 *
2245 */
2246static u32 dce_v10_0_pick_pll(struct drm_crtc *crtc)
2247{
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 struct drm_device *dev = crtc->dev;
2250 struct amdgpu_device *adev = drm_to_adev(dev);
2251 u32 pll_in_use;
2252 int pll;
2253
2254 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2255 if (adev->clock.dp_extclk)
2256 /* skip PPLL programming if using ext clock */
2257 return ATOM_PPLL_INVALID;
2258 else {
2259 /* use the same PPLL for all DP monitors */
2260 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2261 if (pll != ATOM_PPLL_INVALID)
2262 return pll;
2263 }
2264 } else {
2265 /* use the same PPLL for all monitors with the same clock */
2266 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2267 if (pll != ATOM_PPLL_INVALID)
2268 return pll;
2269 }
2270
2271 /* DCE10 has PPLL0, PPLL1, and PPLL2 */
2272 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2273 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2274 return ATOM_PPLL2;
2275 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2276 return ATOM_PPLL1;
2277 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2278 return ATOM_PPLL0;
2279 DRM_ERROR("unable to allocate a PPLL\n");
2280 return ATOM_PPLL_INVALID;
2281}
2282
2283static void dce_v10_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2284{
2285 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2286 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2287 uint32_t cur_lock;
2288
2289 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2290 if (lock)
2291 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2292 else
2293 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2294 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2295}
2296
2297static void dce_v10_0_hide_cursor(struct drm_crtc *crtc)
2298{
2299 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2300 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2301 u32 tmp;
2302
2303 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2304 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2305 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2306}
2307
2308static void dce_v10_0_show_cursor(struct drm_crtc *crtc)
2309{
2310 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2311 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2312 u32 tmp;
2313
2314 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2315 upper_32_bits(amdgpu_crtc->cursor_addr));
2316 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2317 lower_32_bits(amdgpu_crtc->cursor_addr));
2318
2319 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2320 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2321 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2322 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2323}
2324
2325static int dce_v10_0_cursor_move_locked(struct drm_crtc *crtc,
2326 int x, int y)
2327{
2328 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2329 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2330 int xorigin = 0, yorigin = 0;
2331
2332 amdgpu_crtc->cursor_x = x;
2333 amdgpu_crtc->cursor_y = y;
2334
2335 /* avivo cursor are offset into the total surface */
2336 x += crtc->x;
2337 y += crtc->y;
2338 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2339
2340 if (x < 0) {
2341 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2342 x = 0;
2343 }
2344 if (y < 0) {
2345 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2346 y = 0;
2347 }
2348
2349 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2350 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2351 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2352 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2353
2354 return 0;
2355}
2356
2357static int dce_v10_0_crtc_cursor_move(struct drm_crtc *crtc,
2358 int x, int y)
2359{
2360 int ret;
2361
2362 dce_v10_0_lock_cursor(crtc, true);
2363 ret = dce_v10_0_cursor_move_locked(crtc, x, y);
2364 dce_v10_0_lock_cursor(crtc, false);
2365
2366 return ret;
2367}
2368
2369static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc,
2370 struct drm_file *file_priv,
2371 uint32_t handle,
2372 uint32_t width,
2373 uint32_t height,
2374 int32_t hot_x,
2375 int32_t hot_y)
2376{
2377 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2378 struct drm_gem_object *obj;
2379 struct amdgpu_bo *aobj;
2380 int ret;
2381
2382 if (!handle) {
2383 /* turn off cursor */
2384 dce_v10_0_hide_cursor(crtc);
2385 obj = NULL;
2386 goto unpin;
2387 }
2388
2389 if ((width > amdgpu_crtc->max_cursor_width) ||
2390 (height > amdgpu_crtc->max_cursor_height)) {
2391 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2392 return -EINVAL;
2393 }
2394
2395 obj = drm_gem_object_lookup(file_priv, handle);
2396 if (!obj) {
2397 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2398 return -ENOENT;
2399 }
2400
2401 aobj = gem_to_amdgpu_bo(obj);
2402 ret = amdgpu_bo_reserve(aobj, false);
2403 if (ret != 0) {
2404 drm_gem_object_put(obj);
2405 return ret;
2406 }
2407
2408 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2409 amdgpu_bo_unreserve(aobj);
2410 if (ret) {
2411 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2412 drm_gem_object_put(obj);
2413 return ret;
2414 }
2415 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2416
2417 dce_v10_0_lock_cursor(crtc, true);
2418
2419 if (width != amdgpu_crtc->cursor_width ||
2420 height != amdgpu_crtc->cursor_height ||
2421 hot_x != amdgpu_crtc->cursor_hot_x ||
2422 hot_y != amdgpu_crtc->cursor_hot_y) {
2423 int x, y;
2424
2425 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2426 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2427
2428 dce_v10_0_cursor_move_locked(crtc, x, y);
2429
2430 amdgpu_crtc->cursor_width = width;
2431 amdgpu_crtc->cursor_height = height;
2432 amdgpu_crtc->cursor_hot_x = hot_x;
2433 amdgpu_crtc->cursor_hot_y = hot_y;
2434 }
2435
2436 dce_v10_0_show_cursor(crtc);
2437 dce_v10_0_lock_cursor(crtc, false);
2438
2439unpin:
2440 if (amdgpu_crtc->cursor_bo) {
2441 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2442 ret = amdgpu_bo_reserve(aobj, true);
2443 if (likely(ret == 0)) {
2444 amdgpu_bo_unpin(aobj);
2445 amdgpu_bo_unreserve(aobj);
2446 }
2447 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2448 }
2449
2450 amdgpu_crtc->cursor_bo = obj;
2451 return 0;
2452}
2453
2454static void dce_v10_0_cursor_reset(struct drm_crtc *crtc)
2455{
2456 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2457
2458 if (amdgpu_crtc->cursor_bo) {
2459 dce_v10_0_lock_cursor(crtc, true);
2460
2461 dce_v10_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2462 amdgpu_crtc->cursor_y);
2463
2464 dce_v10_0_show_cursor(crtc);
2465
2466 dce_v10_0_lock_cursor(crtc, false);
2467 }
2468}
2469
2470static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2471 u16 *blue, uint32_t size,
2472 struct drm_modeset_acquire_ctx *ctx)
2473{
2474 dce_v10_0_crtc_load_lut(crtc);
2475
2476 return 0;
2477}
2478
2479static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc)
2480{
2481 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2482
2483 drm_crtc_cleanup(crtc);
2484 kfree(amdgpu_crtc);
2485}
2486
2487static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = {
2488 .cursor_set2 = dce_v10_0_crtc_cursor_set2,
2489 .cursor_move = dce_v10_0_crtc_cursor_move,
2490 .gamma_set = dce_v10_0_crtc_gamma_set,
2491 .set_config = amdgpu_display_crtc_set_config,
2492 .destroy = dce_v10_0_crtc_destroy,
2493 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2494 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2495 .enable_vblank = amdgpu_enable_vblank_kms,
2496 .disable_vblank = amdgpu_disable_vblank_kms,
2497 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2498};
2499
2500static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2501{
2502 struct drm_device *dev = crtc->dev;
2503 struct amdgpu_device *adev = drm_to_adev(dev);
2504 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2505 unsigned type;
2506
2507 switch (mode) {
2508 case DRM_MODE_DPMS_ON:
2509 amdgpu_crtc->enabled = true;
2510 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2511 dce_v10_0_vga_enable(crtc, true);
2512 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2513 dce_v10_0_vga_enable(crtc, false);
2514 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2515 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2516 amdgpu_crtc->crtc_id);
2517 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2518 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2519 drm_crtc_vblank_on(crtc);
2520 dce_v10_0_crtc_load_lut(crtc);
2521 break;
2522 case DRM_MODE_DPMS_STANDBY:
2523 case DRM_MODE_DPMS_SUSPEND:
2524 case DRM_MODE_DPMS_OFF:
2525 drm_crtc_vblank_off(crtc);
2526 if (amdgpu_crtc->enabled) {
2527 dce_v10_0_vga_enable(crtc, true);
2528 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2529 dce_v10_0_vga_enable(crtc, false);
2530 }
2531 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2532 amdgpu_crtc->enabled = false;
2533 break;
2534 }
2535 /* adjust pm to dpms */
2536 amdgpu_dpm_compute_clocks(adev);
2537}
2538
2539static void dce_v10_0_crtc_prepare(struct drm_crtc *crtc)
2540{
2541 /* disable crtc pair power gating before programming */
2542 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2543 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2544 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2545}
2546
2547static void dce_v10_0_crtc_commit(struct drm_crtc *crtc)
2548{
2549 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2550 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2551}
2552
2553static void dce_v10_0_crtc_disable(struct drm_crtc *crtc)
2554{
2555 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2556 struct drm_device *dev = crtc->dev;
2557 struct amdgpu_device *adev = drm_to_adev(dev);
2558 struct amdgpu_atom_ss ss;
2559 int i;
2560
2561 dce_v10_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2562 if (crtc->primary->fb) {
2563 int r;
2564 struct amdgpu_bo *abo;
2565
2566 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2567 r = amdgpu_bo_reserve(abo, true);
2568 if (unlikely(r))
2569 DRM_ERROR("failed to reserve abo before unpin\n");
2570 else {
2571 amdgpu_bo_unpin(abo);
2572 amdgpu_bo_unreserve(abo);
2573 }
2574 }
2575 /* disable the GRPH */
2576 dce_v10_0_grph_enable(crtc, false);
2577
2578 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2579
2580 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2581 if (adev->mode_info.crtcs[i] &&
2582 adev->mode_info.crtcs[i]->enabled &&
2583 i != amdgpu_crtc->crtc_id &&
2584 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2585 /* one other crtc is using this pll don't turn
2586 * off the pll
2587 */
2588 goto done;
2589 }
2590 }
2591
2592 switch (amdgpu_crtc->pll_id) {
2593 case ATOM_PPLL0:
2594 case ATOM_PPLL1:
2595 case ATOM_PPLL2:
2596 /* disable the ppll */
2597 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2598 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2599 break;
2600 default:
2601 break;
2602 }
2603done:
2604 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2605 amdgpu_crtc->adjusted_clock = 0;
2606 amdgpu_crtc->encoder = NULL;
2607 amdgpu_crtc->connector = NULL;
2608}
2609
2610static int dce_v10_0_crtc_mode_set(struct drm_crtc *crtc,
2611 struct drm_display_mode *mode,
2612 struct drm_display_mode *adjusted_mode,
2613 int x, int y, struct drm_framebuffer *old_fb)
2614{
2615 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2616
2617 if (!amdgpu_crtc->adjusted_clock)
2618 return -EINVAL;
2619
2620 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2621 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2622 dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2623 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2624 amdgpu_atombios_crtc_scaler_setup(crtc);
2625 dce_v10_0_cursor_reset(crtc);
2626 /* update the hw version fpr dpm */
2627 amdgpu_crtc->hw_mode = *adjusted_mode;
2628
2629 return 0;
2630}
2631
2632static bool dce_v10_0_crtc_mode_fixup(struct drm_crtc *crtc,
2633 const struct drm_display_mode *mode,
2634 struct drm_display_mode *adjusted_mode)
2635{
2636 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2637 struct drm_device *dev = crtc->dev;
2638 struct drm_encoder *encoder;
2639
2640 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2641 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2642 if (encoder->crtc == crtc) {
2643 amdgpu_crtc->encoder = encoder;
2644 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2645 break;
2646 }
2647 }
2648 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2649 amdgpu_crtc->encoder = NULL;
2650 amdgpu_crtc->connector = NULL;
2651 return false;
2652 }
2653 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2654 return false;
2655 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2656 return false;
2657 /* pick pll */
2658 amdgpu_crtc->pll_id = dce_v10_0_pick_pll(crtc);
2659 /* if we can't get a PPLL for a non-DP encoder, fail */
2660 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2661 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2662 return false;
2663
2664 return true;
2665}
2666
2667static int dce_v10_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2668 struct drm_framebuffer *old_fb)
2669{
2670 return dce_v10_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2671}
2672
2673static int dce_v10_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2674 struct drm_framebuffer *fb,
2675 int x, int y, enum mode_set_atomic state)
2676{
2677 return dce_v10_0_crtc_do_set_base(crtc, fb, x, y, 1);
2678}
2679
2680static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = {
2681 .dpms = dce_v10_0_crtc_dpms,
2682 .mode_fixup = dce_v10_0_crtc_mode_fixup,
2683 .mode_set = dce_v10_0_crtc_mode_set,
2684 .mode_set_base = dce_v10_0_crtc_set_base,
2685 .mode_set_base_atomic = dce_v10_0_crtc_set_base_atomic,
2686 .prepare = dce_v10_0_crtc_prepare,
2687 .commit = dce_v10_0_crtc_commit,
2688 .disable = dce_v10_0_crtc_disable,
2689 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2690};
2691
2692static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index)
2693{
2694 struct amdgpu_crtc *amdgpu_crtc;
2695
2696 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2697 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2698 if (amdgpu_crtc == NULL)
2699 return -ENOMEM;
2700
2701 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v10_0_crtc_funcs);
2702
2703 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2704 amdgpu_crtc->crtc_id = index;
2705 adev->mode_info.crtcs[index] = amdgpu_crtc;
2706
2707 amdgpu_crtc->max_cursor_width = 128;
2708 amdgpu_crtc->max_cursor_height = 128;
2709 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2710 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2711
2712 switch (amdgpu_crtc->crtc_id) {
2713 case 0:
2714 default:
2715 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2716 break;
2717 case 1:
2718 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2719 break;
2720 case 2:
2721 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2722 break;
2723 case 3:
2724 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2725 break;
2726 case 4:
2727 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2728 break;
2729 case 5:
2730 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2731 break;
2732 }
2733
2734 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2735 amdgpu_crtc->adjusted_clock = 0;
2736 amdgpu_crtc->encoder = NULL;
2737 amdgpu_crtc->connector = NULL;
2738 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v10_0_crtc_helper_funcs);
2739
2740 return 0;
2741}
2742
2743static int dce_v10_0_early_init(void *handle)
2744{
2745 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2746
2747 adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg;
2748 adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg;
2749
2750 dce_v10_0_set_display_funcs(adev);
2751
2752 adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
2753
2754 switch (adev->asic_type) {
2755 case CHIP_FIJI:
2756 case CHIP_TONGA:
2757 adev->mode_info.num_hpd = 6;
2758 adev->mode_info.num_dig = 7;
2759 break;
2760 default:
2761 /* FIXME: not supported yet */
2762 return -EINVAL;
2763 }
2764
2765 dce_v10_0_set_irq_funcs(adev);
2766
2767 return 0;
2768}
2769
2770static int dce_v10_0_sw_init(void *handle)
2771{
2772 int r, i;
2773 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2774
2775 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2776 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2777 if (r)
2778 return r;
2779 }
2780
2781 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2782 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2783 if (r)
2784 return r;
2785 }
2786
2787 /* HPD hotplug */
2788 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2789 if (r)
2790 return r;
2791
2792 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2793
2794 adev_to_drm(adev)->mode_config.async_page_flip = true;
2795
2796 adev_to_drm(adev)->mode_config.max_width = 16384;
2797 adev_to_drm(adev)->mode_config.max_height = 16384;
2798
2799 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2800 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2801
2802 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2803
2804 r = amdgpu_display_modeset_create_props(adev);
2805 if (r)
2806 return r;
2807
2808 adev_to_drm(adev)->mode_config.max_width = 16384;
2809 adev_to_drm(adev)->mode_config.max_height = 16384;
2810
2811 /* allocate crtcs */
2812 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2813 r = dce_v10_0_crtc_init(adev, i);
2814 if (r)
2815 return r;
2816 }
2817
2818 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2819 amdgpu_display_print_display_setup(adev_to_drm(adev));
2820 else
2821 return -EINVAL;
2822
2823 /* setup afmt */
2824 r = dce_v10_0_afmt_init(adev);
2825 if (r)
2826 return r;
2827
2828 r = dce_v10_0_audio_init(adev);
2829 if (r)
2830 return r;
2831
2832 /* Disable vblank IRQs aggressively for power-saving */
2833 /* XXX: can this be enabled for DC? */
2834 adev_to_drm(adev)->vblank_disable_immediate = true;
2835
2836 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2837 if (r)
2838 return r;
2839
2840 INIT_WORK(&adev->hotplug_work,
2841 amdgpu_display_hotplug_work_func);
2842
2843 drm_kms_helper_poll_init(adev_to_drm(adev));
2844
2845 adev->mode_info.mode_config_initialized = true;
2846 return 0;
2847}
2848
2849static int dce_v10_0_sw_fini(void *handle)
2850{
2851 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2852
2853 kfree(adev->mode_info.bios_hardcoded_edid);
2854
2855 drm_kms_helper_poll_fini(adev_to_drm(adev));
2856
2857 dce_v10_0_audio_fini(adev);
2858
2859 dce_v10_0_afmt_fini(adev);
2860
2861 drm_mode_config_cleanup(adev_to_drm(adev));
2862 adev->mode_info.mode_config_initialized = false;
2863
2864 return 0;
2865}
2866
2867static int dce_v10_0_hw_init(void *handle)
2868{
2869 int i;
2870 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2871
2872 dce_v10_0_init_golden_registers(adev);
2873
2874 /* disable vga render */
2875 dce_v10_0_set_vga_render_state(adev, false);
2876 /* init dig PHYs, disp eng pll */
2877 amdgpu_atombios_encoder_init_dig(adev);
2878 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2879
2880 /* initialize hpd */
2881 dce_v10_0_hpd_init(adev);
2882
2883 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2884 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2885 }
2886
2887 dce_v10_0_pageflip_interrupt_init(adev);
2888
2889 return 0;
2890}
2891
2892static int dce_v10_0_hw_fini(void *handle)
2893{
2894 int i;
2895 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2896
2897 dce_v10_0_hpd_fini(adev);
2898
2899 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2900 dce_v10_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2901 }
2902
2903 dce_v10_0_pageflip_interrupt_fini(adev);
2904
2905 flush_work(&adev->hotplug_work);
2906
2907 return 0;
2908}
2909
2910static int dce_v10_0_suspend(void *handle)
2911{
2912 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2913 int r;
2914
2915 r = amdgpu_display_suspend_helper(adev);
2916 if (r)
2917 return r;
2918
2919 adev->mode_info.bl_level =
2920 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2921
2922 return dce_v10_0_hw_fini(handle);
2923}
2924
2925static int dce_v10_0_resume(void *handle)
2926{
2927 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2928 int ret;
2929
2930 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2931 adev->mode_info.bl_level);
2932
2933 ret = dce_v10_0_hw_init(handle);
2934
2935 /* turn on the BL */
2936 if (adev->mode_info.bl_encoder) {
2937 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2938 adev->mode_info.bl_encoder);
2939 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2940 bl_level);
2941 }
2942 if (ret)
2943 return ret;
2944
2945 return amdgpu_display_resume_helper(adev);
2946}
2947
2948static bool dce_v10_0_is_idle(void *handle)
2949{
2950 return true;
2951}
2952
2953static int dce_v10_0_wait_for_idle(void *handle)
2954{
2955 return 0;
2956}
2957
2958static bool dce_v10_0_check_soft_reset(void *handle)
2959{
2960 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2961
2962 return dce_v10_0_is_display_hung(adev);
2963}
2964
2965static int dce_v10_0_soft_reset(void *handle)
2966{
2967 u32 srbm_soft_reset = 0, tmp;
2968 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2969
2970 if (dce_v10_0_is_display_hung(adev))
2971 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
2972
2973 if (srbm_soft_reset) {
2974 tmp = RREG32(mmSRBM_SOFT_RESET);
2975 tmp |= srbm_soft_reset;
2976 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
2977 WREG32(mmSRBM_SOFT_RESET, tmp);
2978 tmp = RREG32(mmSRBM_SOFT_RESET);
2979
2980 udelay(50);
2981
2982 tmp &= ~srbm_soft_reset;
2983 WREG32(mmSRBM_SOFT_RESET, tmp);
2984 tmp = RREG32(mmSRBM_SOFT_RESET);
2985
2986 /* Wait a little for things to settle down */
2987 udelay(50);
2988 }
2989 return 0;
2990}
2991
2992static void dce_v10_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2993 int crtc,
2994 enum amdgpu_interrupt_state state)
2995{
2996 u32 lb_interrupt_mask;
2997
2998 if (crtc >= adev->mode_info.num_crtc) {
2999 DRM_DEBUG("invalid crtc %d\n", crtc);
3000 return;
3001 }
3002
3003 switch (state) {
3004 case AMDGPU_IRQ_STATE_DISABLE:
3005 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3006 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3007 VBLANK_INTERRUPT_MASK, 0);
3008 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3009 break;
3010 case AMDGPU_IRQ_STATE_ENABLE:
3011 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3012 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3013 VBLANK_INTERRUPT_MASK, 1);
3014 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3015 break;
3016 default:
3017 break;
3018 }
3019}
3020
3021static void dce_v10_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3022 int crtc,
3023 enum amdgpu_interrupt_state state)
3024{
3025 u32 lb_interrupt_mask;
3026
3027 if (crtc >= adev->mode_info.num_crtc) {
3028 DRM_DEBUG("invalid crtc %d\n", crtc);
3029 return;
3030 }
3031
3032 switch (state) {
3033 case AMDGPU_IRQ_STATE_DISABLE:
3034 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3035 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3036 VLINE_INTERRUPT_MASK, 0);
3037 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3038 break;
3039 case AMDGPU_IRQ_STATE_ENABLE:
3040 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3041 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3042 VLINE_INTERRUPT_MASK, 1);
3043 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3044 break;
3045 default:
3046 break;
3047 }
3048}
3049
3050static int dce_v10_0_set_hpd_irq_state(struct amdgpu_device *adev,
3051 struct amdgpu_irq_src *source,
3052 unsigned hpd,
3053 enum amdgpu_interrupt_state state)
3054{
3055 u32 tmp;
3056
3057 if (hpd >= adev->mode_info.num_hpd) {
3058 DRM_DEBUG("invalid hdp %d\n", hpd);
3059 return 0;
3060 }
3061
3062 switch (state) {
3063 case AMDGPU_IRQ_STATE_DISABLE:
3064 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3065 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3066 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3067 break;
3068 case AMDGPU_IRQ_STATE_ENABLE:
3069 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3070 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3071 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3072 break;
3073 default:
3074 break;
3075 }
3076
3077 return 0;
3078}
3079
3080static int dce_v10_0_set_crtc_irq_state(struct amdgpu_device *adev,
3081 struct amdgpu_irq_src *source,
3082 unsigned type,
3083 enum amdgpu_interrupt_state state)
3084{
3085 switch (type) {
3086 case AMDGPU_CRTC_IRQ_VBLANK1:
3087 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3088 break;
3089 case AMDGPU_CRTC_IRQ_VBLANK2:
3090 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3091 break;
3092 case AMDGPU_CRTC_IRQ_VBLANK3:
3093 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3094 break;
3095 case AMDGPU_CRTC_IRQ_VBLANK4:
3096 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3097 break;
3098 case AMDGPU_CRTC_IRQ_VBLANK5:
3099 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3100 break;
3101 case AMDGPU_CRTC_IRQ_VBLANK6:
3102 dce_v10_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3103 break;
3104 case AMDGPU_CRTC_IRQ_VLINE1:
3105 dce_v10_0_set_crtc_vline_interrupt_state(adev, 0, state);
3106 break;
3107 case AMDGPU_CRTC_IRQ_VLINE2:
3108 dce_v10_0_set_crtc_vline_interrupt_state(adev, 1, state);
3109 break;
3110 case AMDGPU_CRTC_IRQ_VLINE3:
3111 dce_v10_0_set_crtc_vline_interrupt_state(adev, 2, state);
3112 break;
3113 case AMDGPU_CRTC_IRQ_VLINE4:
3114 dce_v10_0_set_crtc_vline_interrupt_state(adev, 3, state);
3115 break;
3116 case AMDGPU_CRTC_IRQ_VLINE5:
3117 dce_v10_0_set_crtc_vline_interrupt_state(adev, 4, state);
3118 break;
3119 case AMDGPU_CRTC_IRQ_VLINE6:
3120 dce_v10_0_set_crtc_vline_interrupt_state(adev, 5, state);
3121 break;
3122 default:
3123 break;
3124 }
3125 return 0;
3126}
3127
3128static int dce_v10_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3129 struct amdgpu_irq_src *src,
3130 unsigned type,
3131 enum amdgpu_interrupt_state state)
3132{
3133 u32 reg;
3134
3135 if (type >= adev->mode_info.num_crtc) {
3136 DRM_ERROR("invalid pageflip crtc %d\n", type);
3137 return -EINVAL;
3138 }
3139
3140 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3141 if (state == AMDGPU_IRQ_STATE_DISABLE)
3142 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3143 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3144 else
3145 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3146 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3147
3148 return 0;
3149}
3150
3151static int dce_v10_0_pageflip_irq(struct amdgpu_device *adev,
3152 struct amdgpu_irq_src *source,
3153 struct amdgpu_iv_entry *entry)
3154{
3155 unsigned long flags;
3156 unsigned crtc_id;
3157 struct amdgpu_crtc *amdgpu_crtc;
3158 struct amdgpu_flip_work *works;
3159
3160 crtc_id = (entry->src_id - 8) >> 1;
3161 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3162
3163 if (crtc_id >= adev->mode_info.num_crtc) {
3164 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3165 return -EINVAL;
3166 }
3167
3168 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3169 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3170 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3171 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3172
3173 /* IRQ could occur when in initial stage */
3174 if (amdgpu_crtc == NULL)
3175 return 0;
3176
3177 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3178 works = amdgpu_crtc->pflip_works;
3179 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED) {
3180 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3181 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3182 amdgpu_crtc->pflip_status,
3183 AMDGPU_FLIP_SUBMITTED);
3184 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3185 return 0;
3186 }
3187
3188 /* page flip completed. clean up */
3189 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3190 amdgpu_crtc->pflip_works = NULL;
3191
3192 /* wakeup usersapce */
3193 if (works->event)
3194 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3195
3196 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3197
3198 drm_crtc_vblank_put(&amdgpu_crtc->base);
3199 schedule_work(&works->unpin_work);
3200
3201 return 0;
3202}
3203
3204static void dce_v10_0_hpd_int_ack(struct amdgpu_device *adev,
3205 int hpd)
3206{
3207 u32 tmp;
3208
3209 if (hpd >= adev->mode_info.num_hpd) {
3210 DRM_DEBUG("invalid hdp %d\n", hpd);
3211 return;
3212 }
3213
3214 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3215 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3216 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3217}
3218
3219static void dce_v10_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3220 int crtc)
3221{
3222 u32 tmp;
3223
3224 if (crtc >= adev->mode_info.num_crtc) {
3225 DRM_DEBUG("invalid crtc %d\n", crtc);
3226 return;
3227 }
3228
3229 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3230 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3231 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3232}
3233
3234static void dce_v10_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3235 int crtc)
3236{
3237 u32 tmp;
3238
3239 if (crtc >= adev->mode_info.num_crtc) {
3240 DRM_DEBUG("invalid crtc %d\n", crtc);
3241 return;
3242 }
3243
3244 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3245 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3246 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3247}
3248
3249static int dce_v10_0_crtc_irq(struct amdgpu_device *adev,
3250 struct amdgpu_irq_src *source,
3251 struct amdgpu_iv_entry *entry)
3252{
3253 unsigned crtc = entry->src_id - 1;
3254 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3255 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, crtc);
3256
3257 switch (entry->src_data[0]) {
3258 case 0: /* vblank */
3259 if (disp_int & interrupt_status_offsets[crtc].vblank)
3260 dce_v10_0_crtc_vblank_int_ack(adev, crtc);
3261 else
3262 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3263
3264 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3265 drm_handle_vblank(adev_to_drm(adev), crtc);
3266 }
3267 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3268
3269 break;
3270 case 1: /* vline */
3271 if (disp_int & interrupt_status_offsets[crtc].vline)
3272 dce_v10_0_crtc_vline_int_ack(adev, crtc);
3273 else
3274 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3275
3276 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3277
3278 break;
3279 default:
3280 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3281 break;
3282 }
3283
3284 return 0;
3285}
3286
3287static int dce_v10_0_hpd_irq(struct amdgpu_device *adev,
3288 struct amdgpu_irq_src *source,
3289 struct amdgpu_iv_entry *entry)
3290{
3291 uint32_t disp_int, mask;
3292 unsigned hpd;
3293
3294 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3295 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3296 return 0;
3297 }
3298
3299 hpd = entry->src_data[0];
3300 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3301 mask = interrupt_status_offsets[hpd].hpd;
3302
3303 if (disp_int & mask) {
3304 dce_v10_0_hpd_int_ack(adev, hpd);
3305 schedule_work(&adev->hotplug_work);
3306 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3307 }
3308
3309 return 0;
3310}
3311
3312static int dce_v10_0_set_clockgating_state(void *handle,
3313 enum amd_clockgating_state state)
3314{
3315 return 0;
3316}
3317
3318static int dce_v10_0_set_powergating_state(void *handle,
3319 enum amd_powergating_state state)
3320{
3321 return 0;
3322}
3323
3324static const struct amd_ip_funcs dce_v10_0_ip_funcs = {
3325 .name = "dce_v10_0",
3326 .early_init = dce_v10_0_early_init,
3327 .late_init = NULL,
3328 .sw_init = dce_v10_0_sw_init,
3329 .sw_fini = dce_v10_0_sw_fini,
3330 .hw_init = dce_v10_0_hw_init,
3331 .hw_fini = dce_v10_0_hw_fini,
3332 .suspend = dce_v10_0_suspend,
3333 .resume = dce_v10_0_resume,
3334 .is_idle = dce_v10_0_is_idle,
3335 .wait_for_idle = dce_v10_0_wait_for_idle,
3336 .check_soft_reset = dce_v10_0_check_soft_reset,
3337 .soft_reset = dce_v10_0_soft_reset,
3338 .set_clockgating_state = dce_v10_0_set_clockgating_state,
3339 .set_powergating_state = dce_v10_0_set_powergating_state,
3340};
3341
3342static void
3343dce_v10_0_encoder_mode_set(struct drm_encoder *encoder,
3344 struct drm_display_mode *mode,
3345 struct drm_display_mode *adjusted_mode)
3346{
3347 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3348
3349 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3350
3351 /* need to call this here rather than in prepare() since we need some crtc info */
3352 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3353
3354 /* set scaler clears this on some chips */
3355 dce_v10_0_set_interleave(encoder->crtc, mode);
3356
3357 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3358 dce_v10_0_afmt_enable(encoder, true);
3359 dce_v10_0_afmt_setmode(encoder, adjusted_mode);
3360 }
3361}
3362
3363static void dce_v10_0_encoder_prepare(struct drm_encoder *encoder)
3364{
3365 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3366 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3367 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3368
3369 if ((amdgpu_encoder->active_device &
3370 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3371 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3372 ENCODER_OBJECT_ID_NONE)) {
3373 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3374 if (dig) {
3375 dig->dig_encoder = dce_v10_0_pick_dig_encoder(encoder);
3376 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3377 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3378 }
3379 }
3380
3381 amdgpu_atombios_scratch_regs_lock(adev, true);
3382
3383 if (connector) {
3384 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3385
3386 /* select the clock/data port if it uses a router */
3387 if (amdgpu_connector->router.cd_valid)
3388 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3389
3390 /* turn eDP panel on for mode set */
3391 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3392 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3393 ATOM_TRANSMITTER_ACTION_POWER_ON);
3394 }
3395
3396 /* this is needed for the pll/ss setup to work correctly in some cases */
3397 amdgpu_atombios_encoder_set_crtc_source(encoder);
3398 /* set up the FMT blocks */
3399 dce_v10_0_program_fmt(encoder);
3400}
3401
3402static void dce_v10_0_encoder_commit(struct drm_encoder *encoder)
3403{
3404 struct drm_device *dev = encoder->dev;
3405 struct amdgpu_device *adev = drm_to_adev(dev);
3406
3407 /* need to call this here as we need the crtc set up */
3408 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3409 amdgpu_atombios_scratch_regs_lock(adev, false);
3410}
3411
3412static void dce_v10_0_encoder_disable(struct drm_encoder *encoder)
3413{
3414 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3415 struct amdgpu_encoder_atom_dig *dig;
3416
3417 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3418
3419 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3420 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3421 dce_v10_0_afmt_enable(encoder, false);
3422 dig = amdgpu_encoder->enc_priv;
3423 dig->dig_encoder = -1;
3424 }
3425 amdgpu_encoder->active_device = 0;
3426}
3427
3428/* these are handled by the primary encoders */
3429static void dce_v10_0_ext_prepare(struct drm_encoder *encoder)
3430{
3431
3432}
3433
3434static void dce_v10_0_ext_commit(struct drm_encoder *encoder)
3435{
3436
3437}
3438
3439static void
3440dce_v10_0_ext_mode_set(struct drm_encoder *encoder,
3441 struct drm_display_mode *mode,
3442 struct drm_display_mode *adjusted_mode)
3443{
3444
3445}
3446
3447static void dce_v10_0_ext_disable(struct drm_encoder *encoder)
3448{
3449
3450}
3451
3452static void
3453dce_v10_0_ext_dpms(struct drm_encoder *encoder, int mode)
3454{
3455
3456}
3457
3458static const struct drm_encoder_helper_funcs dce_v10_0_ext_helper_funcs = {
3459 .dpms = dce_v10_0_ext_dpms,
3460 .prepare = dce_v10_0_ext_prepare,
3461 .mode_set = dce_v10_0_ext_mode_set,
3462 .commit = dce_v10_0_ext_commit,
3463 .disable = dce_v10_0_ext_disable,
3464 /* no detect for TMDS/LVDS yet */
3465};
3466
3467static const struct drm_encoder_helper_funcs dce_v10_0_dig_helper_funcs = {
3468 .dpms = amdgpu_atombios_encoder_dpms,
3469 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3470 .prepare = dce_v10_0_encoder_prepare,
3471 .mode_set = dce_v10_0_encoder_mode_set,
3472 .commit = dce_v10_0_encoder_commit,
3473 .disable = dce_v10_0_encoder_disable,
3474 .detect = amdgpu_atombios_encoder_dig_detect,
3475};
3476
3477static const struct drm_encoder_helper_funcs dce_v10_0_dac_helper_funcs = {
3478 .dpms = amdgpu_atombios_encoder_dpms,
3479 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3480 .prepare = dce_v10_0_encoder_prepare,
3481 .mode_set = dce_v10_0_encoder_mode_set,
3482 .commit = dce_v10_0_encoder_commit,
3483 .detect = amdgpu_atombios_encoder_dac_detect,
3484};
3485
3486static void dce_v10_0_encoder_destroy(struct drm_encoder *encoder)
3487{
3488 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3489 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3490 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3491 kfree(amdgpu_encoder->enc_priv);
3492 drm_encoder_cleanup(encoder);
3493 kfree(amdgpu_encoder);
3494}
3495
3496static const struct drm_encoder_funcs dce_v10_0_encoder_funcs = {
3497 .destroy = dce_v10_0_encoder_destroy,
3498};
3499
3500static void dce_v10_0_encoder_add(struct amdgpu_device *adev,
3501 uint32_t encoder_enum,
3502 uint32_t supported_device,
3503 u16 caps)
3504{
3505 struct drm_device *dev = adev_to_drm(adev);
3506 struct drm_encoder *encoder;
3507 struct amdgpu_encoder *amdgpu_encoder;
3508
3509 /* see if we already added it */
3510 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3511 amdgpu_encoder = to_amdgpu_encoder(encoder);
3512 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3513 amdgpu_encoder->devices |= supported_device;
3514 return;
3515 }
3516
3517 }
3518
3519 /* add a new one */
3520 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3521 if (!amdgpu_encoder)
3522 return;
3523
3524 encoder = &amdgpu_encoder->base;
3525 switch (adev->mode_info.num_crtc) {
3526 case 1:
3527 encoder->possible_crtcs = 0x1;
3528 break;
3529 case 2:
3530 default:
3531 encoder->possible_crtcs = 0x3;
3532 break;
3533 case 4:
3534 encoder->possible_crtcs = 0xf;
3535 break;
3536 case 6:
3537 encoder->possible_crtcs = 0x3f;
3538 break;
3539 }
3540
3541 amdgpu_encoder->enc_priv = NULL;
3542
3543 amdgpu_encoder->encoder_enum = encoder_enum;
3544 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3545 amdgpu_encoder->devices = supported_device;
3546 amdgpu_encoder->rmx_type = RMX_OFF;
3547 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3548 amdgpu_encoder->is_ext_encoder = false;
3549 amdgpu_encoder->caps = caps;
3550
3551 switch (amdgpu_encoder->encoder_id) {
3552 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3553 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3554 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3555 DRM_MODE_ENCODER_DAC, NULL);
3556 drm_encoder_helper_add(encoder, &dce_v10_0_dac_helper_funcs);
3557 break;
3558 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3559 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3560 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3561 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3562 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3563 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3564 amdgpu_encoder->rmx_type = RMX_FULL;
3565 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3566 DRM_MODE_ENCODER_LVDS, NULL);
3567 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3568 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3569 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3570 DRM_MODE_ENCODER_DAC, NULL);
3571 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3572 } else {
3573 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3574 DRM_MODE_ENCODER_TMDS, NULL);
3575 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3576 }
3577 drm_encoder_helper_add(encoder, &dce_v10_0_dig_helper_funcs);
3578 break;
3579 case ENCODER_OBJECT_ID_SI170B:
3580 case ENCODER_OBJECT_ID_CH7303:
3581 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3582 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3583 case ENCODER_OBJECT_ID_TITFP513:
3584 case ENCODER_OBJECT_ID_VT1623:
3585 case ENCODER_OBJECT_ID_HDMI_SI1930:
3586 case ENCODER_OBJECT_ID_TRAVIS:
3587 case ENCODER_OBJECT_ID_NUTMEG:
3588 /* these are handled by the primary encoders */
3589 amdgpu_encoder->is_ext_encoder = true;
3590 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3591 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3592 DRM_MODE_ENCODER_LVDS, NULL);
3593 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3594 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3595 DRM_MODE_ENCODER_DAC, NULL);
3596 else
3597 drm_encoder_init(dev, encoder, &dce_v10_0_encoder_funcs,
3598 DRM_MODE_ENCODER_TMDS, NULL);
3599 drm_encoder_helper_add(encoder, &dce_v10_0_ext_helper_funcs);
3600 break;
3601 }
3602}
3603
3604static const struct amdgpu_display_funcs dce_v10_0_display_funcs = {
3605 .bandwidth_update = &dce_v10_0_bandwidth_update,
3606 .vblank_get_counter = &dce_v10_0_vblank_get_counter,
3607 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3608 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3609 .hpd_sense = &dce_v10_0_hpd_sense,
3610 .hpd_set_polarity = &dce_v10_0_hpd_set_polarity,
3611 .hpd_get_gpio_reg = &dce_v10_0_hpd_get_gpio_reg,
3612 .page_flip = &dce_v10_0_page_flip,
3613 .page_flip_get_scanoutpos = &dce_v10_0_crtc_get_scanoutpos,
3614 .add_encoder = &dce_v10_0_encoder_add,
3615 .add_connector = &amdgpu_connector_add,
3616};
3617
3618static void dce_v10_0_set_display_funcs(struct amdgpu_device *adev)
3619{
3620 adev->mode_info.funcs = &dce_v10_0_display_funcs;
3621}
3622
3623static const struct amdgpu_irq_src_funcs dce_v10_0_crtc_irq_funcs = {
3624 .set = dce_v10_0_set_crtc_irq_state,
3625 .process = dce_v10_0_crtc_irq,
3626};
3627
3628static const struct amdgpu_irq_src_funcs dce_v10_0_pageflip_irq_funcs = {
3629 .set = dce_v10_0_set_pageflip_irq_state,
3630 .process = dce_v10_0_pageflip_irq,
3631};
3632
3633static const struct amdgpu_irq_src_funcs dce_v10_0_hpd_irq_funcs = {
3634 .set = dce_v10_0_set_hpd_irq_state,
3635 .process = dce_v10_0_hpd_irq,
3636};
3637
3638static void dce_v10_0_set_irq_funcs(struct amdgpu_device *adev)
3639{
3640 if (adev->mode_info.num_crtc > 0)
3641 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3642 else
3643 adev->crtc_irq.num_types = 0;
3644 adev->crtc_irq.funcs = &dce_v10_0_crtc_irq_funcs;
3645
3646 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3647 adev->pageflip_irq.funcs = &dce_v10_0_pageflip_irq_funcs;
3648
3649 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3650 adev->hpd_irq.funcs = &dce_v10_0_hpd_irq_funcs;
3651}
3652
3653const struct amdgpu_ip_block_version dce_v10_0_ip_block =
3654{
3655 .type = AMD_IP_BLOCK_TYPE_DCE,
3656 .major = 10,
3657 .minor = 0,
3658 .rev = 0,
3659 .funcs = &dce_v10_0_ip_funcs,
3660};
3661
3662const struct amdgpu_ip_block_version dce_v10_1_ip_block =
3663{
3664 .type = AMD_IP_BLOCK_TYPE_DCE,
3665 .major = 10,
3666 .minor = 1,
3667 .rev = 0,
3668 .funcs = &dce_v10_0_ip_funcs,
3669};